JPS5974734A - Frequency divider - Google Patents

Abstract

PURPOSE:To obtain a high S/N with a small number of frequency jitters when a frequency divider is used to a PLL, by regarding the divider as a normal fixed frequency divider within an allowable range of phase errors. CONSTITUTION:An input is supplied to a variable frequency divider 10 from the 1st input 8 and switched among 3-, 5- and 7-divisions by outputs 13a and 13b and outputs 10-11. The 2nd input 9 is equal to a pulse width modulated signal. When the phase of this modulated signal advances, the dividing ratio is set at 7 and then at 3 when the phase delays. When the pulse width modulated signal has a phase within a prescribed range, the dividing ratio is set at 5. A period during which the dividing ratio is set at 3 or 7 is set equal to the output cycle of a fixed frequency divider 12. The figure 11 shows a fixed frequency divider.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a branching unit having a phase synchronization function used for data demodulation and the like.

Conventionally, the variable frequency oscillator, which is one of the components of L things have been used.

Normally, a PLL has a function of synchronizing both frequency and phase, and if frequency synchronization is required, a variable frequency oscillator must be used as a synchronization circuit. However, the frequency is synchronized by another circuit, and there are cases where only phase synchronization is required. FIG. 1 shows such an example. In the figure, l is the input, 2 is the PLI, 3 is the first multiplier, 4 is the frequency divider, 5
is the second multiplier, and 6 is the output.

FIG. 1 is an example of a demodulator for multiple modulated waves. The input is a carrier wave suppression signal, and the carrier wave is regenerated by the PLL 2 and multiplied by the input, and the output of the first multiplier 30 becomes a first demodulated signal. Furthermore, this signal changes the carrier frequency to l/
The second carrier wave frequency-divided by N is multiplied by the second multiplier 5 to obtain the final demodulated signal at the output 6.

In this case, the first carrier layer tj which is the output of PLL2
Since the input signal is generated in advance so that an accurate relationship of integral multiples is maintained between the I number and the second carrier frequency that is the output of the splitter 4, this kind of circuit configuration is sufficient. be.

However, there is a problem here if 4 is just a frequency divider. This is because when the output of PLL 2 is divided, outputs with various phases are generated depending on the division timing.
It is from. Of course, the second multiplier 5 must be supplied with a second carrier wave whose phase is also synchronized, and the branching unit 4 shown in FIG. 1 is required to have a phase synchronization function. Of course splitter 4
0, the second one using a conventional variable frequency tII number oscillator.
A method using 0PLL is also considered. FIG. 2 is an example of such a configuration. In the figure, 7 indicates the 20th PLL. However, in the method of FIG. 2, the 20th PLL 7 inherently has frequency instability as long as it has a variable frequency oscillator. In addition to the instability of PLL2, it has the disadvantage of further deteriorating the output F3/N'r.

An object of the present invention is to provide a divider that can be regarded as a normal fixed divider within an allowable phase error, has lower frequency jitter, and can obtain a higher 8/N Y than when using a PLL. It is.

In order to achieve the above object, the divider according to the present invention includes a variable frequency divider with a variable division ratio, a division ratio control circuit that determines the division ratio, and a division period control circuit that controls the division period. The gist is every time you have W. According to an advantageous embodiment of the invention, at least three division ratios are available and are selected by a division ratio control circuit, the division ratio control circuit being different from the input to be divided (the first input). It has a second input, and the signal input to the second input determines whether the phase of the branch output is appropriate. If the phase is ahead, the division ratio is increased, and if it is delayed, the division ratio is increased. decrease.

The frequency division period control circuit causes the variable frequency division operation to be performed intermittently.

FIG. 3 is a block diagram showing the configuration of a branching device according to the present invention;
FIG. 4 is a specific circuit diagram of the branching device of the present invention. Third
In the figure, 8 is a first input, 9 is a second input, 10 is a variable frequency divider, 13.12 is a fixed frequency divider, 13 is a control signal generator, and 14 is an output. The fixed frequency dividers 13 and 12 may be of widely used frequency dividers, and therefore will not be described in detail here.

Reference numbers in Figure 4 that are common to Figure 3 refer to the same parts as the same numbers in Figure 3. 1o-1 is like 74 LS 90 N made by Texas Instruments 11 B
CD force fy y It, 10-2.10-3.10-
7 is an inverter, 10-4.10-5.10-6.10-8
．． 10-9.1O-10G'! NAND goo), 10-
13c is an exclusive OR gate, 10-12 is a Dm flip-flop, 13-■ is an operational amplifier, 13-2.13-.
3 is a voltage comparator.

First, the variable division divider, which is the central part of the present invention, will be explained. The variable frequency divider 10 has the function of switching the frequency to 3, 5, or 7 depending on the outputs of 13a and 13b and the output of 10-11. Its operation is determined by how it is connected to the QB, QO output, and port o(2) inputs of the IJcD counter 10-1. The truth table is shown in Part 1.懺中, ■J means low logic level, 11 means high logic level, X means) iK is irrelevant.

The Tables 13a and 13b inputs determine the division ratio -, 1
The o-1J output functions as a gate signal for frequency division operation.

In other words, when the output is 10-11, the division ratio is 13a.
.

13 b is 5 regardless of K, and 10-H output is H
The division ratio changes only when .

The relationship between the outputs 13a, 13b, and 10-H and the frequency division ratio will be explained in more detail.

The second human power 9 is a pulse width modulation signal, and its DC component changes depending on the phase of the output second carrier wave. The ideal blood flow component is the power supply voltage V. 00 cows, i.e. vCc/2
It is. The operational amplifier 13-1 is a third-order low-pass filter, and extracts the DC component at a frequency W-W sufficiently lower than the lower limit of the signal component of pulse width modulation. Voltage ratio V device 1
3-2 and 13-3, the extracted DC component is (vc
c/2) ±ΔV.

When the phase of the output second carrier wave advances, the pulse width modulated DC component becomes smaller than Vcc/2, and conversely, when it lags, it becomes larger. The output 13n of the voltage comparator 13-2 becomes H when the DC component becomes smaller than (Vcc/2)-ΔV. The output 13b of the voltage comparator 13-3 has a DC component (
vcc/2) jii When it becomes larger than V, it becomes H.

To summarize the above operations, the carrier wave phase advances → the DC component of pulse width modulation (Vc
c / 2 ) - Δ■ or less and 1 → Voltage comparator 13 -
The output of 2 becomes H → the frequency division ratio becomes 7, and the phase of the carrier wave is delayed.

The phase of the carrier wave is delayed → the DC component of pulse width modulation becomes (V
cc/2)+ΔV or more → Voltage comparator 13-
The output of 3 becomes H → the frequency division ratio becomes 3 and the phase of the carrier wave is advanced.

The DC component of pulse width modulation is (vcc/2) ±Δν
If it is within the range, both 13a and 13b are L, and the division ratio is 5. Naturally, when the frequency division ratio of the fixed frequency divider 11 is N1, the first carrier tlI frequency f1 and the second carrier frequency fz Cfs, fz are both determined at the stage of generating the human signal. The following equation holds between

Exclusive i! 1iil buried sum game), the output of 10-IT is the period in which the frequency division ratio is changed to 3 or 7 (division period)
This is the gate signal that controls the Its period is fixed frequency divider 1
It is a signal with an extremely small duty cycle, and the width is equivalent to one cycle of the output of the inverter 10-70. Fixed division period 120 You can reduce the division ratio or add an inverter 1O- to the clock input of the D-type flimp prop 10-12.
If a signal with a longer period than the output of 7 is used, the control amount can be increased, but if the control amount is increased too much, there is a risk of oscillation.

FIG. m5 is a block diagram showing an application example corresponding to FIG. 1 using the frequency divider according to the present invention, and 15 indicates the frequency divider according to the present invention.

As explained above, according to the present invention, by setting (Vcc/2) ±Δ■, which corresponds to the allowable phase error, the overall division ratio does not change within the allowable value, and a stable output without frequency jitter is achieved. can be obtained. In addition, when converting to ■C, there is an advantage that there are fewer external parts.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional demodulator for multiple modulated waves; FIG. 2 is a block diagram showing the configuration of a modification of the device shown in FIG. 1; FIG. 3 is a frequency divider according to the present invention. FIG. 4 is a specific circuit diagram of the device shown in FIG. 3, and fifth is a block diagram showing an application example corresponding to FIG. 1 using a branching device according to the present invention. . ■...Input, 2...PLL, 3...First multiplier, 4...Divider, 5...Second multiplier, 6...Output, 7... 20th PLL, Z...1st input, 9.
...Second input, IO...Variable frequency divider, 10-1...
・B CD calendar, 10-2. 10-3. 10-
7... Inverter, 10-4.10-5. to-6,
to-s, 10-9. 10-10...NAND
Gate, 10-11... Exclusive weaving gate, 10-
12... D-type frimbflop, II, 12... Fixed frequency divider, 13... Control signal generator, 13-1...
Enlarger, 13-2.13-3...Voltage comparator,
14... Output, 15... Branching device according to the present invention. Figure 1 t7 Figure 3 Figure 5

Claims (1)

[Claims] Frequency divider. (The divider according to claim m1, characterized in that at least three 27 frequency division ratios are obtained and selected by the 1 division ratio control circuit. (3) The division ratio control circuit is a frequency divider. The desired input (first input) has a second input Y called jI4, and the signal given to the second input determines whether the phase of the divided output is appropriate, and whether the phase is advanced or not. The branching device according to any one of the preceding claims, characterized in that if there is a delay, the branching ratio l is increased, and if there is a delay, the branching ratio is decreased. (4) The branching period control circuit is variable. A frequency divider according to any one of the preceding claims, characterized in that the frequency division operation is performed intermittently.