JPS5969793A - Matrix panel driver - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for generating a shift clock applied to a shift register used in a matrix type display device iJt or an image pickup device's nIb circuit.

FIG. 1 shows an example of an IJ type display device. While one scanning electrode is selected by the vertical drive unit 3, a display signal applied to the terminal 5 is applied to the horizontal switching element 4, which is sequentially selected by the horizontal drive unit 2, to the display panel l. So-called point-sequential scanning is performed in which the voltage is applied to each pixel. As the horizontal drive section 2 and the vertical section V section 3, conventional drive devices shown in +<(2 and 1) are installed.This operation will be explained below using the waveform diagram of each part in Fig. 3. do.

12 and 13 are D-type latches that input data at the rising edge of the clock, and 10 is a shift register that shifts data at the rising edge of the clock. Terminal 16 is a shift clock application terminal like terminals 1 and 9 in FIG. Terminal 11 is the same as terminals 6 and 8 in FIG. 1, and is a display start signal pulse application terminal.

Display start pulse of waveform ■ on terminal 11, waveform ■ on terminal 16
When the clock is input, the D-type latch 12 outputs a waveform that rises in synchronization with the rise of the clock. Upon receiving this output, the D-type latch 13 outputs a waveform (2) that rises in synchronization with the rising edge of the next clock. D type latches 12 and 13
In response to the output of the waveform 0, the NOR gate 14 obtains an output that is a differential of the rising edge of the waveform 0 and is synchronized with the clock pulse 0, as shown in the waveform.

Next, when the reverse phase clock pulse waveform obtained by passing the waveform (2) through the inverter 15 is added to the shift register 10, a waveform C in which pulses are sequentially sent in synchronization with the clock is output. This output is used to form an electric signal that drives the display panel shown in FIG. Here, shift register 1
By adding a clock pulse of opposite phase to 0, the input pulse of the shift register is read in the exact middle of 0 to ensure reliable operation.

In the electric device shown in FIG. 2, the shift clock is constantly supplied from the terminal 16 and added to the shift register. If a matrix type display device is used for television display, it is thought that the number of horizontal and vertical pixels will need to be about 200 or more, and therefore the output of the shift register forming the drive circuit will also need to be about 200 or more. If, for example, a clock with a horizontal clock frequency of 5Ml12, which is essential for television display, is to be applied to a shift register with such a large number of stages, the power consumption cannot be ignored.

Above, I have talked about the U-shaped display device.
The same applies to a matrix type imaging device similar to that shown in FIG.

An object of the present invention is to provide a matrix panel drive device that alleviates the drawbacks of the above-mentioned prior art and achieves a reduction in power consumption using additional devices. The present invention is characterized in that no clock pulses are applied to the shift register during a period not necessary for display, such as a retrace period during display.

An embodiment of the present invention is shown in FIG. The same or equivalent parts as in the conventional example shown in FIG. 2 are given the same reference numerals. Fourth
The illustrated embodiment differs from the conventional example shown in FIG. 2 in that a NOR gate 20 is used instead of the inverter 150, and the clock input to the shift register 10 is controlled by the output of the SR latch 1). This operation will be explained below using the waveform diagram of each part in FIG.

When the display start pulse waveform ■ is input to the terminal 11 and the clock waveform is input to the terminal 16, as explained in the conventional example, N
The waveform is output from the OR gate 14 and applied to the input terminal of the shift register 10. Here, it is assumed that a logic 0 level is input to terminals 18 and 19. When the shift register 10 starting pulse of waveform (2) is applied to the SR latch 1f, the SR latch is set and the waveform (2) is output.

Therefore, shift register 10 Fc, clock waveform C
and the NOR of the waveform ■. The reverse phase clock shown by the waveform ■ is input. Therefore, as in the conventional example, a waveform (2) is obtained in which pulses are sent sequentially in synchronization with the clock. Here, the SR latch IPI is reset with the output waveform 0 of the first stage of the foot next to the final stage of the drive output/1i1, which is not found in the conventional example. In other words, the waveform (no is output, the SR latch output waveform ■ rises,
/The clock waveform @ applied to the /ft register lOK stops. Then, the display start pulse waveform comes next, and the waveform ■
Until the waveform 1 rises, that is, during the call 1 period, the shift register 10 is not applied with a clock, and is in a static state, reducing power consumption.

Note that the terminal 18 is designed to improve the startup characteristics of the device by applying logic l for a while (several tens of milliseconds or less) after the power is turned on, inputting a clock to the shift register, and clearing its contents. . In addition, when the device shown in FIG. 4 is used, for example, in the horizontal drive unit 2 shown in FIG. This is added to stop the 10 clock and further reduce the extinction force. In this case, the signal given to the terminal 19 is specifically
If the device shown in Fig. 4 is also used, the waveform
It may be applied to the terminal 19 used for.

Next, another embodiment of the present invention is shown in FIG. Parts that are the same or equivalent to those that have appeared so far are given the same reference numerals. In this embodiment, the clock pulse is obtained by an oscillator that oscillates in synchronization with the display start signal applied to the terminal 11), and this oscillator itself is controlled to prevent unnecessary lock pulses from being generated. be. This operation will be explained using the waveform diagram of each part in FIG.

When the display start pulse 0 is applied to the terminal 11, the SR latch 22 is set, and the waveform ■ is output.

According to waveform (2), the oscillator 21 starts oscillating, and a clock waveform (7), an anti-phase clock waveform [present], is obtained.

When the reverse phase clock waveform [present] rises, the shift register 10 operates, and the shift pulse waveform remaining in the W+1 stage falls, and the SR latch 22 is completely set, υ, waveform ■ rises and thereafter, even if waveform (2) becomes logic 0, waveforms (2) and (2) do not change. The subsequent operation is similar to the conventional example, in which the waveform is synchronously differentiated using the D-type 7-lip 70 tube 2a13 and the IVOR gate 14 to obtain a waveform, which is input to the shift register IOK. In this way, waveform 0 is obtained in which pulses are sent sequentially in synchronization with the clock. After 1, the SR latch 22 is reset and the oscillator 21 is stopped by the 11th stage output, which is not conventional. Until the next display start pulse is sent, that is, the waveform During periods of static state, power consumption is reduced.

Terminal 18II'i has the same function as that in Fig. 4,
When the embodiment shown in FIG. 6 is used in the horizontal drive section 2, the oscillator 21 is stopped during the vertical non-display period to further reduce power consumption.

Next, we will explain how much power consumption is reduced by stopping the clock. Here, a case will be considered in which the present invention is applied to a horizontal drive unit, taking a television display as an example. When cHo5 is used as a drive circuit with the aim of reducing power consumption,
Since the power consumption is almost proportional to the clock frequency, it is negligible in a static state, compared to the large power consumption for high-speed operation (approximately 5 MII).

Therefore, by determining the clock stop period of 1 horizontal block, the effect of reducing power consumption can be seen.

Maximum information member is 5λ for l water period 6 to 5μ♂acr1c
Since it is Fflttee, the power consumption reduction due to clock stop is -17%.

Furthermore, even in the vertical non-display period by the terminal 18, if the horizontal clock is stopped, 26 scanning lines per field are generated.
Since the maximum amount of information is 241 out of 2.5 lines, the effect of reducing power consumption is 124 lines. Furthermore, if the maximum information amount of display light is 90eI6, it becomes -38%.

As described above, according to the present invention, in addition to the conventional example,
By using a simple additional circuit, locking can be stopped without the need for selection, and power consumption can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a general configuration diagram of a matrix panel and its drive device, Fig. 2 is a block diagram of a conventional drive device, Fig. 3 is a waveform diagram of its platform, and Figs. 4 and 6 are diagrams of the present invention. A block diagram of the vortex drive device of one embodiment, FIG. 5 and FIG. 1 are waveform diagrams of various parts of FIG. 4 and FIG. 6, respectively. 1... Matrix panel, 2... Water XV drive unit,
3...Vertical drive unit, 4...Horizontal switch, lO・
...Shift register, 1%13...D type latch,
1) 22..., SR latch, 21...synchronous oscillator, 23...with reset! ! ! latch. Fang 1 Ao 2 Ao Sai 3 Kuchi 4 Koku/7 O 5 Koku O 20 □-■ Total 7 Kuchi O'

Claims (1)

[Claims] A matrix panel driving device comprising a matrix panel of one column (X rows) and a shift register for driving the matrix panel, and stopping a shift clock signal applied to the shift register when the shift register operation is unnecessary.