JPS5967680A - Photo bi-stable element - Google Patents
Photo bi-stable elementInfo
- Publication number
- JPS5967680A JPS5967680A JP57178757A JP17875782A JPS5967680A JP S5967680 A JPS5967680 A JP S5967680A JP 57178757 A JP57178757 A JP 57178757A JP 17875782 A JP17875782 A JP 17875782A JP S5967680 A JPS5967680 A JP S5967680A
- Authority
- JP
- Japan
- Prior art keywords
- mesa stripe
- layer
- type
- active layer
- grooves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 18
- 230000003287 optical effect Effects 0.000 claims description 12
- 239000013078 crystal Substances 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 125000005842 heteroatom Chemical group 0.000 abstract description 2
- 230000000903 blocking effect Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000005253 cladding Methods 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 102220084100 rs769053886 Human genes 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 238000010025 steaming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、半導体を用いた、光論理回路の主要構成要
素でらる光双安定素子に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an optical bistable element using a semiconductor and which is a main component of an optical logic circuit.
光論理回路は、従来の電子論理回路よりも高速の動作が
ロエ能になる新しい論理回路として期待され、基礎的な
検討がはじめられている。光論理回路の主要な構成要素
のひとつに、光双安定素子があジ、f!にの構成が考え
られているが、半導体材料を用いるものが、その高速性
を最も良く生かせるものとして注目されている。その中
に、二重へテロ(IJH)構造の半導体レーザの′電流
注入部が、その共振器軸方向に途切れ途切れになるよう
にして、この方向に不均一な゛電流分布を形成し、注入
1流が小さい部分での過飽和吸収効果により光双安定動
作を実現したものがある。これについては、何口式によ
りエレクトロニクスレターズ(Electro−nic
s Letters)誌、第17巻167Kから168
魔に報告された論文に詳しい。この構造の素子により光
双安定動作が実現されたが、この素子は電流注入の幅を
限定して横モードをtlj制御するいわゆゆるプレーナ
型の構造のために、横モードが不安定であるばかりでな
く、発成しきい値が高く、室温での動作が困難であり、
実用的な素子とは言い難い。Optical logic circuits are expected to be new logic circuits capable of operating at higher speeds than conventional electronic logic circuits, and fundamental studies have begun. One of the main components of optical logic circuits is an optical bistable element. Several configurations have been considered, but one using semiconductor materials is attracting attention as the one that can best utilize its high-speed performance. The current injection part of the double hetero (IJH) semiconductor laser is discontinuous in the direction of the cavity axis, forming a non-uniform current distribution in this direction. Some devices have achieved optical bistable operation due to the supersaturation absorption effect in areas where the first flow is small. Regarding this, please refer to the Electronics Letters (Electro-nic Letters)
Letters), Volume 17, 167K to 168
I am familiar with the papers reported to the devil. Optical bistable operation was achieved using a device with this structure, but the transverse mode is unstable because this device has a so-called planar structure that controls the transverse mode by limiting the width of current injection. Not only that, but the generation threshold is high and operation at room temperature is difficult.
It is hard to say that it is a practical element.
この発明の目的は、室l晶での低電流動作が可能な光双
安定素子を提供することにある。An object of the present invention is to provide an optical bistable element capable of low current operation using a chamber crystal.
この発明によれば、活性層にまで達する2本のほぼ平行
な溝で形成した活性層を含むメサストライプを少なくと
も前記メサストライプの上部の半導体層とは異なる導電
型の半導体層を含む半導体層で埋め込んだ埋め込みへテ
ロ構造半導体レーザにおいて、前記!荷の前記メサスト
ライプと反対の1itllの側面の少なくとも一部が凹
凸をなし、かつ前記メサストライプの上部が部分的に前
記異なる導電型の半導体層でおおわれていることを特徴
とする光双安定素子が得られる。According to this invention, the mesa stripe including the active layer formed by two substantially parallel grooves reaching the active layer is formed of a semiconductor layer including at least a semiconductor layer of a conductivity type different from the semiconductor layer above the mesa stripe. In the buried buried heterostructure semiconductor laser, the above! An optical bistable device characterized in that at least a part of the side surface of the substrate opposite to the mesa stripe is uneven, and the upper part of the mesa stripe is partially covered with the semiconductor layer of the different conductivity type. is obtained.
以下図面を参照して本兄明を詳しく説明する。The present invention will be explained in detail below with reference to the drawings.
第1図はこの発明の第1の実施例の活性層の形状を示す
る平面+6?而図、第2図は第1図のA−A/。FIG. 1 is a plane +6? showing the shape of the active layer of the first embodiment of the present invention. Figure 2 is A-A/ of Figure 1.
B−B/断面の断面図をそれぞれあられす。この実施例
は、プレーナ型の埋め込みへテロ構造の、活性層を含む
メサストライプを形成する2本の溝のメサストライプと
は反対側の側面が部分的に狭くなっている形状にしたも
のである。プレーナ型の埋め込みへテロ構造半導体レー
ザは、活性層を含むメサストライプをpおよびn型半導
体層で埋め込んだもので、これについては北村らにより
出願中の発明、特願昭56−166666号明細卦に詳
しい。この実m例は以下のようにして製作される。Here are the cross-sectional views of the B-B/section. This embodiment has a planar buried heterostructure in which two grooves forming a mesa stripe including an active layer have a partially narrowed side surface on the opposite side from the mesa stripe. . A planar type buried heterostructure semiconductor laser is one in which a mesa stripe including an active layer is buried with p and n type semiconductor layers, and this is disclosed in the invention pending by Kitamura et al. I am familiar with This example is manufactured as follows.
まず通常の液相成長法により、n−1,Pの板10上に
、 n−10Pのバック7層IllノンドープのInU
aAsPの活性層12+p−1nPのクラッド層13を
形成したIJH基板に、フォトレジスト塗布し、通常の
フォトリソグラフィーυエツチングにより、第1図に示
した形状のウェハーを製作する。First, by a normal liquid phase growth method, an n-10P back 7 layer Ill non-doped InU was formed on an n-1,P plate 10.
A photoresist is coated on an IJH substrate on which an aAsP active layer 12+p-1nP cladding layer 13 is formed, and a wafer having the shape shown in FIG. 1 is manufactured by ordinary photolithography and v-etching.
続いて、このウェハーを成長炉に入れて2回目の結晶成
長を行なう。まず、 p−10Hの第1の電流阻止層
14+n−1nPの第2の電流阻止層15を形成し、続
いてp−1,Hの埋め込み層15+p−1nGaAsP
のキャップIfl17を形成する。弔1図に示したよう
に、活性層を含むメサストライプ20を形成するための
2本の溝21は、メサストライプ20の側で@線、メサ
ストライプ20から離れた側ではとびとびに出たりひっ
こんだりして、幅の広い部分20aと狭い部分20bを
有している。Subsequently, this wafer is placed in a growth furnace and a second crystal growth is performed. First, a first current blocking layer 14 of p-10H + a second current blocking layer 15 of n-1nP is formed, and then a buried layer 15 of p-1,H + p-1nGaAsP is formed.
A cap Ifl17 is formed. As shown in Figure 1, the two grooves 21 for forming the mesa stripe 20 including the active layer are @ lines on the side of the mesa stripe 20, and protrude and retract at intervals on the side away from the mesa stripe 20. Thus, it has a wide portion 20a and a narrow portion 20b.
2回目の結晶成長において、メサストライプ20を形成
する溝21の幅の広い部分20aでは、第2図(a)に
示したようにして、第1.第2の電流阻止層14115
はメサストライプ20の上には成長しない。一方、溝2
1の幅の狭い部分20bでは、溝21内を弔lの電流阻
止層14が埋めてし゛まうために、第2の電流阻止層1
5を成長する直前のメサストライプ20附近の形状が平
坦になってしまうので、第2の電流阻止層15はメサス
トライプ20の上部で途切れることがなく全体をおおっ
てしまう。このような結晶成長の様子については前出の
特願昭56−166666号明細丼に詳しい。In the second crystal growth, in the wide portion 20a of the groove 21 forming the mesa stripe 20, as shown in FIG. 2(a), the first. Second current blocking layer 14115
does not grow on mesa stripe 20. On the other hand, groove 2
In the narrow portion 20b of the first current blocking layer 14, the second current blocking layer 14 fills the inside of the groove 21.
Since the shape near the mesa stripe 20 immediately before the growth of the mesa stripe 5 becomes flat, the second current blocking layer 15 covers the entire mesa stripe 20 without being interrupted at the upper part thereof. Details of such crystal growth can be found in the above-mentioned Japanese Patent Application No. 166666/1983.
結晶成長終了後、キャップ層17の表面にAu−Znの
p側峨極31を、基板lOの表向にAu−(je−Ni
のn側電極32を蒸涜により形成しアロイしてウェノ・
−の製作を終了する。このウェノ・−を通常のへき開法
でメサストライプ20に直角に共振器面を形成し素子が
製作される、この素子のp III電極31を正に、n
側電極32を負にバイアスすると、この素子は電流入力
あるいは光入力に対して安定な2準位を持つ光沢ゲ定素
子として鋤く。それは次の理由による。すなわち、溝幅
の広い部分20aでは、従来の埋め込みレーザと同様に
、活性層12に電流が注入されるのに対して、溝幅の狭
い部分20bでは、n−10)’の第2の電流阻止層1
5がメサストライプ20の上部も含めて全面にわたって
形成されているので、活性層12に電流が注入されるこ
とはない。そのため、共振器軸方向に不均一な電流注入
がされることになり、共撮庸中に可飽和吸収部分と利得
部分が形成され、光双安定素子が実現される。この素子
は従来の光双安定素子と異なり、活性層が半導体層中に
埋め込まれたいわゆる埋め込み構造を有しているので、
室温で容易に低い動作電流で1動かせることができる。After the crystal growth is completed, an Au-Zn p-side electrode 31 is formed on the surface of the cap layer 17, and an Au-(je-Ni
The n-side electrode 32 is formed by steaming and alloyed.
- Finish the production of. A device is fabricated by forming a resonator surface perpendicular to the mesa stripe 20 by using a normal cleavage method on this wafer.
When the side electrode 32 is negatively biased, the device functions as a two-level brightness-gazing device that is stable to current or light input. This is due to the following reason. That is, in the wide groove width portion 20a, a current is injected into the active layer 12, similar to the conventional buried laser, whereas in the narrow groove width portion 20b, a second current of n-10)' is injected into the active layer 12. Blocking layer 1
5 is formed over the entire surface including the upper part of the mesa stripe 20, no current is injected into the active layer 12. Therefore, a non-uniform current is injected in the axial direction of the resonator, and a saturable absorption part and a gain part are formed during co-imaging, and an optical bistable element is realized. Unlike conventional optical bistable devices, this device has a so-called buried structure in which the active layer is embedded in a semiconductor layer.
It can be easily operated at room temperature with low operating current.
この実施例では@蛋しきい1直が約40mAであり、l
oOmA以下の低電流動作が可能であった。In this example, @tea threshold 1 shift is approximately 40 mA, and l
Low current operation of less than oOmA was possible.
以上説明したように、この発明では、メサストライプ上
及びその周辺の溝中の結晶成腿の様子の考察にもとづき
、プレーナ形埋め込み半導体レーザの溝形状をメサスト
ライプの反対側の側面が部分(」ツに出たり入ったりし
Cいる形状にしてs 4幅の央い部分のメチストライブ
の上に、異なる導電型の半等体、I曽を積層させること
により、不均一直流分布を友現し、光双安定素子を得て
いる。この実施列の素子の寸法は、メサストライプ20
の幅が25μm+溝福の広い部分20aの幅が7μ+1
1+央い部分20bの幅が3μm、線幅の広い部分20
aの長さが40μm + 決い部分20bの長さが10
μmである。結晶成長の様子は成長方法や成4を条件等
により大幅に変わるので、それらとともに適切な寸法を
採用すべきことは言うまでもない。また、この実施例で
は溝幅の広い部分20aと狭い部分20bの長さの比を
4:1にとったがこの1直に限定されるものではない。As explained above, in this invention, based on consideration of the state of crystal growth in the groove on and around the mesa stripe, the groove shape of the planar buried semiconductor laser is changed so that the side surface opposite to the mesa stripe is By stacking semi-isomers of different conductivity types, I-stripes, on top of the methystrives in the central part of the s4 width, a non-uniform DC distribution can be realized, and light A bistable element is obtained.The dimensions of the element in this implementation row are as follows: mesa stripe 20
The width of the groove is 25μm + the width of the wide part 20a of the groove is 7μ + 1
1 + central part 20b width is 3 μm, wide line width part 20
The length of a is 40μm + the length of the end portion 20b is 10
It is μm. Since the appearance of crystal growth varies greatly depending on the growth method, growth conditions, etc., it goes without saying that appropriate dimensions should be adopted in conjunction with these factors. Further, in this embodiment, the length ratio of the wide groove portion 20a to the narrow groove portion 20b is set to 4:1, but it is not limited to this one length.
第3図!第4図は、この発明の第21第3の実施例の溝
形状ケ示すための平面図をあられす。第2の実!血例は
、溝幅の侠い部分20bを素子の中央部分に配置ii
Lだものである。l君3のバ倫+り+I ?ま、溝幅の
広い部分20aと狭い部分20bをそれぞれ一カ所つつ
で構成したものである。これらの央剣例においても、室
温で低電流動作可能なメC双安定素子が得られた。以上
の実施例において、半導体材料はL H)’ / l
n (j B A S P系に限られずG3As/AI
UaAs系等他のものであっても醍い。また、凹凸のあ
る溝1Ijl1面は図のように断続的である必媛はなく
、なめらかに変化しているものであっても良い。Figure 3! FIG. 4 is a plan view showing the groove shape of the twenty-first third embodiment of the present invention. Second fruit! In the example, the narrow groove width portion 20b is placed in the center of the element ii
It's L. L-kun 3's barun+ri+I? Well, it is constructed by having one wide groove portion 20a and one narrow groove portion 20b. In these examples as well, MeC bistable devices capable of low current operation at room temperature were obtained. In the above examples, the semiconductor material is L H)' / l
n (j B A SP Not limited to G3As/AI
Other materials such as UaAs are also suitable. Furthermore, the uneven grooves 1Ijl1 surface need not be discontinuous as shown in the figure, but may be smoothly changing.
第1図はこの発明の第1の実施例の活性層を営む而の平
面図、第2図はその断面図、第3図、第4図はこの発明
の來2.第3の実施例の活性層を含む面の平面図をそれ
ぞれあられす。
図において、10・・・・・・基板、11・・・・・・
バッファ1偕、12・・・・・・γ占1生)曽、13・
・・・・・クラッド層、1415・・・・・・g(流阻
止層、16・・・・・・埋め込み層、20・・・・・・
メサストライプ、21・・・・・・溝、20a・・・・
・・溝幅の広いr、1;分、20b・・・・・・同法い
部分をそれぞれあられす。
ヱ〕
″、
−40:
恭! 凹
32FIG. 1 is a plan view of the active layer of the first embodiment of the present invention, FIG. 2 is a sectional view thereof, and FIGS. A plan view of the surface including the active layer of the third embodiment is shown. In the figure, 10...substrate, 11...
Buffer 1, 12... γ 1st life) Zeng, 13.
...Clad layer, 1415...g (Flow prevention layer, 16...Buried layer, 20...
Mesa stripe, 21...groove, 20a...
...The wide groove width r, 1; minute, 20b...The same wide part is covered respectively.ヱ〕 ″, -40: Kyou! Concave 32
Claims (1)
大きく屈折率が小さく互いに異なる導電型の第1・第2
の半導体層を前記活性層に達するほぼ平行な2本の溝で
形成したメサストライプ“を少なくとも前記メサストラ
イプの上面の前記半導体層と異なる導電型の第3の半導
体層を含む半導体層で岨め込んだ埋め込みへテロ構造半
導体レーザにおいて、前記溝の前記メサストライプの側
とは反対の側の側面の少なくとも一部が凹凸をなし、か
つ前記メサストライプの上部が部分的に前記第3の半導
体層でおおわれていることを特徴とする光双安定素子The active layer and the first and second layers sandwiching the active layer and having a larger energy gap, a smaller refractive index, and different conductivity types.
A mesa stripe formed of two substantially parallel grooves reaching the active layer is formed by at least a semiconductor layer including a third semiconductor layer having a conductivity type different from that of the semiconductor layer on the upper surface of the mesa stripe. In the buried heterostructure semiconductor laser, at least a part of the side surface of the trench opposite to the mesa stripe is uneven, and the upper part of the mesa stripe is partially covered with the third semiconductor layer. An optical bistable element characterized by being covered with
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57178757A JPS5967680A (en) | 1982-10-12 | 1982-10-12 | Photo bi-stable element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57178757A JPS5967680A (en) | 1982-10-12 | 1982-10-12 | Photo bi-stable element |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5967680A true JPS5967680A (en) | 1984-04-17 |
JPS641075B2 JPS641075B2 (en) | 1989-01-10 |
Family
ID=16054062
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57178757A Granted JPS5967680A (en) | 1982-10-12 | 1982-10-12 | Photo bi-stable element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5967680A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60239083A (en) * | 1984-05-11 | 1985-11-27 | Nec Corp | Optical bistable semiconductor laser |
US5543355A (en) * | 1994-04-18 | 1996-08-06 | Nec Corporation | Method for manufacturing semiconductor laser device having current blocking layers |
-
1982
- 1982-10-12 JP JP57178757A patent/JPS5967680A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60239083A (en) * | 1984-05-11 | 1985-11-27 | Nec Corp | Optical bistable semiconductor laser |
US5543355A (en) * | 1994-04-18 | 1996-08-06 | Nec Corporation | Method for manufacturing semiconductor laser device having current blocking layers |
Also Published As
Publication number | Publication date |
---|---|
JPS641075B2 (en) | 1989-01-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4791647A (en) | Semiconductor laser | |
JPS5967680A (en) | Photo bi-stable element | |
JPS61289689A (en) | Semiconductor light emission device | |
JPS61102086A (en) | Semiconductor laser | |
JPS6034089A (en) | Optical bistable semiconductor laser | |
JPS62296490A (en) | Semiconductor laser device | |
JPS6297384A (en) | Semiconductor laser device | |
JPS5967679A (en) | Photo bi-stable element | |
JP4024319B2 (en) | Semiconductor light emitting device | |
JPS5944886A (en) | Photo bistable element | |
JPS6239088A (en) | Semiconductor laser | |
JPH01215087A (en) | Semiconductor light emitting device | |
JPH0385785A (en) | Semiconductor laser element | |
JPS5871681A (en) | Semiconductor laser element | |
JPH0228388A (en) | Semiconductor laser element | |
JPH01309393A (en) | Semiconductor laser device and its manufacture | |
JPS61244082A (en) | Semiconductor laser device | |
JPS6355875B2 (en) | ||
JPH0233988A (en) | Semiconductor laser | |
JPS63111687A (en) | Manufacture of optical semiconductor element | |
JPS60163485A (en) | Photo bi-stable semiconductor laser | |
JPS60119787A (en) | Semiconductor laser element and manufacture thereof | |
JPS63164385A (en) | Semiconductor laser device | |
JPH03116991A (en) | Semiconductor laser device | |
JPH047887A (en) | Semiconductor laser device |