JPS5966764A - Picture rotating system - Google Patents

Abstract

PURPOSE:To obtain a rotating picture congruent to an original picture in high speed, by taking the block size at block transfer as 1/tantheta each for longitudinal and lateral direction and performing approximation of integral number of a memory address skip length with the fraction discarding. CONSTITUTION:An address control section generates alternately a transferred and transferring address for attaining data transfer. A parameter is given to registers 601-608 of the address control section and a value of (address initial value -1) is given to a register 617. A counter 611 keeps count-up until the content is equal to that of the register 605 and an address data outputted onto an address bus 646 is incremented by one each. The operation is continued until the content of the counter 614 is equal to the content ltantheta of the register 608, and when they are equal, the final address data is transmitted and an end signal 516 is outputted.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an image rotation method9, and in particular to a rotation method suitable for rapidly obtaining a rotated image that is congruent with an original image. , which can generally be expressed by coordinate transformation. Here, (X, y) are the two-dimensional coordinates of the original image, (X, Y) are the two-dimensional coordinates of the rotated image, and θ is the rotation angle. FIG. 1 shows the direction of jiiiI symbol θ. In the figure,
(a) is the original image, (b) is the rotated image, 0. O indicates the origin of the original image and the rotated image, respectively. In rotation processing, (
The method of calculating addresses pixel by pixel according to formula 1) has the disadvantage that the processing time is long.

In order to completely eliminate this drawback, the applicant of the present invention has already proposed a rotation method using two-dimensional block transfer (% Application No. 57-1020
68; image rotation method). In one embodiment of the invention described in this application, the following transfer control is executed.

1) The size of the block is 1/θ pixels vertically and 1/θ pixels horizontally.

2) Insert blank lines between blocks at the transfer destination. A blank line is
There is one row per 1/θ21III element vertically.

Although this method is fast, the rotational coordinate transformation takes a long time.
). For this reason, compared to the rotation method in which address calculation is performed pixel by pixel using method (1), the rotated image has the disadvantage that the rotated image is enlarged in a similar form with an enlargement ratio of 1+02 compared to the original image.

[of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for obtaining a transformation 1 which is congruent with a cause 1 image without reducing the processing speed.

[Summary of the invention]

Features of the present invention The size of the block must be 1. /lanθ pixels, 1/janθ pixels horizontally.

2) Assign blank lines between blocks at the transfer destination. Go away,
There is one row per pixel where vertical<cos θ/(1-cos θ).

3) At the transfer source, assign all blanks between blocks. The empty stab is
One column is set for horizontal cos θ/(1-cos θ) pixels.

The present invention will be explained in detail using FIG. In the figure, (C)
is the original image, (d) is the rotated image, ■~■ is the original image block, ■'-■' is the rotated image block [7 soku, A is (a) Sθ/
(Length of 1-cosθ9 pixels, ■3 is 1/ta
The length of nθ pixels, C is the length of one pixel, and the diagonal line is added (7
The blank lines indicate blank lines and blank lines. The rotation process is (0)
This is realized by pixel transfer from to (d). Here, the coordinate transformation representing the single rotation method of transferring blocks 1 to 2 to blocks ' to 2', respectively, is equivalent to equation (1).

0], then the pixel correspondence in the transfer described in - is as follows. This is equivalent to equation (1). Therefore, the rotated image obtained by this rotation method is congruent with the original image and has no shape distortion.

[Embodiment J of the Invention An embodiment of the invention will be described below. First, images are stored in one-dimensional memory in rask units! It is assumed that you have done so. Referring to FIG. 3, the relationship between a pixel position on an image and a one-dimensional memory address for storing it will be explained. In the figure, (e
) is an image, and (f) is a schematic drawing of the memory that stores it. The memory (f) is addressed in ascending order from the left. 301 and 302 represent partial diagrams, and 303 and 304 represent continuous memory areas. The figure is partial diagram 3
01 indicates that the partial diagram 302 is stored in the memory area 303, and the partial diagram 302 is stored in the memory area 304.

Under the above premise, the transfer addresses for realizing this rotation method are (1-1) to (1-9) and (1-1).
~ (can be generated sequentially according to the rule 2-91. The symbols are explained in Figure 4. In the figure, (g) is the original image, (
h) is the rotated image, m is the horizontal length of the original image, t is the vertical length of the original image, and p is the horizontal length of the area to which the original image belongs. At this time, the transfer source address is (1-1) with the first M value of the address as
Set to the memory address corresponding to the upper left black pixel of the original image.

(1-2) Output the address 1/ and increment it by 1.

(1-3) (1-21 as A=cQSθ/(1-ω
Repeat Sθ) times.

(1-4) Skip 7 dresses k, C2i.

(1-5) (1-2>-(1-4), m (1-
Repeat (JJSθ) times.

(1-61-f dress gold, p-Inm skip.

(17) (1-2) to (1-6), 13d 1/l
Repeat anθ times.

(1-8) Skip the address by -1.

(1-9) (1-2) to (1-8), t ta
Repeat nθ times.

The transfer destination address is as follows: (2-1) Set the initial value of the address to the memory address corresponding to the upper left point pixel of the rotated image.

<2-2) Output address money and increment it by 1.

(2-3) (2-2), B = l / ta
Repeat nθ times.

(2-4) Skip the address by -p.

(2-5) (2-2) ~ (2-4) Gold, m ta
Repeat nθ times.

(2-6) Address, I) (m tanθ+1
)-m skip.

(2-7) (2-2) to (2-6), 1=cO
Repeat 3θ/(1-cosθ) times.

(2-8) Give the address p.

(z-q) (2-2) ~ (2-8j, t<1-
ωSθ)/(Repeat 030 times.

can occur sequentially according to

However, rules (1-1) to (1-9) and (2-
1) The repetition numbers and skip lengths appearing in (2-9) that are not integers are approximated by the nearest integer.

FIG. 5 shows an example of an apparatus for implementing the rotation method of the present invention. In the figure, the part surrounded by a dotted line is the memory control device 503.
It is. This is located between a central processing unit (CPU) 501 and a memory 502, and the central processing unit 501 is
Address bus 504, data bus 505, control bus 506,! : Connected by. The memory control device 503 includes an address switch 507, an address control section 508, a control section 509, a read/write buffer 510, and a read/write switch 511.

The address switch 507 is configured so that the mode signal 512 sent from the control unit 509 is mode 1 (a mode in which the memory 502 is used as the main storage device of the central processing unit 501).
When , data sent from Atto1/Snox 504 is sent to memory 502 as address data. When the mode signal 512 indicates mode 2 (a mode in which the memory 502 is used for cutting out and combining partial figures), the data 517 sent from the address control unit 508 is used as address data. , memory 502
Send to.

The read/write buffer 510 is a buffer that stores data read from the memory 502 and data to be written. This completes one operation in two steps. That is, in the first step, data is imported into the read/write node (sofa 510), and this data is sent out in the next second step.The read source determines the source from which the data is taken in, and the destination to which it is sent. - This is the read/write Y strobe signal 513 sent from the write switch 511.When the mode signal 512 indicates mode 1, when the processing Yasugi of the central processing unit 3 is in the read mode, the read/write strobe signal 513 is in the read mode. When the instruction is a write, it becomes a write instruction. At this time, the read operation takes data from the memory 502 to the read/write buffer 510 in the first step, and in the second step, the data is transferred to the central processing unit 501. The write operation is the opposite.

On the other hand, when the mode signal 512 indicates mode 2, the read/write strobe signal 513 alternately repeats read instructions and write instructions. That is, in the first step, data is fetched from the memory 502 into the read/write buffer 510, and in the second step, the data is not sent to the central processing unit 501, but is loaded into the memory 502 again.
Send to. This allows data transfer within memory 502 without going through buses 504-506.

The read/write switch 511 is a part that generates a read/write strobe signal 513.

As mentioned above, in mode 1■, the central processing unit 501 issues a read request, β or write request (), respectively, and accordingly issues a read instruction or a write instruction.In mode 2, a read instruction and a write instruction are issued. is issued repeatedly and alternately.

In mode 2, the address control unit 508 controls the transfer source, address, and destination address. Its detailed configuration is shown in FIG. The figure shows only the part that calculates the transfer source address. The part that calculates the forwarding address has the same constituent sounds as the part that calculates the forwarding address, so
Omit the inducement. In the figure, 601 to 608 are parameters that appear in the address generation rule (1() to (1-9) ((2-1) to (2-9) in the case of the part that calculates the transfer destination address). 609 is a selector for selecting the address update amount, 610 is a counter 611-
614 output lunch, 611 to 614 are counters that detect address switch timing, 615 is an adder that updates the address, 6]-6 is a selector for loading the initial address value, and 617 holds the address. 618 is a register, 618 is a buffer for address output, 619 is a timing controller that controls address update and output timing, 620 is a data, address and control bus, and 646 is an address bus.

FIG. 7 shows a flowchart of a program executed by the CPU 501 when the present rotary force type is realized using the above-described apparatus. In the figure, 701 is a rule (1-
1) A step of calculating the parameters appearing in (1-9) and (2-1) to (2-9), 702 is a step of storing the parameters calculated in step 701 in the registers 601 to 608iC4 of the memory control device, 703 704 is a step of starting up the memory control device, and 704 is a step of monitoring termination of the memory control device. Step 702
The parameters given in are (3-11 to (3-8) and (4-1) to (4-8). The parameters given to the transfer source address control section are (3-1) 14o = 1 ( 3-2) Hl = Ho + C = 1 + 1 = 2 (33
) H2=Ht+([)-m)”p m+2(3
-4) Hl = H2+(1)”I) m+1
(3-5) W, = A = CO3θ/ (1-, -c
osθ) (3-6) W+ =m (1-cos
θ ) (37) W2 = B = 1 /lanθ
(3-8) W3 "The parameter given to the ttanθ transfer destination address control section is (-4-1) Ho'
=1 (42) H1'=Ho' + (p)=l-p(
43) H2'=i(f+(p(mtanθ+1)−
m)=ml)tanθ-m(4-4), H3'=H
2'+ p-=mptaoθ ten p-m (4-5) W
o-B = 1/tanθ(4-6) W1'=
mtanθ (4-7) W2'=A=CO3θ/ (1-cos
θ) (4-8) W3'= 1 (1-+; O3θ)
/CoSθ.

However, parameters (3-1) to (3-8) and (
4-1) to (4-8) that are not integers are approximated by the nearest integer.

Next, the present operation for explaining the operation of the transfer source address control section is performed between step 703 and step 704.

In mode 2, the address control unit 508 mutually generates transfer source and transfer destination addresses to perform data transfer. The operation of the transfer destination address control section is similar to the operation of the transfer source address control section, so a description thereof will be omitted. First, the value of address initial value - 1 is sent to the parameters (3-1) to (3-8 registers 601 to 608 via the bus 620 and to the register 617 via the bus 648 and the selector 616. The input 643 of the selector 616 and 648 are selected by the signal 641.Next, when the memory controller activation is applied to the control section 509 through the control bus 506, the timing controller 61
It takes 9 to start. The timing controller 619 is
Signals 636-640 are generated sequentially. Counter 611~
614 is cleared in the initial state, but the signal 636
As a result, the counter 611 counts up by one. As a result, the content of the counter 611 becomes 1. register 60
5, the signal 632 is not generated.

Therefore, the values of signals 632-634 are 0 at this point. Signal 637 causes signals 632 to 634 to latch 61
They are latched to 0 and output as signals 629 to 631, respectively. Selector 609 selects m of the values of signals 629-631.
(0,0,0), (1,0,0), (1,1°0), (
1, 1, 1), respectively V distalo 01 to 60
4 through buses 621 to 624. Currently, the signals 632 to 634 are all 0, that is, the 1st numbers 629 to 631 are all 0, so the signal 638 changes the content 1 of the register 601 to the selector 6.
09 is sent to bus 642. Adder 6
15 is the contents of the register 617, the value of the initial address value - 1, and the data of the bus 642, 1? Add and send the result to bus 643. Signal 641 causes selector 616
The input is switched to bus 643 and the result is sent to bus 644. In response to a signal 639, the data on the bus 644 is taken into the register 617, and the data is output on the bus 645.

Signal 640 causes data on bus 645 to be transferred to buffer 61.
8 and sends it to the address bus 646. below,
Similarly, the counter 611 has the contents of the register 605.
The address data is counted up until it becomes equal to the content A, and the address data output to the address bus 646 becomes a value incremented by one. When the contents of the counter 611 become equal to the contents A of the register 605, a signal 632 is generated, clearing the contents of the counter 611, and increasing the counter 612 by one. As a result, the selector 609 selects the content 2 of the register 602, and the data output to the address bus 646 becomes a value incremented by two. The operation continues in the same manner until the contents of the counter 614 become equal to the contents L[anθ of the register 608. When the contents of the counter 614 become equal to the contents of the register 608, the timing controller 619 stops and outputs the end signal 516 after transmitting the last address data. The signal 516 is input manually to the control unit 509 and is used in step 704 to determine the end.

According to this embodiment, at most parameters (3-1) to (3-8
), and (4-1) to (4-8), it is possible to obtain a rotated image that is congruent with the original image. The processing speed is comparable to that of normal DMA (Direct
MThmorYAccess) transfer.

〔Effect of the invention〕

According to the present invention, a rotated image can be obtained at high speed and with high image quality. In other words, the processing speed is the same as that of normal DMA.
(Direct Memory A, access) This is equivalent to transfer, and the rotated image is congruent with the original image.

[Brief explanation of the drawing]

Figure 1 is a definition diagram of the coordinate axes and rotation angle directions, and Figure 2 is:
A diagram of the principle of the rotation method of the present invention, FIG. 3 is a diagram showing an example of correspondence between images and memory, FIG. 4 is a definition diagram of symbols used for parameters, FIG. 5 is an overall configuration diagram of the device, and FIG. 6 7 is a block diagram of the address control section, and FIG. 7 is a processing flow diagram of the present invention. (a), (c), (g>--original image,' (
b), (d), (b)-・Rotated image, (e)・
...Image, (f)...Memo IJ, 501...Central processing unit (CP[J), 502...Memory, 503...
-Memory control device, 504...address bus, 505
...Data bus, 506...Control bus, 5
07...Address switch, 508...Address control L 509...Control unit, 510...Read/write buffer, 511...Read/write switch, 601-608...Register, 609...・
Selector, 610...Latch, 611-614...
Counter, 615...Adder, 616...Selector, 617...Register, 618...Buffer, 61
9...Timing controller, 62G...Address/data/control bus, 646...Atto piece
1 Figure y 3 Figure (e) η 4- Figure C3) (h) Circulation 5; Figure 398- 7th Ward Ka

Claims (1)

[Claims] In a method for obtaining a rotated image rotated by an arbitrary angle from an original image stored in a memory, a first means for reading image information and sound from the memory and storing this information in the memory again, and the read address and the storage address are provided. and a third means for calculating the number of repeats and the address skip length from the rotation angle. Image rotation method.