JPS596649A - Repeating device of data - Google Patents

Repeating device of data

Info

Publication number
JPS596649A
JPS596649A JP57115410A JP11541082A JPS596649A JP S596649 A JPS596649 A JP S596649A JP 57115410 A JP57115410 A JP 57115410A JP 11541082 A JP11541082 A JP 11541082A JP S596649 A JPS596649 A JP S596649A
Authority
JP
Japan
Prior art keywords
synchronization
data
terminal device
bit
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57115410A
Other languages
Japanese (ja)
Inventor
Osamu Sasaki
治 佐々木
Shigeo Kobayashi
小林 成夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57115410A priority Critical patent/JPS596649A/en
Publication of JPS596649A publication Critical patent/JPS596649A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/05Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To reduce the delay of data repeating and to reduce the cost of a cable and a data transmitting/receiving circuit, by accumulating data and adding a synchronization maintaining sequence in accordance with the phase difference between a synchronizing signal in receiving data and that in an MODEM. CONSTITUTION:The phase difference between a synchronizing signal extracted 44 from data received from a terminal device 3 and the synchronizing signal of the MODEM2 is detected, and when the number of synchronizing signals extracted from the data received from the terminal device 3 is larger than that of MODEM synchronizing signals, the data which can not be transmitted to the MODEM2 is stored in a bit buffer 48 of a repeating device 4 until the terminal device 3 sends an end character for a transmission massage. If the number of synchronizing signals of the MODEM2 is larger than the number of synchronizing signals extracted from the data received from the terminal device 3, the terminal device 3 sends a synchronization maintaining sequence, then the repeating device 4 adds a synchronization maintaining sequence moreover.

Description

【発明の詳細な説明】 発明の対象 本発明はSYN同期通信手順によるビット同期信号を中
継する場合の中継装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a relay device for relaying bit synchronization signals using a SYN synchronization communication procedure.

従来技術 複数の端末装置を通信回線で経由し端末制御装置に接続
する場合、第1図に示すように端末制御装置1にモデム
2、通信回線5を経由して端末装置3をマルチブランチ
接続することが行なわれている。この場合、 (a)各端末装置i3をモデム2に接続しなげればなら
ないため端末装置の接続台数が増加するとモデム台数も
増加する。
Prior Art When connecting multiple terminal devices to a terminal control device via a communication line, a modem 2 and a terminal device 3 are connected to the terminal control device 1 via a modem 2 and a communication line 5 in a multi-branch manner, as shown in FIG. things are being done. In this case: (a) Since each terminal device i3 must be connected to the modem 2, as the number of connected terminal devices increases, the number of modems also increases.

(b)マルチブランチ接続のため、各端末装置が交゛互
にモデムのキャリア出力制御を行うため、伝送上のオー
バヘッドが太きい。等の問題がある。
(b) Due to the multi-branch connection, each terminal device alternately controls the carrier output of the modem, resulting in a large transmission overhead. There are other problems.

そこで従来は以上の問題を解決するため、第2図に示す
ようにデータ中継装置4を介して端末制御装置1、モデ
ム2、通信回線5および端末袋ff3を接続することが
行なわれている。この場合、端末装置13から受信した
データのビット速度とモデムの同期信号のピッチ速度の
位相差によるデータ課すな対策するためデータ中継(1
)端末装置3に、モデムの同期信号を供給し、端末装置
3からのデータ送信をモデム2からの同期信号に同期さ
せる方式がある。この場合。
Conventionally, in order to solve the above problem, a terminal control device 1, a modem 2, a communication line 5, and a terminal bag ff3 are connected via a data relay device 4 as shown in FIG. In this case, data relay (1
) There is a method in which a modem synchronization signal is supplied to the terminal device 3 and data transmission from the terminal device 3 is synchronized with the synchronization signal from the modem 2. in this case.

データ中継装置4と各端末袋f3との信号ケーブルはデ
ータ伝送のためのケーブルと同期信号を伝送するケーブ
ルが必要となり、ケーブルコストおよびデータ送受信回
路部コストが端末接続台数に比例して増加する欠点があ
る。また、0)データ中継装置4に直並列変換部、記憶
装置および10セツサを備え直並列変換部により、端末
装置3から受信したシリアルデータなパラレルテークに
変換し、一旦記憶装置へ貯えた後端末制御装置1ヘモデ
ム2の同期信号に同期してデータを伝送する方式では信
号の直並列変換を行うためデータ中継による遅延が大き
くなると共にデータ中継装置コストが増大する欠点があ
る。
The signal cable between the data relay device 4 and each terminal bag f3 requires a cable for data transmission and a cable for transmitting synchronization signals, and the disadvantage is that the cost of the cable and the cost of the data transmission/reception circuit increase in proportion to the number of terminals connected. There is. 0) The data relay device 4 is equipped with a serial/parallel converter, a storage device, and a 10 setter, and the serial/parallel converter converts the serial data received from the terminal device 3 into a parallel take, and once stores it in the storage device, the terminal The method of transmitting data to the control device 1 in synchronization with the synchronization signal of the modem 2 has the drawback that the delay due to data relay increases and the cost of the data relay device increases because the signal is converted from serial to parallel.

発明の目的 本発明の目的は、従来技術の問題点を解決することにあ
る。
OBJECT OF THE INVENTION The object of the invention is to solve the problems of the prior art.

発明の総括的説す1 本発明は端末装置より受信するデータから抽出した同期
信号と、モデムとの同期信号の位相差を検出しくa)端
末装置からの受信データより抽出した同期信号の数がモ
デム同期信号の数より大きい場合には、端末装置が、伝
文の終了キャラクタな送出するまでモデム−\送出しき
れなかったテークをビットバッファに貯える。
General description of the invention 1 The present invention detects the phase difference between a synchronization signal extracted from data received from a terminal device and a synchronization signal with a modem.a) The number of synchronization signals extracted from data received from the terminal device is If the number is greater than the number of modem synchronization signals, the terminal stores the takes that could not be sent out to the modem in the bit buffer until it sends the end character of the message.

また(2)モデムの同ルリ信号の数が端末装置の受信゛
データから抽出した同期信号の数より大きくなったとぎ
に、端末装置iが同期維持シーケンスを送出した後、さ
らに中継装置が同期維持シーケンスを付加するものであ
る。
(2) When the number of synchronization signals from the modem becomes larger than the number of synchronization signals extracted from the data received by the terminal device, after the terminal device i sends the synchronization maintenance sequence, the relay device further maintains synchronization. It adds a sequence.

実施例 以下、本発明の一実施例を第3図および第4図により説
明する。
EXAMPLE Hereinafter, an example of the present invention will be explained with reference to FIGS. 3 and 4.

第6図の4が本発明によるデータ中継装置であり、端末
装置6から受信したデータを受信回路40、OR回路4
1を経て受信信号401として取り出す。なお、本デー
タ中継装f4では、同時に2台以上の端末装置3からの
データ送信がないものとする。受信信号401はSYN
検出部42゜終了キャラクタ検出部46、同期信号抽出
部44およびビットバッファ部48に供給される。SY
N検出部42では同期維持シーケンス(0011001
0)2の監視を行い、終了キャラクタ検出部46では伝
文の終了の監視を行ない結果を制御部46に報告する。
Reference numeral 4 in FIG. 6 is a data relay device according to the present invention, in which data received from the terminal device 6 is transferred to a receiving circuit 40 and an OR circuit 4.
1 and is extracted as a received signal 401. Note that in this data relay device f4, it is assumed that data is not transmitted from two or more terminal devices 3 at the same time. The received signal 401 is SYN
The detection unit 42 is supplied to an end character detection unit 46, a synchronization signal extraction unit 44, and a bit buffer unit 48. S.Y.
The N detection unit 42 uses a synchronization maintenance sequence (0011001
0)2, and the end character detection section 46 monitors the end of the message and reports the result to the control section 46.

同期信号抽出部44は受信信号401のデータ変化点を
検出することにより、受信信号40101ビット間隔を
抽出し受信データ同期信号402を出力する。さらに受
信信号401は受信データ同期信号402に同期して1
ビツト受信される毎にピットバッファ部48に貯えられ
る。ピントバッファ部48は、入力データをあらかじめ
初期設定されたビット数だけ貯えた後、モデム同期信号
403とモデム同期信号4030位相が常に位相比較部
45により比較されており位相比較部45が(a)モデ
ム同期信号403を1ビツト検出する間に受信テーク同
期信号402を1ビット以上検出した場合、ピットバッ
ファ部48−\の入力は受信データ同期信号402に同
期して行なわれるため、ピットバッファ48には入力と
出力のビット数の差だけ余分にデータが貯えられる。こ
のとき、終了キャラクタ検出部43による伝文終了を検
出すると、制御部46はピットバッファ部48へのデー
タ入力をピットバッファ部48で貯えられているデータ
のビット数が初期設定値に達するまで禁止する。以上の
場合の受信信号401と送信信号404との関係を第4
図(a)K示す。(b)受信データ同期信号402を1
ビツト検出する間にモデム同期信号405を1ビット以
上検出した場合、ピットバッファ部48からの出力は、
モデム同期信号405に同期して行なわれるため、ピッ
トバッファ部4Bで貯えられるデータのビット数は減少
する。このとき、SYN検出部42で同期維持シルケン
スを検出するとS′YN挿入部47を動作させ、ピット
バッファ部48へ強制的に同期維持シーケンスを挿入す
ることにより貯えるデータのビット数を増加させる。以
上の場合の受信信号401と送信信号404との関係を
第4図←)に示す。なお、本方式では第4図の)に示す
ように同期維持シーケンスの後にさらに同期維持シーケ
ンスが付加されるがSYN同期通信手順では、同期維持
シーケンスを複数個連続させても同期維持シーケンス間
にiまさまれだフレーム部の伝送には影響を与えない。
The synchronization signal extraction unit 44 extracts the bit interval of the received signal 40101 by detecting the data change point of the received signal 401, and outputs the received data synchronization signal 402. Furthermore, the received signal 401 is 1 in synchronization with the received data synchronization signal 402.
Every time a bit is received, it is stored in the pit buffer unit 48. After the focus buffer section 48 stores the input data by a preset number of bits, the phases of the modem synchronization signal 403 and the modem synchronization signal 4030 are constantly compared by the phase comparison section 45. If one bit or more of the receive take synchronization signal 402 is detected while one bit of the modem synchronization signal 403 is detected, input to the pit buffer section 48-\ is performed in synchronization with the receive data synchronization signal 402, The extra data is stored by the difference between the number of input and output bits. At this time, when the end character detection section 43 detects the end of the message, the control section 46 prohibits data input to the pit buffer section 48 until the number of bits of data stored in the pit buffer section 48 reaches the initial setting value. do. The relationship between the received signal 401 and the transmitted signal 404 in the above case is explained in the fourth example.
Figure (a) shows K. (b) Receive data synchronization signal 402 to 1
If one bit or more of the modem synchronization signal 405 is detected during bit detection, the output from the pit buffer section 48 is
Since this is performed in synchronization with the modem synchronization signal 405, the number of bits of data stored in the pit buffer section 4B is reduced. At this time, when the SYN detecting section 42 detects a synchronization maintenance sequence, the S'YN insertion section 47 is operated to forcibly insert the synchronization maintenance sequence into the pit buffer section 48, thereby increasing the number of bits of stored data. The relationship between the received signal 401 and the transmitted signal 404 in the above case is shown in FIG. Note that in this method, a synchronization maintenance sequence is added after the synchronization maintenance sequence as shown in ) in Figure 4, but in the SYN synchronization communication procedure, even if multiple synchronization maintenance sequences are consecutive, there is no i time between the synchronization maintenance sequences. It does not affect the transmission of the frame part.

以上、本発明の一実施例について説明したが上記実施例
は更に変形して実施され得る。
Although one embodiment of the present invention has been described above, the above embodiment can be implemented with further modifications.

例えば、上記実施例において、クロック偏差がない場合
、例えば受信データが所定の速度で到来する場合には、
SYN検出部42、及び8YN挿入部47は必ずしも必
要とされない。
For example, in the above embodiment, if there is no clock deviation, for example, if the received data arrives at a predetermined speed,
The SYN detection section 42 and the 8YN insertion section 47 are not necessarily required.

他の変形例として、終了キャラクタ検出部43は必ずし
もなくてもよい。
As another modification, the end character detection section 43 may not necessarily be provided.

発明の効果 本発明によれば、次の効果を得ることができる。Effect of the invention According to the present invention, the following effects can be obtained.

(a)端末装置にモデム同期信号を供給することが不要
となるためケーブルコストおよびデータ送受信回路コス
トを低減できる。
(a) Since it is not necessary to supply a modem synchronization signal to the terminal device, cable costs and data transmission/reception circuit costs can be reduced.

(b) 本方式はシリアルデータの直並列変換を行なわ
ないためデータ中継のための遅延が少ない。
(b) Since this method does not perform serial-to-parallel conversion of serial data, there is little delay for data relay.

(C)直並列変換部やプロセッサが不要なため、廉価な
中継装置が実現できる。
(C) Since no serial/parallel converter or processor is required, an inexpensive relay device can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は従来技術を説明するためのシステム構
成図、第3図は本発明の一実施例を説明するためのデー
タ中継装置ブロック図、第4図はそのタイムチャートで
ある。 1・・・端末制御装置  2・・・モデム6・・・端末
装置    4・・・データ中継装置5・・・通信回線 4D・・・受信回路    41・・・OR回路42・
・・S”YN検出部 43・・・終了キャラクタ検出部 44・・・同期信号抽出部 45・・・位相比較部   46・・・制御部47・・
・めA挿入部 48・・・ピント4727部 49・・・送信回路 401・・・受信信号 402・・・受信データ同期信号 405・・・モデム同期イぎ号 404・・・送信信号 オ 1 層 ′? 2 叱
1 and 2 are system configuration diagrams for explaining the prior art, FIG. 3 is a block diagram of a data relay device for explaining an embodiment of the present invention, and FIG. 4 is a time chart thereof. 1... Terminal control device 2... Modem 6... Terminal device 4... Data relay device 5... Communication line 4D... Receiving circuit 41... OR circuit 42.
...S"YN detection section 43...End character detection section 44...Synchronization signal extraction section 45...Phase comparison section 46...Control section 47...
- Me A insertion section 48... Focus 4727 section 49... Transmission circuit 401... Reception signal 402... Reception data synchronization signal 405... Modem synchronization key code 404... Transmission signal O 1 layer ′? 2 scolding

Claims (1)

【特許請求の範囲】[Claims] 端末装置とは、近距離用インタフェースにより、端末制
御装置とは、モデムを介した遠距離用インタフェースに
より接続され、端末装置と端末制御装置との間のSYN
同期通信手順によるビット同期信号を中継する装置にお
いて、端末装置からの受信データにより、同期維持シー
ケンス(aallaolo )、を検出するSYN検出
部、伝文の終了キャラクタを検出する終了キャラクタ検
出部端末装置からの受信データ1ビツト間隔を抽出する
同期抽出部、当該同期抽出部より抽出した同期信号とモ
デムの同期信号との位相とを比較する位相比較部、端末
装置から受信したデータをあらかじめ初期設定された数
だけ貯えかつデータ入力は同期抽出部から出力される同
期信号に同期して行い、またデータ出力部はモデムの同
期信号に同期して行うピットバッファ部、同期維持シー
ケンスをビットバッファ部に挿入するSYN挿入部およ
び(1)モデムの同期信号1ビツトを検出する間に端末
装置から1ビット以上のデータを検出した場合、その差
のビット数だけピットバッファ部での遅延ビット数を増
加させ、終了キャラクタ検出部で伝文の終了キャラクタ
を検出することによりピットバッファ部の遅延ビット数
を初期復旧させ、また(2)端末装置から受信データを
1ビツト受信する間にモデムの同期信号を1ビツト以上
受信した場合、その差のビット数だけビットバッファで
の遅延ビット数を減少させ、SYN検出部で同期維持シ
ーケンスを検出したときに、SYN挿入部によりビット
バッファに同期維持シーケンスを挿入し挿入したビット
数だけビットバッファでの遅延ビット数を増加させる制
御部を備えたことを特徴とするデータ中継装置。
The terminal device is connected by a short-distance interface, and the terminal control device is connected by a long-distance interface via a modem, and the SYN between the terminal device and the terminal control device is
In a device that relays a bit synchronization signal based on a synchronous communication procedure, a SYN detection section detects a synchronization maintenance sequence (aallaolo) based on data received from a terminal device, and an end character detection section detects an end character of a message from the terminal device. a synchronization extractor that extracts the 1-bit interval of the received data; a phase comparator that compares the phase of the synchronization signal extracted from the synchronization extractor with the synchronization signal of the modem; The data input is performed in synchronization with the synchronization signal output from the synchronization extraction section, and the data output section is performed in synchronization with the modem synchronization signal in the pit buffer section and the synchronization maintenance sequence is inserted into the bit buffer section. SYN insertion section and (1) If 1 bit or more of data is detected from the terminal device while detecting 1 bit of modem synchronization signal, the number of delay bits in the pit buffer section is increased by the number of bits of the difference, and the process ends. By detecting the end character of the message in the character detection section, the number of delay bits in the pit buffer section is restored to its initial state; If received, the number of delay bits in the bit buffer is reduced by the number of bits of the difference, and when the SYN detection section detects a synchronization maintenance sequence, the SYN insertion section inserts the synchronization maintenance sequence into the bit buffer, and the inserted bit is 1. A data relay device, comprising: a control unit that increases the number of delay bits in a bit buffer by the number of bits.
JP57115410A 1982-07-05 1982-07-05 Repeating device of data Pending JPS596649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57115410A JPS596649A (en) 1982-07-05 1982-07-05 Repeating device of data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57115410A JPS596649A (en) 1982-07-05 1982-07-05 Repeating device of data

Publications (1)

Publication Number Publication Date
JPS596649A true JPS596649A (en) 1984-01-13

Family

ID=14661872

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57115410A Pending JPS596649A (en) 1982-07-05 1982-07-05 Repeating device of data

Country Status (1)

Country Link
JP (1) JPS596649A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6268346A (en) * 1985-09-20 1987-03-28 Fujitsu Ltd Line connection system for data transmission system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6268346A (en) * 1985-09-20 1987-03-28 Fujitsu Ltd Line connection system for data transmission system

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