JPS596587A - Semiconductor laser device - Google Patents

Semiconductor laser device

Info

Publication number
JPS596587A
JPS596587A JP57115341A JP11534182A JPS596587A JP S596587 A JPS596587 A JP S596587A JP 57115341 A JP57115341 A JP 57115341A JP 11534182 A JP11534182 A JP 11534182A JP S596587 A JPS596587 A JP S596587A
Authority
JP
Japan
Prior art keywords
laser
gaas
layer
semi
electric circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57115341A
Other languages
Japanese (ja)
Inventor
Hideaki Matsueda
秀明 松枝
Michiharu Nakamura
中村 道治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP57115341A priority Critical patent/JPS596587A/en
Publication of JPS596587A publication Critical patent/JPS596587A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40Materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of group III and group V of the periodic system

Abstract

PURPOSE:To make electrical connection between both sufficient in case of integration of a laser diode with an electrical circuit in a lateral direction, and reduce the floating capacity, further offer an integration structure whereby the pattern formation of a complicated and precise electrical circuit can be attained. CONSTITUTION:The titled device is an example applied for an integrated circuit wherein GaAs/GaAlAs is used, and composed of a semi-insulating GaAs substrate 1, an N-GaAs conductive layer 2, an N-GaAlAs clad layer 3, a P-GaAs cap layer 6, bonding pads (Cr/Au) 8, 13, 14, a laser stripe electrode (Cr/Au)G, ohmic electrodes (AuGe/Ni/Au) 10, 12, a Schottky electrode (Ti/Tt/Au) 11 and an SiO2 film 15. A thickened active layer oscillates laser at the active region of a TS laser.

Description

【発明の詳細な説明】 本発明は半導体レーザと電気回路部の集積化に関する。[Detailed description of the invention] The present invention relates to the integration of a semiconductor laser and an electric circuit section.

半絶縁性基板の上に、 T S (TerrasedS
ubstrate )型のレーザダイオードと電気回路
とを、平面的に並べて作り付ける構造を提供する。
On top of the semi-insulating substrate, T S (Terrased S
To provide a structure in which a (ubstrate) type laser diode and an electric circuit are arranged side by side in a plane.

レーザダイオードと電気回路との集積化の例としては、
レーザダイオードとF E T (FieldEffe
ct  Transistor、電界効果形トランジス
タ)・とを縦に、2階建状に組み合わせた例(H6Ma
tsueda、 To Fukzawy、 T、’1(
uroda。
An example of integrating a laser diode with an electric circuit is
Laser diode and FET (FieldEffe
ct Transistor, field effect transistor) and are vertically combined in a two-story shape (H6Ma
Tsueda, To Fukzawy, T, '1 (
uroda.

M、Nakamura ; Japan J、 App
l、 Phys、 ’yo1゜20 (1981) 8
upp1.20−1 1)p、 193−197ンおよ
び、横に平面的に組み合わせた例(S、 Margal
it、 N、 Bar−Chaim、  J。
M, Nakamura; Japan J, App
l, Phys, 'yo1゜20 (1981) 8
upp1.20-1 1) p, 193-197 and an example of horizontal combination (S, Margal
It, N., Bar-Chaim, J.

KatZ 、 1. Ury、 D、 P、 Wilt
、 M、Yustand A、 Yariv HI、a
ser pocus 、 3ept。
KatZ, 1. Ury, D., P., Wilt.
, M., Yustand A., Yariv H.I., a.
ser pocus, 3ept.

(1980)I)p、76−80)などがある。縦に組
み合わせる方法には高速応答性、コンパクトさなどの特
長があるが、電気回路の種類によっては、横に平面的に
組み合わすことが必要になる。ところが従来報告されて
いる横方向の平面的な組み合わせにおいては、電気回路
とレーザダイオードとの間の電気的な接続が十分実用に
耐えるものでなく高速応答性、低電力駆動などが全く望
めない。
(1980) I) p, 76-80). The method of vertically combining devices has advantages such as high-speed response and compactness, but depending on the type of electrical circuit, it may be necessary to combine devices horizontally. However, in the horizontal planar combinations that have been reported so far, the electrical connection between the electric circuit and the laser diode is not sufficiently practical, and high-speed response and low-power driving cannot be expected at all.

しかもレーザダイオード部と、電気回路部との間の段差
が大きく、写真蝕刻法によって精度の良い電気回路パタ
ーンを作ることができなかった。
Moreover, the difference in level between the laser diode section and the electric circuit section was large, making it impossible to create a highly accurate electric circuit pattern by photolithography.

本発明は横向きにレーザダイオードと電気回路とを集積
化する場合、両者の間の電気的接続を十分なものとし、
がつ浮遊容量を少くし、しめ1も複雑精密な電気回路の
パターン形成が達成できる集積構造を提供する。
When a laser diode and an electric circuit are integrated horizontally, the present invention provides a sufficient electrical connection between the two,
To provide an integrated structure which can reduce stray capacitance and achieve complex and precise pattern formation of electric circuits.

レーザダイオードと電気回路を集積化するに当り、特に
イオン打込み技術等による複雑な回路の精密なパターン
形成を可能にするために、半絶縁性基板の上に両者を横
に並列して作り付ける。かつレーザダイオードのn側電
極は、半絶縁性基板の上に高キャリア濃度のn型の半導
体層をつけることによって形成した。全体の構造は第1
図に示す通りである。レーザ部の構造は図に示すように
、T8構造であるために、電気回路部分との間に大きな
段差がなく、写真蝕刻法によるノくター/形成が容易で
ある。
When integrating a laser diode and an electric circuit, they are fabricated horizontally in parallel on a semi-insulating substrate, especially in order to enable precise patterning of complex circuits using ion implantation technology or the like. The n-side electrode of the laser diode was formed by forming an n-type semiconductor layer with a high carrier concentration on a semi-insulating substrate. The overall structure is the first
As shown in the figure. As shown in the figure, the structure of the laser section is a T8 structure, so there is no large step between it and the electric circuit section, and it is easy to form a notch by photolithography.

さらにまたLDの上に、例えば液相エピタキシャル結晶
成長(LPE)法によって高比抵抗層を成長させるなら
ば、LDの上側すなわちp側にも電気回路tイオンイン
プラなどの技術を用いて作り付ける事ができる。
Furthermore, if a high resistivity layer is grown on the LD using, for example, the liquid phase epitaxial crystal growth (LPE) method, an electric circuit can be created on the upper side of the LD, that is, on the p side, using technology such as ion implantation. I can do it.

本発明t” G a A S / G a A I A
 sを用いた集積回路に適用した例を示す。全体の構造
は第1図の通りである。すなわち、1:半絶縁性Q a
 A s基板< (100)面)、2 : n−GaA
s導電層(0,5pm厚)# 3: ”  GaAlA
sクラッド層(0,5μm厚)* 4 :GaAs活性
層(0,1μm厚)。
The present invention
An example of application to an integrated circuit using s is shown below. The overall structure is shown in FIG. That is, 1: semi-insulating Q a
As substrate < (100) plane), 2: n-GaA
s conductive layer (0.5 pm thickness) #3: ” GaAlA
s cladding layer (0.5 μm thick) * 4: GaAs active layer (0.1 μm thick).

5 : p−GaAlAs クラッド層(1μm厚)。5: p-GaAlAs cladding layer (1 μm thick).

6 :p−GaAsキャップ層(0,5p m厚)、8
゜13.14:ボンディングバッド(Cr/Au)s9
:レーザストライプ電極(Cr/Au)((011>方
向)t  io、12ニオ−ミック電−fFM (Au
Ge/N i/Au )、11 : シ=iットキイ電
極(T i/P t/AU ) 、 7.15 : S
in、絶縁膜である。16;部がTSレーザの活性領域
で、太くなった活性層がレーザ発振する。第2図がこの
活性領域の拡大図である。太くなった部分が発光する領
域である。本実施例においては、レーザ部と電気回路部
の間の段差はわずか3μmであり。
6: p-GaAs cap layer (0.5 pm thickness), 8
゜13.14: Bonding pad (Cr/Au) s9
: Laser stripe electrode (Cr/Au) ((011> direction) tio, 12 niomic electron-fFM (Au
Ge/N i/Au ), 11: Shit key electrode (T i/P t/AU ), 7.15: S
in, an insulating film. The part 16 is the active region of the TS laser, and the thick active layer oscillates the laser. FIG. 2 is an enlarged view of this active region. The thicker part is the area that emits light. In this embodiment, the level difference between the laser section and the electric circuit section is only 3 μm.

縮小投影露光法によって、電気回路部において、最小寸
法1μmの微細パターンを形成する事ができた。第1図
の電気回路は1個のFETの例を示したが、実際は数個
のF’ETからなるレーザの変調−駆動回路を集積化す
ることができた。レーザ部と電気回路部との接続は、第
1図中に2.で示す高キャリア濃度n−QaAS層によ
るが、この距離を、TSレーザの段差部〃為ら、電気回
路内の最もレーザに近い金属電極の端までの長さ第1図
dで、15μm以下にすると特に高周波特性、低電力動
作が実現した。
By using the reduction projection exposure method, it was possible to form a fine pattern with a minimum dimension of 1 μm in the electric circuit section. Although the electrical circuit of FIG. 1 shows an example of one FET, in reality, a laser modulation/drive circuit consisting of several F'ETs could be integrated. The connection between the laser section and the electric circuit section is shown in 2. in FIG. The distance from the stepped part of the TS laser to the end of the metal electrode closest to the laser in the electric circuit (d in Figure 1) is 15 μm or less. This resulted in particularly high-frequency characteristics and low-power operation.

以下に製造方法の概略金示す。半導体レーザ部および電
気回路部の各々自体は従来の製造方法そのままを適用し
得るので簡潔な記述にとどめる。
The manufacturing method is outlined below. Since conventional manufacturing methods can be applied to each of the semiconductor laser section and the electric circuit section, their descriptions will be kept brief.

半導体性のQ a 、A s基板1の(100)面の所
定部分に約2μmの凹部を形成する。その傾斜は70″
〜45°の程度である。この凹部を含んで、前述の凹部
は通常1.0〜3.0μm程度となしている。厚さ0.
5μmのn型Q a A s導電層2.厚さ0.5μm
のn Ml! G a、7A t、、、 A s層3.
厚さ0.1prnのQ a A !i活性層4.厚さi
μmop型Ga、。
A recess of approximately 2 μm is formed in a predetermined portion of the (100) plane of the semiconductor Q a , A s substrate 1 . Its slope is 70″
~45°. Including this recess, the above-mentioned recess is usually about 1.0 to 3.0 μm. Thickness 0.
5 μm n-type Q a As conductive layer 2. Thickness 0.5μm
n Ml! Ga, 7A t,,, A s layer 3.
Q a A with a thickness of 0.1 prn! i active layer 4. thickness i
μmop type Ga.

A t、、、 A s層5.厚さ0.5 tt mのp
型GaAs キャップ層を周知の液相エピタキシャル成
長層で形成する。
A t, , A s layer5. Thickness 0.5 tt m p
A GaAs type cap layer is formed using a well-known liquid phase epitaxial growth layer.

次に半絶縁性基板の段差の上側の部分を一部蝕刻する事
によって、n型GaAs4を層2を露出させる。次にこ
の導電層の一部を残し、残りを蝕刻し半絶縁性基板1の
表面を霧出させる。この2回にわたる蝕刻で生ずる段差
の合計は3μmを越えない。
Next, the layer 2 of n-type GaAs 4 is exposed by partially etching the upper part of the step of the semi-insulating substrate. Next, a part of this conductive layer is left and the rest is etched to expose the surface of the semi-insulating substrate 1. The total height difference caused by these two etchings does not exceed 3 μm.

次に露出した半絶縁性基板上に、100〜150KeV
の加速電圧でSiイオンを打ち込む事によって、電気回
路の能動領域、電極領域、電気抵抗などを形成する。イ
オン打込み後、850Cの温度で、砒素雰囲気中におい
てアニールを行い、打込元素の適正なイオン化をうなが
す。しかるのちに、基板段差部にエピタキシャル成長層
弐面からZnを拡散し、活性領域に至る電流経路とする
Next, apply a voltage of 100 to 150 KeV on the exposed semi-insulating substrate.
By implanting Si ions at an acceleration voltage of , the active region, electrode region, electrical resistance, etc. of an electric circuit are formed. After ion implantation, annealing is performed at a temperature of 850 C in an arsenic atmosphere to promote proper ionization of the implanted elements. Thereafter, Zn is diffused into the stepped portion of the substrate from the second surface of the epitaxial growth layer to form a current path leading to the active region.

次に再び露出した半絶縁性基板上にもどり、ここに、先
ずCVD法によって810.絶縁膜を約0.5μmの厚
さ形成した後真空金属蒸着とリフトオフの方法によって
オーミック電極、ショットキイ電極、電極間配線を行う
。オーミック電極はAuQ e/ N i / A ”
 、ショットキィ電極及び電極間配線はCr/Auの逐
次蒸着によった。なお電極間配線に先立ってCVD法に
よりPSG膜(リンガラス)を被着させ、必要な部分を
絶縁する。
Next, return to the exposed semi-insulating substrate, and first 810. After forming an insulating film to a thickness of about 0.5 μm, ohmic electrodes, Schottky electrodes, and inter-electrode wiring are formed by vacuum metal deposition and lift-off. Ohmic electrode is AuQe/Ni/A”
, Schottky electrodes and inter-electrode wiring were formed by sequential Cr/Au deposition. Note that prior to wiring between electrodes, a PSG film (phosphorus glass) is deposited by CVD to insulate necessary portions.

また電極間配線は、金属を蒸着後イオンミリングによっ
て所望のパターンに加工する方法によっても作成する事
ができた。
The inter-electrode wiring could also be created by depositing metal and then processing it into a desired pattern by ion milling.

上述の方法でレーザ部分と電気回路部分とを形成した後
、1チツプずつにウェハーから、襞間とスクライビング
によって切シ出し、ステムに貼り付け、所要の外部配線
kAu線の熱圧着によって行った。
After forming the laser part and the electric circuit part in the above-described manner, each chip was cut out from the wafer by crevices and scribing, attached to the stem, and the required external wiring kAu wire was bonded by thermocompression.

本発明による構造により、レーザ部と電気回路部との間
の段差を3μm以下にすることが可能になった。従って
、電気回路部に写真蝕刻法によって最小寸法1μmの微
細パターンを形成することができた。本発明の素子にお
けるレーザの動作閾値は10〜30mAKiで低くする
ことができる。
The structure according to the present invention makes it possible to reduce the step difference between the laser section and the electric circuit section to 3 μm or less. Therefore, it was possible to form a fine pattern with a minimum dimension of 1 μm on the electric circuit portion by photolithography. The operating threshold of the laser in the device of the invention can be as low as 10-30 mAKi.

なお、上述の例ではGaAs−GaAtAs系材料に関
して説明したが、レーザ発振を実現し得る■−V族化合
物半4体、タトエばI n P −InGaAsP系の
材料においても同様に本発明の実現が可能である。
Although the above example has been explained with respect to GaAs-GaAtAs-based materials, the present invention can also be realized in the same way with materials such as ■-V group compound semi-quadratures that can realize laser oscillation, and Tatoe's InP-InGaAsP-based materials. It is possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は半絶縁性Ga A s基板状に、ダブルへテロ
構造のレーザダイオード吉、FETとを横向きに並列的
に集積化した例を示す斜視図、第2図は半導体レーザの
活性層の形状を示す断面図である。 1・・・半絶縁性()a As基板、2・・・n−Ga
As導電層、3・ n−QaAtAsクラッド層、4 
”・Q a A 8活性層、5”’p GaA4Asク
ラッド層、6 ・I) −GaAsキャップ層、7.1
5・・・5iOt絶縁膜、8゜13.14・・・Cr/
Auポンプイングツ(ラド、9・・・Cr / A u
レーザストライプ電極、10.12・ AuGe/N 
i/Au、t−ミック電極、11・・・Ti/Pt/A
″Uショットキィ電極。 特許出願人 、ヤ111扶人・ ル水六−
Fig. 1 is a perspective view showing an example in which double heterostructure laser diodes and FETs are integrated horizontally in parallel on a semi-insulating GaAs substrate, and Fig. 2 shows an example of the active layer of a semiconductor laser. It is a sectional view showing a shape. 1...Semi-insulating ()a As substrate, 2...n-Ga
As conductive layer, 3.n-QaAtAs cladding layer, 4
"・Q a A 8 active layer, 5"'p GaA4As cladding layer, 6 ・I) -GaAs cap layer, 7.1
5...5iOt insulating film, 8°13.14...Cr/
Au Pumpings (Rad, 9...Cr/A u
Laser stripe electrode, 10.12・AuGe/N
i/Au, t-mic electrode, 11...Ti/Pt/A
``U Schottky electrode. Patent applicant: Ya111 Fujin Le Mizu6-

Claims (1)

【特許請求の範囲】[Claims] 1、半絶縁性半導体基板の所望領域に凹部を形成し、前
記凹部の段差領域を少なくとも覆うが如く導電層および
レーザ発振をせしめるための活性層を含む複数の半導体
層を前記半絶縁性半導体基板の所定領域に積層し、前記
活性層は前記段差領域部で残余の部分に比して厚い領域
會有し、且前記半絶縁性半導体基板の残余の部分に電子
回路が集積化されてなることを特徴とする半導体レーザ
装置。
1. A recess is formed in a desired region of a semi-insulating semiconductor substrate, and a plurality of semiconductor layers including a conductive layer and an active layer for laser oscillation are formed on the semi-insulating semiconductor substrate so as to cover at least the stepped region of the recess. , the active layer has a thicker region in the stepped region than the remaining portion, and an electronic circuit is integrated in the remaining portion of the semi-insulating semiconductor substrate. A semiconductor laser device characterized by:
JP57115341A 1982-07-05 1982-07-05 Semiconductor laser device Pending JPS596587A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57115341A JPS596587A (en) 1982-07-05 1982-07-05 Semiconductor laser device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57115341A JPS596587A (en) 1982-07-05 1982-07-05 Semiconductor laser device

Publications (1)

Publication Number Publication Date
JPS596587A true JPS596587A (en) 1984-01-13

Family

ID=14660139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57115341A Pending JPS596587A (en) 1982-07-05 1982-07-05 Semiconductor laser device

Country Status (1)

Country Link
JP (1) JPS596587A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5670681A (en) * 1979-11-14 1981-06-12 Hitachi Ltd Semiconductor luminous element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5670681A (en) * 1979-11-14 1981-06-12 Hitachi Ltd Semiconductor luminous element

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