JPS5964517A - Formation of oxide film - Google Patents
Formation of oxide filmInfo
- Publication number
- JPS5964517A JPS5964517A JP16952782A JP16952782A JPS5964517A JP S5964517 A JPS5964517 A JP S5964517A JP 16952782 A JP16952782 A JP 16952782A JP 16952782 A JP16952782 A JP 16952782A JP S5964517 A JPS5964517 A JP S5964517A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- polysilicon
- ion
- formation
- dielectric strength
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【発明の詳細な説明】
(1)発明の技術分野
不発明は、酸化膜の形成方法、特に半導体装置に用いる
ポリシリコン酸化膜の形成方法に係る。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The invention relates to a method of forming an oxide film, particularly a method of forming a polysilicon oxide film used in a semiconductor device.
(2)従来技術と問題点
第1図は1トランジスタ・lセルのダイナミック・メモ
リの1例を示すものである。例えば、p型シリコン基板
1に、ドレイン2、絶縁膜3上のゲート4、ソース(反
転層)5からなるトランジスタ(FET )と、キャパ
シタ電極6、絶縁膜7、反転層(キャパシタ電極)5か
らなるキャパシタとが形成され、これらでメモリ・セル
が(n成されている。ゲート4及びキャパシタ電極6は
普通にはポリシリコンでJ構成され、これらの間にr2
緑膜8が存在するが、この絶縁膜8はキャパシタ電極6
のポリシリコン全熱酸化して形成される。しかし、最近
、メモリ谷猪が64−?ロビlトから256キロビツト
、さらVこ1メガビツトへと増大するにつれて、セル寸
法が小さくなり、絶縁1模も薄く形成せざるを得す、欠
陥のない絶縁耐圧の大きい膜を精度よく形成することが
必要になってきている。(2) Prior Art and Problems FIG. 1 shows an example of a one-transistor/l-cell dynamic memory. For example, a transistor (FET) consisting of a drain 2, a gate 4 on an insulating film 3, and a source (inversion layer) 5 is formed on a p-type silicon substrate 1, a capacitor electrode 6, an insulating film 7, and an inversion layer (capacitor electrode) 5. The gate 4 and the capacitor electrode 6 are usually made of polysilicon, and there is an r2 capacitor between them.
There is a green film 8, and this insulating film 8 is connected to the capacitor electrode 6.
It is formed by total thermal oxidation of polysilicon. However, recently, Memory Tani boar is 64-? As the cell size increases from 256 kilobits to 1 megabit, the cell size becomes smaller and the insulation layer must be made thinner.It is important to accurately form a defect-free film with high dielectric strength. is becoming necessary.
(3)発明の目的
こうしプζ従来技術に鑑み、本発明tよ、ポリシリL−
1ン酸化nQ1の耐圧を向上させることを目的とする。(3) Purpose of the Invention In view of the prior art, the present invention provides a polysilicon L-
The purpose is to improve the breakdown voltage of nQ1 oxide.
(4)発明の構成
そして、上記目的を達成するために、本発明は、多結晶
シリコンにイオン打ち込みを行ない、続いて熱処理して
核多結晶シリコンを熱酸化することを特徴とする酸化膜
の形成方法を提供する。(4) Structure of the Invention In order to achieve the above object, the present invention provides an oxide film characterized in that ion implantation is performed on polycrystalline silicon, followed by heat treatment to thermally oxidize the core polycrystalline silicon. A forming method is provided.
すなわち、本発明の方法では、従来のようにポリシリコ
ンを熱酸化する以前に、先ずポリシリコンにイオン打ち
込みを行なう。このイオン打ち込みは、ポリシリコンの
結晶粒を微細化(アモルファス化)し、続いて行なう熱
r1安比(lこおいて、コ皓晶粒が大きいと鹸化が結晶
粒の内部までは進行しにくいという不都合を軽減又は除
去する。従って、イオン打ち込喫全?:fなったポリシ
リコン金熱酸化すれば、イオン打ち込みなしの場合より
も、ポリシリコンがより容易に、より均一に酸化さ′i
L、そしてより緻密な酸化膜を与える。従って、ポリシ
リコン酸化膜の耐圧も向上する。又、打ち込むイオンは
酸素イオン(0+) 、窒素イオン(N+)、アルゴン
イオン(Ar+) などのいずれでもよいが、酸素イ
オン(0+)を用いれば、上記の効果に加えて、打ち込
ま九た酸素・fオンがポリシリコンの内部における酸化
を促進するので、より好ましい結果會得ることができる
。尚、イオン打ち込みの時間は短時間で済むことはグロ
セヌ上部合がよい。That is, in the method of the present invention, ions are first implanted into polysilicon before thermally oxidizing the polysilicon as in the conventional method. This ion implantation refines the polysilicon crystal grains (makes them amorphous), and then heats them. Therefore, thermal oxidation of polysilicon with ion implantation will oxidize the polysilicon more easily and more uniformly than without ion implantation.
L, and gives a denser oxide film. Therefore, the breakdown voltage of the polysilicon oxide film is also improved. In addition, the implanted ions may be oxygen ions (0+), nitrogen ions (N+), argon ions (Ar+), etc., but if oxygen ions (0+) are used, in addition to the above effects, the implanted Since f-on promotes oxidation inside the polysilicon, more favorable results can be obtained. Incidentally, it is preferable that the ion implantation takes a short time in the case of the Glossene upper part.
(5)発明の′μ施例
前に述べた1トランジスタ・1セルのダイナミック・メ
モリにおけるキャパシタ電極6とゲート4間のポリシリ
コン酸化膜8の形成に、本発明の方法を適用する(第2
図〜第4図参照)。シリコン基板又はウェーハ1表面に
絶縁膜7全形成し、その上にポリシリコン全厚さ400
0Aに被着し、拡散処理でシート抵抗全調整後、バター
ニングして、キャパシタ電極6を形成する。それから、
0+。(5) Example of the invention The method of the present invention is applied to the formation of the polysilicon oxide film 8 between the capacitor electrode 6 and the gate 4 in the one-transistor, one-cell dynamic memory described above (Second
(See Figures 4 to 4). The entire insulating film 7 is formed on the surface of the silicon substrate or wafer 1, and a polysilicon film with a total thickness of 400 mm is formed on it.
The capacitor electrode 6 is formed by adhering to 0A, fully adjusting the sheet resistance by diffusion treatment, and then patterning. after that,
0+.
N+等をドーズJl、 10 ’ ” /cd、打ち込
みエネルギー10〜100keVで、深さ数100A程
度に(層]、 0 )イオン打ち込みする。次いで一1
100℃の温度で熱酸化(0□)又はアニール(N2)
L、厚さ1000〜3000Aの酸化膜8を形成す
る0その後通常の工程でダイナミック・メモリを作成す
る。こうして形成されるポリシリコン酸化膜8は従来よ
りもより均質でより緻密な酸化膜を与え、耐圧も大きく
向上する。N+ etc. are implanted to a depth of about 100 A (layer) at a dose of 10'/cd and an implantation energy of 10 to 100 keV.
Thermal oxidation (0□) or annealing (N2) at a temperature of 100℃
After that, a dynamic memory is fabricated by a normal process. The polysilicon oxide film 8 thus formed provides a more homogeneous and denser oxide film than the conventional one, and the withstand voltage is also greatly improved.
以上はダイナミ・Iり・メモリのポリシリコン層間絶縁
用の酸化膜形成に本発明を適用した例であるが、本発明
はスタ〜クドキャパシタの酸化膜形成その他にも適用で
きることは明らかである。The above is an example in which the present invention is applied to the formation of an oxide film for insulation between polysilicon layers in dynamics, IRI, and memory, but it is clear that the present invention can also be applied to the formation of an oxide film for stacked capacitors, etc. .
(6)発明の効果
本発明に依ればポリシリコン熱酸化膜の耐圧を向上させ
ることが可能になる。(6) Effects of the Invention According to the present invention, it is possible to improve the breakdown voltage of a polysilicon thermal oxide film.
第1図はダイナミック・メモリの1折面図、第2図から
第4図は本発明の詳細な説明する工8順の19i面図で
ある。
4:ゲート(ポリシリコン)、6;キャパシタff電極
(ホlJシリコン)、8:ポリシリコン酸化膜、10:
イオン打ぢ込み層。
特許出願人
富士通株式会社
特許出願代理人
弁理士 °1 木 朗
弁理士 西 舘 和 之
弁理士 内 1)幸 男
弁理士 山 口 昭 之
98−
第 1図
第3図
−99−、−FIG. 1 is a 1-fold view of the dynamic memory, and FIGS. 2 to 4 are 19i side views of a step 8 for explaining the present invention in detail. 4: Gate (polysilicon), 6: Capacitor ff electrode (HOLJ silicon), 8: Polysilicon oxide film, 10:
Ion implantation layer. Patent applicant: Fujitsu Ltd. Patent attorney: °1 Akira Ki, patent attorney: Kazuyuki Nishidate, patent attorney: 1) Yukio, patent attorney: Akira Yamaguchi, 98- Figure 1 Figure 3-99-,-
Claims (1)
て熱処理して該多結晶シリコンを熱酸化することヲlt
♀徴とする酸化膜の形成方法。1. Do not implant ions into polycrystalline silicon, then heat-treat and thermally oxidize the polycrystalline silicon.
♀Method for forming oxide film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16952782A JPS5964517A (en) | 1982-09-30 | 1982-09-30 | Formation of oxide film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16952782A JPS5964517A (en) | 1982-09-30 | 1982-09-30 | Formation of oxide film |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5964517A true JPS5964517A (en) | 1984-04-12 |
JPH021232B2 JPH021232B2 (en) | 1990-01-10 |
Family
ID=15888150
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16952782A Granted JPS5964517A (en) | 1982-09-30 | 1982-09-30 | Formation of oxide film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5964517A (en) |
-
1982
- 1982-09-30 JP JP16952782A patent/JPS5964517A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH021232B2 (en) | 1990-01-10 |
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