JPH021232B2 - - Google Patents

Info

Publication number
JPH021232B2
JPH021232B2 JP16952782A JP16952782A JPH021232B2 JP H021232 B2 JPH021232 B2 JP H021232B2 JP 16952782 A JP16952782 A JP 16952782A JP 16952782 A JP16952782 A JP 16952782A JP H021232 B2 JPH021232 B2 JP H021232B2
Authority
JP
Japan
Prior art keywords
polysilicon
oxide film
ions
present
capacitor electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP16952782A
Other languages
Japanese (ja)
Other versions
JPS5964517A (en
Inventor
Yoshimi Shiotani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16952782A priority Critical patent/JPS5964517A/en
Publication of JPS5964517A publication Critical patent/JPS5964517A/en
Publication of JPH021232B2 publication Critical patent/JPH021232B2/ja
Granted legal-status Critical Current

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  • Silicon Compounds (AREA)
  • Physical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】 (1) 発明の技術分野 本発明は、酸化膜の形成方法、特に半導体装置
に用いるポリシリコン酸化膜の形成方法に係る。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of forming an oxide film, particularly a method of forming a polysilicon oxide film used in a semiconductor device.

(2) 従来技術と問題点 第1図は1トランジスタ・1セルのダイナミツ
ク・メモリの1例を示すものである。例えば、p
型シリコン基板1に、ドレイン2、絶縁膜3上の
ゲート4、ソース(反転層)5からなるトランジ
スタ(FET)と、キヤパシタ電極6、絶縁膜7、
反転層(キヤパシタ電極)5からなるキヤパシタ
とが形成され、これらでメモリ・セルが構成され
ている。ゲート4及びキヤパシタ電極6は普通に
はポリシリコンで形成され、これらの間に絶縁膜
8が存在するが、この絶縁膜8はキヤパシタ電極
6のポリシリコンを熱酸化して形成される。しか
し、最近、メモリ容量が64キロビツトから256キ
ロビツト、さらに1メガビツトへと増大するにつ
れて、セル寸法が小さくなり、絶縁膜も薄く形成
せざるを得ず、欠陥のない絶縁耐圧の大きい膜を
精度よく形成することが必要になつてきている。
(2) Prior Art and Problems Figure 1 shows an example of a one-transistor, one-cell dynamic memory. For example, p
A transistor (FET) consisting of a drain 2, a gate 4 on an insulating film 3, a source (inversion layer) 5, a capacitor electrode 6, an insulating film 7,
A capacitor consisting of an inversion layer (capacitor electrode) 5 is formed, and a memory cell is constituted by these. The gate 4 and the capacitor electrode 6 are usually formed of polysilicon, and an insulating film 8 exists between them, and this insulating film 8 is formed by thermally oxidizing the polysilicon of the capacitor electrode 6. However, as memory capacity has recently increased from 64 kilobits to 256 kilobits and then to 1 megabit, cell dimensions have become smaller and insulating films have to be made thinner. It has become necessary to form

(3) 発明の目的 こうした従来技術に鑑み、本発明は、ポリシリ
コン酸化膜の耐圧を向上させることを目的とす
る。
(3) Purpose of the Invention In view of these conventional techniques, the present invention aims to improve the withstand voltage of a polysilicon oxide film.

(4) 発明の構成 そして、上記目的を達成するために、本発明
は、多結晶シリコン層の表面部にイオン打込みを
行なつた後、酸素含有雰囲気中で熱処理して多結
晶シリコン層表面を良質な熱酸化膜に変換するこ
とを特徴とする熱酸化膜の形成方法を提供する。
(4) Structure of the Invention In order to achieve the above object, the present invention implants ions into the surface of a polycrystalline silicon layer, and then heat-treats the surface of the polycrystalline silicon layer in an oxygen-containing atmosphere. Provided is a method for forming a thermal oxide film, which is characterized by converting the film into a high-quality thermal oxide film.

すなわち、本発明の方法では、従来のようにポ
リシリコンを熱酸化する以前に、先ずポリシリコ
ンにイオン打ち込みを行なう。このイオン打ち込
みは、ポリシリコンの結晶粒を微細化(アモルフ
アス化)し、続いて行なう熱酸化において、結晶
粒が大きいと酸化が結晶粒の内部までは進行しに
くいという不都合を軽減又は除去する。従つて、
イオン打ち込みを行なつたポリシリコンを熱酸化
すれば、イオン打ち込みなしの場合よりも、ポリ
シリコンがより容易に、より均一に酸化され、そ
してより緻密な酸化膜を与える。従つて、ポリシ
リコン酸化膜の耐圧も向上する。又、打ち込むイ
オンは酸素イオン(O+)、窒素イオン(N+)、ア
ルゴンイオン(Ar+)などのいずれでもよいが、
酸素イオン(O+)を用いれば、上記の効果に加
えて、打ち込まれた酸素イオンがポリシリコンの
内部における酸化を促進するので、より好ましい
結果を得ることができる。尚、イオン打ち込みの
時間は短時間で済むことはプロセス上都合がよ
い。
That is, in the method of the present invention, ions are first implanted into polysilicon before thermally oxidizing the polysilicon as in the conventional method. This ion implantation makes the crystal grains of polysilicon fine (amorphous), and reduces or eliminates the disadvantage that, in the subsequent thermal oxidation, if the crystal grains are large, oxidation is difficult to proceed to the inside of the crystal grains. Therefore,
Thermal oxidation of ion-implanted polysilicon oxidizes the polysilicon more easily, more uniformly, and provides a denser oxide film than without ion implantation. Therefore, the breakdown voltage of the polysilicon oxide film is also improved. In addition, the ions to be implanted may be oxygen ions (O + ), nitrogen ions (N + ), argon ions (Ar + ), etc.
If oxygen ions (O + ) are used, in addition to the above effects, the implanted oxygen ions promote oxidation inside the polysilicon, so more favorable results can be obtained. Note that it is convenient for the process that the ion implantation can be performed in a short time.

(5) 発明の実施例 前に述べた1トランジスタ・1セルのダイナミ
ツク・メモリにおけるキヤパシタ電極6とゲート
4間のポリシリコン酸化膜8の形成に、本発明の
方法を適用する(第2図〜第4図参照)。シリコ
ン基板又はウエーハ1表面に絶縁膜7を形成し、
その上にポリシリコンを厚さ4000Åに被着し、拡
散処理でシート抵抗を調整後、パターニングし
て、キヤパシタ電極6を形成する。それから、
O+,N+等をドーズ量1018/cm3、打ち込みエネル
ギー10〜100keVで、深さ数100Å程度に(層10)
イオン打ち込みする。次いで、1100℃の温度で熱
酸化(O2)し、厚さ1000〜3000Åの酸化膜8を
形成する。その後通常の工程でダイナミツク・メ
メモリを作成する。こうして形成されるポリシリ
コン酸化膜8は従来よりもより均質でより緻密な
酸化膜を与え、耐圧も大きく向上する。
(5) Embodiments of the Invention The method of the present invention is applied to the formation of the polysilicon oxide film 8 between the capacitor electrode 6 and the gate 4 in the one-transistor, one-cell dynamic memory described above (see FIGS. (See Figure 4). Forming an insulating film 7 on the surface of the silicon substrate or wafer 1,
Polysilicon is deposited thereon to a thickness of 4000 Å, the sheet resistance is adjusted by diffusion treatment, and then patterned to form the capacitor electrode 6. after that,
O + , N +, etc. are implanted at a dose of 10 18 /cm 3 and an implantation energy of 10 to 100 keV to a depth of about 100 Å (layer 10).
Implant ions. Next, thermal oxidation (O 2 ) is performed at a temperature of 1100° C. to form an oxide film 8 with a thickness of 1000 to 3000 Å. Dynamic memory is then created using the normal process. The polysilicon oxide film 8 thus formed provides a more homogeneous and denser oxide film than the conventional one, and the withstand voltage is also greatly improved.

以上はダイナミツク・メモリのポリシリコン層
間絶縁用の酸化膜形成に本発明を適用した例であ
るが、本発明はスタツクドキヤパシタの酸化膜形
成その他にも適用できることは明らかである。
The above is an example in which the present invention is applied to the formation of an oxide film for insulation between polysilicon layers in a dynamic memory, but it is clear that the present invention can also be applied to the formation of an oxide film for stacked capacitors and other applications.

(6) 発明の効果 本発明に依ればポリシリコン熱酸化膜の耐圧を
向上させることが可能になる。
(6) Effects of the Invention According to the present invention, it is possible to improve the breakdown voltage of a polysilicon thermal oxide film.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はダイナミツク・メモリの断面図、第2
図から第4図は本発明の実施例を説明する工程順
の断面図である。 4:ゲート(ポリシリコン)、6:キヤパシタ
電極(ポリシリコン)、8:ポリシリコン酸化膜、
10:イオン打ち込み層。
Figure 1 is a cross-sectional view of dynamic memory, Figure 2
FIGS. 4 to 4 are cross-sectional views in order of steps for explaining an embodiment of the present invention. 4: Gate (polysilicon), 6: Capacitor electrode (polysilicon), 8: Polysilicon oxide film,
10: Ion implantation layer.

Claims (1)

【特許請求の範囲】[Claims] 1 多結晶シリコン層の表面部にイオン打込みを
行なつた後、酸素含有雰囲気中で熱処理して多結
晶シリコン層表面を良質な熱酸化膜に変換するこ
とを特徴とする熱酸化膜の形成方法。
1. A method for forming a thermal oxide film, which comprises implanting ions into the surface of a polycrystalline silicon layer, and then performing heat treatment in an oxygen-containing atmosphere to convert the surface of the polycrystalline silicon layer into a high-quality thermal oxide film. .
JP16952782A 1982-09-30 1982-09-30 Formation of oxide film Granted JPS5964517A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16952782A JPS5964517A (en) 1982-09-30 1982-09-30 Formation of oxide film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16952782A JPS5964517A (en) 1982-09-30 1982-09-30 Formation of oxide film

Publications (2)

Publication Number Publication Date
JPS5964517A JPS5964517A (en) 1984-04-12
JPH021232B2 true JPH021232B2 (en) 1990-01-10

Family

ID=15888150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16952782A Granted JPS5964517A (en) 1982-09-30 1982-09-30 Formation of oxide film

Country Status (1)

Country Link
JP (1) JPS5964517A (en)

Also Published As

Publication number Publication date
JPS5964517A (en) 1984-04-12

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