JPS5963751U - interface circuit - Google Patents
interface circuitInfo
- Publication number
- JPS5963751U JPS5963751U JP15884882U JP15884882U JPS5963751U JP S5963751 U JPS5963751 U JP S5963751U JP 15884882 U JP15884882 U JP 15884882U JP 15884882 U JP15884882 U JP 15884882U JP S5963751 U JPS5963751 U JP S5963751U
- Authority
- JP
- Japan
- Prior art keywords
- microcomputer
- data
- interface circuit
- output data
- inverts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Multi Processors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案になるインターフェース回路の−・実施例の
回路図である。
１．２・・・マイクロ・コンピュータ、３，４，５，７
゜８．１０・・・電源端子、６，９・・・アナログスイ
ッチ、Ｒ□〜Ｒ７・・・抵抗、Ｑ□＋ Ｑ２・・・トラ
ンジスタ、Ｄｌ・・・ダイオード。The figure is a circuit diagram of an embodiment of the interface circuit according to the present invention. 1.2...Micro computer, 3, 4, 5, 7
゜8.10... Power supply terminal, 6,9... Analog switch, R□~R7... Resistor, Q□+ Q2... Transistor, Dl... Diode.
Claims (1)
あるとき第２のマイクロ・コンピュータの出力データに
より開閉成されて該第２のマイクロ・コンピュータの出
力データを反転して該第１のマイクロ・コンピュータに
供給する第一１のスイッチング素子と、該第１のマイク
ロ・コンピュータがデータの出力状態であるとき該第１
のマイクロ・コンピュータの出力データにより□開閉成
され−ｃ該第１のマイクロ・コンピュータの出力データ
を反転して該第２のマイクロ・コンピュータに供給する
第２のスイッチング素子とよりなり、該第１及び第２の
マイクロ・コンピュータ間で双方向性のデータを受は渡
すよう構成してなるインターフェース回路。When the first microcomputer is in the data input state, it is opened and closed by the output data of the second microcomputer, inverts the output data of the second microcomputer, and inputs the data to the first microcomputer. a first switching element that supplies data to the first microcomputer;
a second switching element which is opened and closed by the output data of the first microcomputer and inverts the output data of the first microcomputer and supplies it to the second microcomputer; and an interface circuit configured to receive and pass bidirectional data between the second microcomputer and the second microcomputer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15884882U JPS5963751U (en) | 1982-10-20 | 1982-10-20 | interface circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15884882U JPS5963751U (en) | 1982-10-20 | 1982-10-20 | interface circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5963751U true JPS5963751U (en) | 1984-04-26 |
Family
ID=30349834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15884882U Pending JPS5963751U (en) | 1982-10-20 | 1982-10-20 | interface circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5963751U (en) |
-
1982
- 1982-10-20 JP JP15884882U patent/JPS5963751U/en active Pending
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