JPS5963577A - Voltage generator - Google Patents

Abstract

PURPOSE:To remove an offset voltage, and to reduce the number of D-A converters to only one set for every voltage generating circuit, and to reduce the cost by varying an offset bias which is in a digital signal state. CONSTITUTION:A data converter 201 which performs addition and subtraction according to polarity data is provided, and a digital signal corresponding to the most significant digit bit value of set data 102 is applied as the offset bias by this data setter 201; set voltage data is added on the positive polarity side based upon the bias or subtracted on the negative polarity side, thus performing data conversion. The adding operation and subtracting operation of this data converter 201 are switched according to the polarity data stored in a polarity data register 107 and the arithmetic result is supplied to a D-A converter 202; the converter 202 has a normal output terminal 202a and a complement output terminal 202b, and a current-voltage converter 104 is connected to the normal output terminal 202a to obtain a plus analog voltage. Further, the current-voltage converter 104' consisting of a resistor 203 is connected to the complement output terminal 202b to obtain an analog voltage in negative polarity.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage generator used, for example, in an IC tester, and particularly aims to provide a voltage generator that has a simplified circuit structure and can be manufactured at low cost.

<Background of the Invention> For example, an IC tester tests ICs with different standards, so each time an IC with a different standard is tested, it is necessary to check whether the drive voltage of the signal input to the IC under test and the readout output are H logic. It is necessary to set a reference voltage, etc. for determining whether the logic is L or not. It is necessary to prepare several types of each of these voltages for each terminal of the IC under test. Since the voltage must be controlled independently for each terminal, a large number of voltage generators are required. Therefore, it would be impossible to manually set the voltages of each of these voltage generators, but conventionally, the set voltages are stored in a memory etc., and the data is read from this memory and converted into D-hg.
A desired set voltage is obtained from the D-Ai conversion output. Since the number of D-A converters required is equal to the number of required set voltages, there is a disadvantage that the number of D-A converters is large and the cost is high.

However, as will be described later, offset data is stored for each voltage generator in order to remove the offset voltage of a buffer amplifier, etc. that takes out the output of the D-A converter, and the offset data is converted into a D-A converter. Then, the D-Ax converted output is subtracted from the set voltage. Therefore, there is a drawback that the number of DA converters increases.

<Conventional Description> FIG. 1 shows a conventional voltage generator. In this figure, only the part that generates one set voltage is shown. In the figure, 101 indicates a register that stores digital data corresponding to the voltage value to be output. Data 102 is given to this register 101 from a memory (not particularly shown), and the data is stored. The data stored in register 101 is D
-A converter 103, and this D-A converter 103
is converted to an analog value at . Since the DA converter is generally of the current output type, a current-voltage converter 104 is provided on the output side of the DA converter 103 to convert it into a voltage signal.

The output voltage of the current-voltage converter 104 is supplied as is to the polarity selection circuit 106 through the polarity inverter 105.

- The polarity selection circuit 106 has two switches 106a and 1
06b are provided, and these switches 1 (16a and 10
6b selects either a positive or negative voltage based on the polarity data stored in the polarity data register 107, and supplies the voltage of the selected polarity to the voltage adding circuit 108.

This voltage adder circuit 108 is provided to remove the offset h% pressure generated in the buffer amplifier 109 and other analog circuits connected to the subsequent stage.

If an offset voltage exists in the analog circuit after the buffer amplifier 109, the offset voltage is added to the D-A conversion value of the set voltage data stored in the register 101, and the voltage is different from the voltage that should be applied. There is an inconvenience that the force 1 pressure is given as a set value.

Therefore, a value equivalent to the offset voltage generated in the analog circuit after the buffer amplifier 109 is generated from the correction circuit 111, and the correction voltage output from the correction circuit 111 is applied to the voltage addition circuit 108 to remove the offset voltage. There is.

The correction circuit 111 includes a register 112, a DA converter 113, and a current-voltage conversion circuit 1, similar to the voltage generator described above.
14, stores data 115 corresponding to the offset voltage value of the analog circuit measured in advance in the register 112 from the memory, and stores the data value in the D-A.
The voltage is converted and applied to the voltage adding circuit 108.

<Disadvantages of the Conventional Method> As mentioned above, the conventional method requires the same number of D-A converters 103 as the number of channels, and also requires a D-to-A converter 103 for each channel.
-A converter 113 is required. Therefore, the number of D-A2m devices increases, resulting in high cost. There is still a drawback that the circuit becomes larger and more complex.

<Object of the invention> This invention omit the DA converter on the correction circuit 111 side,
The purpose is to reduce the cost by simplifying the circuit.

<Summary of the Invention> This invention adds or subtracts an offset voltage equivalent value to or from the set voltage data in the digital signal state, removes the offset voltage equivalent value in the digital signal state, and It is configured to DA convert a digital signal from which an offset voltage equivalent value has been removed.

Therefore, according to the first aspect of the present invention, since the number of DA converters can be reduced to 11 in one channel, the number of DA converters can be reduced as a whole, and cost savings can be expected.

<Embodiment of the Invention> FIG. 2 shows an embodiment of the invention. In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals. In this invention, for example, a data converter 201 capable of performing addition and subtraction operations according to polarity data is provided, and this data converter 201 converts a digital coefficient corresponding to the value of the most significant bit of the setting data 102. Add it as an offset bias, add the set voltage data around this offset bias on the positive polarity side, and subtract it on the negative polarity side to perform data conversion, and convert this digital signal into D-A. It is configured as follows.

The operation of data converter 201 will be explained in more detail. Setting 'paper pressure data 10 given from register 101
For example, if 2 is data of 4 bits and 5 bits, then from the register 112 configuring the correction circuit 111, an offset bias r 1 having logic "1" is generated in the upper part of the data.
,0,0,0. Give Oj.

For this offset bias, the data converter 201 performs an addition operation based on the set voltage data inputted from the register 101 and the positive polarity data. If the set voltage data is still negative, a subtraction operation is performed. The results of this addition and subtraction are shown in FIG. In Figure 3, B
1-B5 indicates the bit number, and Bs indicates the MSB. As is clear from this figure, the upper side around the offset bias 301 shows the value obtained by adding positive data to the offset bias 301, and the lower side does not show the value obtained by subtracting negative data from the offset bias 301. The addition operation and subtraction operation of the data converter 201 are switched by the polarity data register 10.
This is done according to the polarity data stored in 7.

At this '7, the lower 4 bits g+ to B4 of the 'H- result are given to the DA converter 202. This D-A converter 202
has a normal output width 202a and a complement output terminal 202b, and in this example performs DA conversion of 4-bit digital data.

The normal output terminal 202a of the D-A converter 202 has a current of −
A voltage converter 104 is connected, and this current-voltage replacer 104
Obtain a positive analog voltage from

Further, a current-voltage converter 104° constituted by a resistor 203 is connected to the complement output terminal 202b, and a negative analog voltage generated by the current flowing through the resistor 203 is obtained.

The positive and negative analog voltages output from these current-voltage converters 104 and 104' are applied to the polarity selection circuit 106,
Either a positive or negative analog voltage is taken out from this polarity selection circuit 106 and outputted to an output terminal 110 through an amplifier 109 . Switches 106a and 106b of polarity selection circuit 106 are controlled on and off by the logic of the most significant bit B5 output from data converter 201. When the most significant bit B5 output from the adder/subtracter 201 is logic "1", the switch 106a is turned on and a positive analog voltage is taken out. If the most significant bit B5 is rO'M+A, the switch 106b is turned on and a negative analog voltage is taken out.

The relationship between the normal output terminal 202a and the complement output terminal 202b of the Dh converter 202 is as shown in FIG. 401a and 401b in FIG.

401c and 401d are switches each controlled by a digital signal. Terminal 402a.

Digital signals are provided to 402b, 402c, and 402d. Terminal 402a is LSB, terminal 402d is MSB
It is. L is connected to each of these terminals 402a to 402d.
When logic is given, switches 401a to 401d
The terminals 402a to 402d are switched to the contact a side, and when the KH logic of each terminal 402a to 402d is violated, the switches 401a to 401d are controlled to be switched to the contact side.

Therefore, if all the digital signals of 97F4 children 402a to 402d are LMi city, the normal output terminal 202a
The current flowing through is zero. On the other hand, complement output terminal 2
All current sources 403a, 403b, 403c are connected to 02b.
.

All the currents 1.2I, 4I, and 8I of 403d flow together. When the terminal 402a reaches the H logic, the switch = 401a changes to a contact point, and the normal output terminal 202
The current ■ of the aK current source 403a is output. In addition to this, the current at the complement output terminal 203b is (2I+4I+8I). In this way, the normal output terminal 202a and the complement output terminal 2
The output currents of 02b change complementary to each other.

FIG. 5 shows the relationship between digital data and analog output. In the digital data shown in FIG. 5, the bit shown in parentheses is the MSB, and the polarity selection circuit 106 is controlled by the logic of the MSB.

The case where the buffer amplifier 109 has an offset It pressure will be explained here. To measure the offset voltage, data rO, 0, 0, OJ is stored in the register 101, and the digital data ``ro, o, o, o'' is subjected to DA conversion in the DA converter 202. This D-h converted output is given to the buffer amplifier 109, and the voltage at the output terminal 110 is measured. At this time, the voltage output to the output terminal 110 is the offset voltage.

The resistor 112 is set so that this offset voltage becomes zero.
The offset bias stored in [Fine adjustment of direct.

For example, if an offset voltage of +1 mV is generated, the value of the offset bias is changed in a direction to cancel that value. In other words, the offset bias is r 1 , OJ 0 , 0
, Oj to ro, 1, 1 . t, o”.

Further, when the offset voltage is, for example, -1rnV, the value of the offset bias is changed to rl, O, O, O, IJ in a direction to cancel this negative polarity offset voltage.

<Effects of the Invention> As described above, according to the present invention, the offset frost 4 pressure can be removed by changing the offset bias in the digital signal state. Therefore, one DA converter can be used for one voltage generation circuit, and cost reduction can be expected.

<Other Embodiments of the Invention> In the above description, one voltage generator is configured by one D-A converter 202, but as shown in FIG. A tamer multiplexer 601 is provided in accordance with the rule, and this demultiplexer 601
A plurality of sample and hold circuits 602a, 602
The output voltage of the buffer amplifier 109 is distributed to the registers 101 and 107 in synchronization with this distribution.
, 112 is sequentially rewritten to the data required for each channel, it is possible to output multi-channel voltages with one D-A converter 202, which is expected to further reduce costs. can.

In FIG. 6, 603 indicates a timing generator, and the setting voltage data, polarity data, and offset bias data of each channel read from the memory by the timing signal output from the timing generator 603 are stored in registers 101, 107, and 112. The operation of sequentially importing the data is performed. Further, each of the registers 101, 109, and 112 may be a memory such as a RAM, and the data of each channel may be directly output from this memory and input to the data converter 201.

Although the data converter 201 has been described above as an adder/subtracter, another method is to output positive data as is,
The data conversion circuit 201 can also be configured by a circuit that converts negative data into its complement.

An example is shown in FIG. In FIG. 7, 701 indicates a buffer. Id IiM data is given to this buffer 701 . 702a, 702b, 702c, 702
d each represents an exclusive OR circuit. Polarity data is applied to one input terminal of each of these exclusive-rational sum circuits 702a to 702d, and setting voltage data is applied to the other input terminal.

Therefore, in the case of positive polarity data, the exclusive OR circuit 702
Since a logic "1" is input to each of the input terminals a to 702d, the set voltage data is output as is. In addition, in the case of negative polarity data, since "0" logic is applied to one input terminal of each of the exclusive logic circuits 702a to 702d, the set voltage data is inverted to the opposite logic by 1 and converted into a complement. is output. The logic converted to this complement is the offset bias 3 shown in Figure 3.
It corresponds to the logic of B1 to B4 shown below 01.

In this way, the data converter 201 can be configured not only by an addition/subtraction circuit but also by a circuit that converts input data into a complement in accordance with annotation data.

[Brief Description of the Drawings] Fig. 1 is a block diagram for explaining a conventional voltage generator, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a block diagram for explaining a conventional voltage generator.
4 is a connection diagram showing an example of an r+-A converter used in the voltage generator of this invention, and FIG. 5 is a diagram for explaining a detailed explanation of this invention. FIG. 6 is a block diagram showing another embodiment of this invention, and FIG. 7 is a connection diagram showing another example of a data converter used in this invention. 201: Data converter, 202: 1)-A converter, 10
6: Polarity selection circuit.

Claims (1)

[Claims] t11A, data specifying the voltage value to be output, polarity data specifying the polarity of the voltage to be output, and an offset bias value are input, and for input data of one polarity, the input data and offset are input. A data converter that adds data, adds 1 to the input data of the other polarity, subtracts the input data from the offset bias, and outputs it; A voltage generator comprising: a D-A converter having a complement output terminal; and a selection switch for selecting and outputting the output of the normal output terminal and the complement output terminal according to the polarity theta.