JPS5962216A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To obtain a D/A converting system to be outputted to a remote point with a simple constitution by storing a digital signal to be converted in an RAM and obtaining an objective analog signal via an integration circuit. CONSTITUTION:Information of 1 or 0 is written in the RAM3, and this information is read out suitably with an address data being the input digital signal, and this readout information is applied to a transistor 5 for light emitting diode drive via a buffer 4. The information is converted into an optical signal and led to a photodetector 8 located at a remote location via an optical fiber 7. The signal is converted into an analog signal at the integration circuit 9 and extracted as an analog output.

Description

[Detailed description of the invention] The present invention relates to a D-A conversion device.

The purpose of the present invention is to not only convert the input Denkle information (1) to the log information (G), but also to continuously output the converted analog information while storing it until the next human input signal changes. An object of the present invention is to provide an Il-/\conversion device that performs the following.

Another object of the present invention is to provide a D-Δ conversion device that outputs analog one-cog information converted at a remote point from a digital information input point.

Another object of the present invention is to provide a D-Δ converter that converts and outputs analog waveform information rather than a mere voltage value.

Still another object of the invention is to make g6 extremely compact.
The object of the present invention is to provide an I)-Δ conversion device that can be manufactured at low cost, has good stability, and low resolution.

In order to achieve the above objects, 1) -Δ conversion device of the present invention decodes (1) a high-level count for nI clock signals in a predetermined order and the state output of the high-level count. A data selector that repeats the address 1h setting in a predetermined order, and either '1' or 0' is written for each address.
0, a means for converting the output of the random access memory into an optical signal, an optical fiber for transmitting the optical signal, and smoothing the output waveform of the optical fiber. 8. Dano writes, f1 shift means to change the contents of access memory,
Once the digital information to be converted is stored in the access memory, the information converted to the output of the above-mentioned integrating circuit is J'.
It is characterized in that it is configured to obtain group information.

Below is a detailed description of the present invention. FIG. 1 shows a block diagram of an embodiment. The counter 1 counts each signal, and when the counted value reaches a full count, it returns to 0 again and repeats the counting operation. For example, it consists of 10 bits and its status output is 0-AB.

An λ9 is output every moment. In this case, the full count value is 1024, so the repetition period of the old enemy is 1024 times the clock signal period.

Data select 2 decodes 0-Δ days to the state output of pinary counter 1, 9 to λo-, and sequentially designates one of the 1024 output lines in a predetermined force 1q order. Therefore,
1024 output lines are address 0, address 1, -1111-1
Addresses 023 are selected one after another, and this process is repeated. Random-j' access memory (1 AM) 3 BA, 102
Information of "1" or "0" is written to each of the four address lines, and the digital values obtained by arranging this information in series from address 0 to address 1023 are the digital information to be converted. The output sofa 4 temporarily stores the output of the memory 3, amplifies it, and turns on and off the output switches 1 to 5. This transistor 5 drives a light emitting diode 6 to emit light, and this light is transmitted to a remote location by an optical fiber. The output of the phototransistor 8 provided at the other end of the optical fiber is integrated by the JIJ branch circuit 9 and output as a complete DC signal or a pulsating current having a multiple waveform.

CPIJ (shown in the figure) creates and outputs D-Δ conversion size data, and also controls the 1)-Δ conversion device of the present invention. Digital ti' to convert? +u is one 7
The bit position is specified by the address data, and the RAM
The write data specifies the digital information to be placed in the pinotoy 1 position, the data selector 2 specifies the specified address, and the stored contents of the 1h specified address are rewritten according to the write h7-ta. This loading process is performed at the timing of the M write timing signal to the 1st line. Reading of the RAM memory contents is executed according to the RAM memory 1 timing signal synchronized with the clock.
This read timing signal is transmitted to the CPU and controlled so that it does not coincide with the write timing signal.

Because of this configuration, even if the contents of RAM are not replaced, reading from RAM is rllllllN
This is done in a continuous manner, and an analog message is output continuously. In addition, since it is transmitted via optical fiber and then converted into final analog information, it is not affected by electrical or magnetic noise during transmission, and the accuracy of the converted analog information is determined by integration. Since it depends on the power supply voltage of the circuit 9 and is not affected by the power supply voltage on the transmitting side, the signal-to-noise frequency, etc., analog information with high precision and a high S/N ratio can be obtained. Furthermore, it is possible to easily produce high resolution products.
Not only a predetermined DC signal but also, for example, a sine wave, a sawtooth wave, a ramp wave, or other irregular waveform information can be converted into output. By the way, in the above example, RAM
There are 2 to the 1024th power of combinations that the serialized signal output from step 3 can take between all bits "0" and all bits "1". When converted, there are 1024 voltage levels. Further, according to the present invention, unlike the conventional resistance type D-A converter, a precision resistor is not required, so it can be manufactured much more cheaply, compactly and lightweight, and the transmitter and receiver are connected electrically by optical fiber. Since it is insulated, it is easy to design power supply systems and has a wide range of applications.

Next, a multi-channel DA converter will be explained. FIG. 2 shows a four-channel embodiment. According to this embodiment, four pieces of digital information can be written, transmitted, and converted into analog information at the same time.

RAM3Δ stores digital information N3+ of 4 pins 1- for each address from address O to address 1023.

n2. +13,1i4) 4. I city. Kono 1st Via 1 +31 series O? 1024 Pino 1 from fi address to address 1023 creates another digital information of the 1st channel, the series of C12 2nd hit L3 of the same work, the series of 3rd pin 1-B], the 4th pin I・134 series constitute the second channel, third channel, ', B 4 channel, 1 bow 6 channel information (-13).・Nerno 1, i+Ti is used for 4 ・5° output Hanofa 4Δ is set up with 1, each channel: 4 Le・2 and Lanau y-area is provided, so that −1・, l・transistor 5Δ, 513. 5C, 5
1), Light-emitting di-key-1 [; △.

6B, 6C, 6D, optical fiber Huff Δ, 714.7C.

7D, Bototransistor 8A, 81+, 8(:,,
81].

and integrating circuits 9Δ, 9B, 9C,! I11 is provided for each channel. In addition, the RAM data relocation principle is implemented in common for each channel.According to this embodiment, the configuration of the multi-channel IJ-Δ converter is In particular, the transmission (r:i-1!!I+) can be made very compact.In addition, the number of channels can be easily increased or decreased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the invention, and FIG. 2 is a block diagram showing another embodiment of the invention. 1 - Binary counter 2 - Data selector 3 - Random access memory 4 - Output bath sofa 6 - Light emitting diode 7 - Optical fiber 9 - Integrating circuit

Claims (1)

[Claims] A highnary count that reads the dl number of clock signals in a predetermined order, a data selector that decodes the status output of the highnary count and repeats address designation in a predetermined order, and a data selector that corresponds to the addresses in the predetermined order. Random access memory that stores a series of decile information and its random "1"
(!) A means for converting Snow's digital information into an optical signal, an optical fiber for transmitting the optical signal, an integrating circuit for flattening the output waveform of the optical fiber, and the contents of the random access memory mentioned above. The digital information to be converted to the rank access memory is converted to the digital information to be converted to the rank access memory. Device.