JPH0114737B2 - - Google Patents

Description

[Detailed description of the invention]

When the sampled values of an analog signal obtained by periodic sampling are converted into a digital signal in the form of PCM words, the analog values combined from unrestricted level values are used in the encoding Due to the limited number of elements, a limited number of amplitude stages can be accommodated. That is, so-called quantization is performed. This type of quantization results in quantization noise. To ensure that this quantization noise is not perceived as noise, the ratio between the analog signal amplitude and the noise level caused by quantization must be kept at a predetermined value. Sufficient signal-to-noise ratio may be obtained using 4000 amplitude stages evenly divided over the entire amplitude range of the analog signal. In this case, a digital signal with at least 12 code signal elements must be transmitted. Moreover, if the quantization steps are uniformly distributed in this way, the signal-to-noise ratio will become excessively large in the region of large analog value amplitudes. Therefore, during the encoding process, a companding, ie a conversion from a linear code representation to a non-linear code representation, takes place in such a way that the signal-to-noise ratio is constant over the entire amplitude range. A precisely constant signal-to-noise ratio is obtained by the logarithmic companding characteristic. In practice, this is carried out in accordance with companding properties which can be easily realized according to the so-called A-law or μ-law.
When using the A law, it is done according to a characteristic curve that is combined from 13 straight line segments,
According to μ law, there are 15 segments. The slopes of the straight line segments of these characteristic curves decrease by half in adjacent segments in both the positive and negative regions. Furthermore, each segment is divided into 16 equally sized quantization intervals, and the height of each interval is doubled in each adjacent segment. This regularity is not used in the first segment. Based on A-law, the first segment consists of 32 positive and negative quantization intervals, each having two values of linearly encoded information. In μ-law, the first segment similarly consists of 15 positive and negative quantization intervals, each with two values of the linearly encoded signal, and one positive and negative quantization interval, each with only one value of the linearly encoded signal. and a negative quantization interval. Therefore, according to the A law, 8192 steps in the linear code representation are equivalent to 8192 steps in the companded representation.
Compatible with 256 steps. According to the μ-law, the ratio of linear encoding steps to non-linear encoding steps is
The ratio is 16,318 to 256. When performing the above correspondence of linearly encoded signal values to nonlinearly encoded signal values using a storage device, possible
To control 256 non-linearly encoded signal values,
Based on A law, the address of 2 ¹³ is also μ
Based on the law, 2 ¹⁴ addresses are required.
That is, because of the 8 bits required for non-linear encoding, the former requires a storage capacity of 2 ¹⁶ bits and the latter 2 ¹⁷ bits, or in other words,
This means that a storage capacity of 64kBit to 128kBit is required. If a mass-produced integrated semiconductor memory device of suitable size is used (in this case a semiconductor memory device with a storage capacity of 512 memory locations for 8 bits each, i.e. 4 kBit is used), Between 16 and 32 such storage devices with 20 connection terminals each are required. However, in reality, it is inconvenient to arrange such a large number of terminals throughout. SUMMARY OF THE INVENTION It is therefore an object of the invention to provide a method for converting a linearly coded digital signal into a non-linearly coded digital signal with low outlays for the conversion. According to the present invention, this problem is solved by using two storage devices to correspond the signal values encoded in two encoding formats, and the first storage device of these storage devices has the positive and negative values stored in each storage device. As a control address, the relatively high value bits of the linearly encoded signal value following the highest value bit determining the polarity of the linearly encoded signal value are at least as many as are necessary to characterize the segment of the characteristic curve to which the signal value in question belongs. supply, in which case digital words are stored in the memory cells of this first storage device, the three highest value bits of these digital words being associated with a corresponding non-linear sign representing the segment of the characteristic curve in which this information value lies. The digital word is the highest value bit following the bit indicating the positive or negative polarity of the digital word, and the remaining bits of the digital word represent a partial address for controlling the second storage device and the second storage device. The device is supplied with the remaining bits of the respective linearly encoded signal value, excluding the lowest value bit, which remains unconsidered during the conversion, as a relatively low-value control address part, with this second The memory cells of the storage device store bit combinations characterizing the corresponding steps of the segments of the characteristic curve to which the non-linearly encoded signal values belong, and the bit combinations that characterize the corresponding steps of the segments of the characteristic curve to which the non-linearly encoded signal values belong are stored, and are used to The highest value bit of the encoded signal value, the three previously mentioned highest value bits whose value is read out from the first storage device as the next bit, and the second storage device as the lowest value bit. The solution is to use a bit combination read from Next, the present invention will be explained in detail using the drawings.

[Table] As mentioned above, Table 1 shows the logical correspondence between a digital signal that is linearly encoded using 13 bits and a digital signal that is correspondingly non-linearly encoded using 8 bits. , and the relationships shown in the table then follow the selected A-law. The table only shows relationships in the positive region of the underlying 13-fold line characteristics. For the negative region of the characteristic,
The same representation applies, except that the highest value bit ²¹³ in the linear encoding to the highest value bit ²⁷ in the non-linear representation has the binary value O instead of the binary value L. The numbers 0 to 7 entered between the two codeword groups indicate that the corresponding line corresponds to segments 0 to 7 of the characteristic curve half, with both characteristic curve halves segments 0 and 7 corresponding to each other. 1 each have the same slope, so that the complete characteristic curve actually consists of 13 straight lines. As shown by the non-linear signage in the right half of the table, all segments 0 to 7 contain four bits 2 ^{0 to 7} .
2 ³ 16 different possible combinations a, b, c,
d, it is divided into 16 equally sized steps. Highest value bit 2 ⁷ indicating positive/negative polarity
The latter three bits ²⁶ to ²⁴ take the combination OOO to LLL from segment 0 to segment 7,
Therefore, it indicates a segment area. From the logical correspondence between the two types of encoding, especially the encoding corresponding to segment 0, the binary value of the lowest value bit ²⁰ of linear encoding has an influence on the correspondence to codewords that are non-linearly encoded. It can be seen that there is no force and therefore a step in the non-linear encoding has at least two linearly encoded signal values. According to a partial feature of the invention, this lowest value bit is
Leave it as is without consideration when converting from one type of encoding to another. 2 more
From a comparison of the two codebooks, it can be seen that, corresponding to the possible bit combinations in segment 0 and segment 1, 16 and 2 linear steps respectively correspond to 16 steps in non-linear encoding. Furthermore, segment 2 to segment 7
It can be seen that the quantization intervals gradually become twice as large. i.e. segment 2
In each of the 16 non-linearly encoded codewords,
Four linearly encoded codewords differing in the possible combinations of bits ²⁰ and ²¹ correspond to 16 non-linearly encoded codewords in segment 3, respectively with bits ²⁰ to ²² . There are eight linearly encoded codewords that vary depending on the possible combinations of . In this way, segment 7
In , each of the 16 nonlinearized codewords corresponds to a possible combination of bits ²⁰ to ²⁶ .
It supports 128 linearly encoded codewords. The device shown in the figure for implementing the method of the invention has two storage devices K1 and K2, in which a permanent memory (ROM) or a programmable permanent memory (PROM) is used. If it is based on the μ law, it is formed using 14 bits ²⁰ to ²¹² and V, and if it is based on the A law, it is formed by 13 bits ²⁰ to ²¹¹ and V. Linear encoded signal to be converted
From the SDL, following the highest value bit V that determines the positive or negative polarity, the number of relatively high value bits required to characterize the segment of the characteristic curve to which the signal value in question belongs is determined in order to determine the control region. Provided as a control address. Based on the A-law used for the following explanation, it is bits ²¹¹ to ²⁵ , as shown in the codebook used for linear encoding in Table 1. The reason is that each segment has bits ²¹ to ²¹⁰ with different weights, except for segments 0 and 1, which specify the step limits in each individual segment only when all these bits are associated. This is because it is possible to determine which position the bits a, b, c, and d will occupy. For conversion according to A-law, the first fixed storage device K1 therefore has 2 ⁷ =128 storage cells. Furthermore, when converting using the μ law, there are 2 ⁸ = 256 memory cells. Digital words are stored in these storage cells in a corresponding manner. The three highest value bits of the digital word are followed by bits indicating positive and negative polarity and, as already mentioned, are associated with a corresponding non-linearly encoded information value representing the segment of the characteristic curve in which this information value lies. This is the highest value bit. The remaining bits of the digital word above, in this case 5 bits, are
A partial address is formed for controlling the second storage device K2. The above-mentioned storage cells of the first programmable storage device thus each provide storage locations for 8 bits, so that the total storage capacity based on A-law is 1024 bits. The partial address read from the first programmable storage device K1 for the second programmable storage device K2 represents a relatively high value portion of the control address of this storage device. As a relatively low value part of the control address of this storage device, the lowest value bit of the linearly encoded signal is excluded.
Therefore, bits ²¹ to ²⁴ are used in this case. By means of these control addresses with 9 bits the second programmable memory K2
can control 512 storage cells. In these storage cells, bit combinations are stored which characterize the corresponding step of the segment of the characteristic curve to which the individual non-linearly coded signal value is assigned. As explained in connection with Table 1,
These bit combinations have 4 bits and are thereby used in the second programmable memory K2.
The storage capacity of is 512.4 = 2048 bits. As explained at the beginning, for code conversion, A
The device for implementing the method of the invention requires only 3072 bits of storage space compared to the case of using only a programmable storage device, which in the case of the law would have to have a storage capacity of 64 KBits. I don't. As shown in the figure, in order to form a non-linearly encoded digital signal, the bits indicating positive and negative polarities of the linearly encoded signal are directly used as the highest value bits, that is, the bits indicating positive and negative polarities, and The above three bits ²⁶ to ²⁴ read from one programmable memory K1 are used as bits of the subsequent value, ie as bits representing the segment address, and are then read from the second programmable memory K2. 4 bits read
²³ to ²⁰ are used as the lowest value bits. The lowest value bit ²⁰ of the linearly encoded digital signal remains unconsidered for the reasons already explained. Finally, the bits ²¹¹ to ²⁵ of the linearly encoded digital signal are used as control addresses, and the second storage device K
The present invention will be summarized once again in order to clarify what kind of partial address is output by the first storage device K1 for the control of the second storage device K1. Table 1 contrasts the relationship between a linearly encoded digital signal with 12 bits ²⁰ to ²¹¹ and a polarity bit V and a correspondingly non-linearly encoded digital signal with a multi-linear characteristic curve. The latter contains in each case seven bits ²⁰ to ²⁶ and one polarity bit. Only digital signals with positive polarity corresponding to the polarity bit L are considered in the table. As the right side of Table 1 shows, the non-linearly encoded digital signal encoded corresponding to the positive half of the characteristic curve consists of eight segments 0, of which bits ²⁴ to ²⁶ form a segment address. It belongs to any one of 7 to 7. Within these segments, 16 different values are possible, represented by bits ²⁰ to ²³ . As a comparison of the table on the right and the table on the left shows, the position of the first bit with binary value L in the linearly encoded digital signal that occurs after the polarity bit is
Determining which segment the corresponding non-linearly encoded digital signal corresponds to. That is, for example, a linearly encoded digital signal with a binary value L and the first bit in bit position ²⁸ will have a segment address
It corresponds to a non-linearly encoded digital signal belonging to segment 4, which is LOO. A comparison of the two table parts determines which segment of the non-linearly encoded digital signal it corresponds to in the indicated relationship between linearly encoded and non-linearly encoded digital signal. It also shows that bits ²⁵ to ²¹¹ must be associated when doing so. This is therefore why in the device of FIG. 1 bits ²⁵ to ²¹¹ (bits ²¹² shown in dashed lines correspond to the other code representations) are supplied to the first storage device K1. . Furthermore, from the comparison in the table, using the association of bits ²⁵ to ²¹¹ of the linearly encoded digital signal,
As already mentioned, it is also clear that the addresses of the segments 0 to 7 in question, which are constituents of the non-linearly coded code word, can also be determined. The storage device K1 therefore stores bits ²⁴ to ²⁶ representing the segment address of the non-linearly encoded digital signal.
can be sent directly. From the comparison of the two code tables in Table 1, it can be seen that the 16 x 2 linear steps in segments 0 and 1 each correspond to 16 steps in the non-linear code representation, and that the quantization gradually increases from segment 2 to segment 7. It is also clear that each division grows by a factor of 2. The 4096 linear encoded code combinations with the same overall polarity are contrasted with the 128 code combinations of the same polarity in the non-linear display. As already mentioned, the correspondence to the eight segments of the non-linearly encoded code word is provided by associating bits ²⁵ to ²¹¹ of the linearly encoded digital signal with the control of the memory K1. In order to be able to take into account a total of 4096 different combinations of linearly encoded digital signals, the memory K2 must have 512 storage locations that can be different (4096:8). Since bits ²¹ to ²⁴ of the linearly coded code word are fed directly to the memory K2, this memory additionally requires another five control bits fed from the memory K1, so that this 2 ⁹ =512 locations can be addressed in memory.

[Brief explanation of drawings]

The figure shows two storage devices and the corresponding control and output line arrangement used to implement the conversion method of the invention. SDL...linear encoded digital signal, SDK...
Non-linear encoded digital signals, K1, K2... storage device.

Claims (1)

[Scope of Claims] 1. A method for converting a linearly encoded digital signal into a non-linearly encoded digital signal according to a multi-line characteristic according to the A-law or the μ-law, comprising: a signal encoded in two encoding formats; value SDL,
SDK correspondence is performed using two storage devices K1 and K2, and the first storage device K of the storage devices is
1, in each case a comparison of as many linearly encoded signal values SDL following the highest value bit V determining the positive or negative polarity and at least as many as are necessary to characterize the segment of the characteristic curve to which the signal value in question belongs. The bits with the highest value (2 ¹² to 2 ⁵ to 2 ¹¹ to 2 ⁵ ) are supplied as a control address, and a digital word is stored in the storage cells of this first storage device K1, and the bits of this digital word are The three highest value bits (A8 to A6) are the highest value bits (2 ⁶ to ²⁴ ), and the remaining bits (A5 to A1) of the digital word are partial addresses (A8 to A1) for the control of the second storage device K2.
A4), and the control address part (A3 to A0) with a relatively low value is stored in the second storage device.
as the respective linearly encoded signal value (SDL)
The remaining bits (from 2 ^{4 to}
2 ¹ ) is supplied, then this second storage device K2
storage cells contain non-linearly encoded signal values (SDK)
The bit combinations ²⁰ to ²³ characterizing the corresponding step of the segment of the characteristic curve to which
Linear encoded signal values (SDL) to form
The highest value bit V and the three highest value bits ( ^A8 to A6) read from the first storage device as the next bits (26 to ²⁴ ) in value.
and a bit combination read from the second storage device K2 as the lowest value bits (2 ³ to 2 ⁰ ).