JPS5961948A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPS5961948A JPS5961948A JP57173770A JP17377082A JPS5961948A JP S5961948 A JPS5961948 A JP S5961948A JP 57173770 A JP57173770 A JP 57173770A JP 17377082 A JP17377082 A JP 17377082A JP S5961948 A JPS5961948 A JP S5961948A
- Authority
- JP
- Japan
- Prior art keywords
- insulating frame
- copper
- molybdenum
- thermal conductive
- base material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
- H01L23/4924—Bases or plates or solder therefor characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体パッケージの改良に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in semiconductor packages.
近時、情報処理装置の高性能化、高速度化に伴い、それ
を構成する半導体素子も高密度、高築積化が急激に進ん
でいる。そのため半導体素子の単位面積、中位体稍あた
りの発熱量が増大し、半導体素子を正常に、かつ安定に
作動さセるためにはその熱をいかに効率的に除去するか
が課独となっている。BACKGROUND ART In recent years, as information processing devices have become more sophisticated and faster, the semiconductor elements that make up the devices have also rapidly become denser and more stacked. As a result, the amount of heat generated per unit area and intermediate size of semiconductor devices increases, and in order for semiconductor devices to operate normally and stably, it becomes a challenge to remove this heat efficiently. ing.
従来、半導体素子の発生する熱の除去方法としては、半
導体素子を、銅（’ Ｃ１１）等の良熱伝導性材料から
成る基体にセラミック等の絶縁月料から成る枠体を取着
した構造の半導体パッケージに収納し、半導体素子から
発生される熱を熱伝導性基体に吸収させるとともに該吸
収した熱を大気中に放出することによりおこなっている
。Conventionally, as a method for removing heat generated by a semiconductor element, the semiconductor element has a structure in which a frame made of an insulating material such as ceramic is attached to a base made of a material with good thermal conductivity such as copper ('C11). This is accomplished by housing the semiconductor element in a semiconductor package, allowing a thermally conductive substrate to absorb the heat generated by the semiconductor element, and releasing the absorbed heat into the atmosphere.
しかしながら、この従来の半導体パッケージは熱伝導性
基体と絶縁性枠体との熱膨張係数の差に起因して、半導
体パッケージに半導体素子の熱が印加された場合、熱伝
導性基体が絶縁性枠体より大きく膨張し、その結果、該
熱膨張差に伴う応力によって絶縁性枠体にクラックや欠
は等を発生してしまうという欠点を有していた。そのた
め従来の半導体パッケージでは収納している半導体素子
の気密が容易に破れ、半導体素子を長期間にわたり正常
にかつ安定に作動させるこができなかった。However, in this conventional semiconductor package, due to the difference in coefficient of thermal expansion between the thermally conductive base and the insulating frame, when the heat of the semiconductor element is applied to the semiconductor package, the thermally conductive base changes to the insulating frame. This has the disadvantage that the insulating frame expands more than the body, and as a result, cracks and chips occur in the insulating frame due to stress caused by the difference in thermal expansion. Therefore, in conventional semiconductor packages, the airtightness of the semiconductor elements housed therein is easily broken, making it impossible for the semiconductor elements to operate normally and stably for a long period of time.
本発明は」二記欠点に鑑み案出されたもので、その目的
は半導体素子から発生される熱を良好に吸収除去すると
ともに絶縁性枠体の熱膨張差に起因する応力によるクラ
ンクや欠＋−１等の発生を皆無として収納する半７η体
素子を長期間にわたり正常に、かつ安定に作動さ−ｌる
ことのできる半導体ハノケージを提供するごとにある。The present invention was devised in view of the above two drawbacks, and its purpose is to effectively absorb and remove heat generated from semiconductor elements, and to prevent cracks and cracks caused by stress caused by the difference in thermal expansion of the insulating frame. It is an object of the present invention to provide a semiconductor cell cage that can operate normally and stably for a long period of time in which a semi-7η element is housed without any occurrence of -1 or the like.
本発明は；：ｐＨ伝導性基体上に絶縁性枠体を取着して
成る′−１θＩ体パッケージにおいて、前記ｆ：ハ伝導
性基体を銅５乃至３ｏ ｗ ｔ％とモリブデン７０乃至
９５ｗｔ％を有する合金により形成したことを特徴とす
るものである。The present invention provides a '-1θI body package comprising an insulating frame attached to a pH conductive substrate, wherein the f: conductive substrate contains 5 to 3 wt% of copper and 70 to 95 wt% of molybdenum. The invention is characterized in that it is made of an alloy having the following properties.
以下９本発明を添付図面に示す実施例に基づき詳細に説
明する。Hereinafter, the present invention will be described in detail based on embodiments shown in the accompanying drawings.
１は熱伝導性基体であり、その」二面中央部に半導体素
子３が、また外周部に前記半導体素子３を囲繞するよう
に絶縁性枠体２がそれぞれ樹脂、半田等の接着材を介し
取着されている。Reference numeral 1 denotes a thermally conductive substrate, with a semiconductor element 3 at the center of its two sides, and an insulating frame 2 surrounding the semiconductor element 3 at the outer periphery via an adhesive such as resin or solder. It is attached.
前記熱伝導性基体１は銅−モリブデン合金から成り、そ
の熱膨張係数は５．５乃至９．０Ｘ１０／Ｃの範囲であ
る。The thermally conductive substrate 1 is made of a copper-molybdenum alloy, and its coefficient of thermal expansion is in the range of 5.5 to 9.0×10/C.
また、前記絶縁性枠体２は例えばアルミナ（Δ１２０３
）等のセラミックにより１５成され、その！“ハ膨張係
数は６．０乃至７． ５ Ｘ １０／’Ｃの範囲である
。Further, the insulating frame 2 is made of, for example, alumina (Δ1203
) is made of ceramics such as 15, and the! "Ha expansion coefficient ranges from 6.0 to 7.5 x 10/'C.
熱伝導性基体１の合金組成は絶縁イ（１枠体２の月１’
１に応してその熱膨張係数に近似する熱膨張係数となる
ように決定されるべきである。これにより、半導体素子
３の熱が印加されても熱伝導性基体１と絶縁性枠体２と
の接合部には熱膨張係数の差による応力の発生が解消さ
れる。The alloy composition of the thermally conductive substrate 1 is insulating
The coefficient of thermal expansion should be determined so as to approximate the coefficient of thermal expansion corresponding to 1. As a result, even when heat from the semiconductor element 3 is applied, stress generated at the joint between the thermally conductive base 1 and the insulating frame 2 due to the difference in coefficient of thermal expansion is eliminated.
前記熱伝導性基体１は高熱伝導率を有しており。The thermally conductive substrate 1 has high thermal conductivity.
半導体素子３から発生される熱を直接伝導吸収するとと
もに該吸収した熱を大気中に放出する作用を為す。It functions to directly conduct and absorb the heat generated from the semiconductor element 3 and to release the absorbed heat into the atmosphere.
前記熱伝導性基体１に用いる銅−モリブデン合金の組成
ば銅５乃至３０ｗｔ％とモリシ゛デン７０乃至９５ｗｔ
％を有するように設定され、モリブデン粉末（約Ｉ Ｏ
／ｌＡ）を１０００Ｋｇ／ｃＩ♂の圧力で加圧成形し、
これを還元雰囲気中、約１５００’ＣのｌＡ？を度で焼
成するごとによって得た多孔質のモリブデン焼結体ニ、
約１１００’Ｃの温度で加；ｉｊ４熔融させた＃ｌａ＋
を前記モリブデン焼結体の多孔部分に毛管現象を利用し
て含浸させることによって形成される。The composition of the copper-molybdenum alloy used for the thermally conductive substrate 1 is 5 to 30 wt% copper and 70 to 95 wt% molybdenum.
Molybdenum powder (approximately I O
/lA) at a pressure of 1000Kg/cI♂,
This is carried out in a reducing atmosphere at about 1500'C lA? A porous molybdenum sintered body obtained by firing the
heated at a temperature of about 1100'C; ij4 melted #la+
It is formed by impregnating the porous portion of the molybdenum sintered body using capillary action.
前記ｉ：Ｊ５伝導性）Ｈ５体ＩのＦ面外周部に取着され
ている絶縁性枠体２の内部にはモリブデン（Ｍｏ）、タ
ングステン（Ｗ）等の金属から成る導電層４が形成され
ており、該導電層４は半導体素子３の電極を外部り−１
０１１，１了５に接続する作用を成し、その一端に外部
り−１” ＋／ｊ＋Ｊ Ｊ’ ＋１が、また他端に半導
体素子３の電極に接続されたワイヤ６が取着されている
。A conductive layer 4 made of a metal such as molybdenum (Mo) or tungsten (W) is formed inside the insulating frame 2 attached to the outer periphery of the F-plane of the H5 body I. The conductive layer 4 connects the electrodes of the semiconductor element 3 to the outside -1.
A wire 6 is attached to one end of the wire, and a wire 6 connected to the electrode of the semiconductor element 3 is attached to the other end. .
また、前記絶縁性枠体２の１部には盟休７がガラス、樹
脂等の接着材を介し取着されており、これにより半導体
パッケージの内部が完全に気密に封１にされる。Further, a seal 7 is attached to a portion of the insulating frame 2 through an adhesive such as glass or resin, so that the inside of the semiconductor package is completely hermetically sealed 1.
か＜Ｌ’Ｕ、本発明の半導体パッケージによれば。or<L'U, according to the semiconductor package of the present invention.
内部に収納した半導体素子を作動させた場合、該半導体
素子から発生される熱は熱伝導性基体に吸収されるとと
もに大気中に放出され、半導体幸子自１を１１１１ ／
？！ｔとして熱破壊させたり、特性に熱変化を与え誤動
作さ−ｌたりずろことがなく、また同時に、！クシ伝導
性基体と絶縁性枠体との熱膨張係数が近似しているため
両者の熱膨張差に起因する応力によって絶縁性枠体にク
ラックや欠は等を発生ずることもなく、半導体素子の気
密を長期間にわたり保持することができる。これによっ
て半導体素子を長期間にわたり正常にかつ安定に作動さ
せることがｉ′ＩＪ能となる。 ４次に本発明の作用効
果を実験例に基づき説明する実施例
図に示す半導体パッケージにおいて熱伝導性基体として
Ｆ表に示す組成のものを、また絶ｉｔ性枠体としてアル
ミナセラミック（熱膨張係数７． （ｌ Ｘ １ （
１−’／゛Ｃ）を用いたものをそれぞれ２０個〆Ｉ”
（Ｉｎｎ ６部次に内部に収納した半導体素子を常温か
ら１５０ ′ｃに冒険ｌｌ！！ｔさせ、ごれを１０ザイ
クルくり返した（々、゛１１導体パッケージの気密性を
ヘリウムリークデテクターにより測定し、気密が破れた
ものの数をｌｉｄべた。When the semiconductor element housed inside is operated, the heat generated by the semiconductor element is absorbed by the thermally conductive substrate and released into the atmosphere, causing the semiconductor element to become 1111 /
? ! At the same time, there will be no thermal damage or malfunction due to thermal changes in the characteristics, and at the same time! Since the thermal expansion coefficients of the comb conductive base and the insulating frame are similar, the stress caused by the difference in thermal expansion between the two will not cause cracks or chips in the insulating frame, and the semiconductor device Airtightness can be maintained for a long period of time. This makes it possible to operate the semiconductor device normally and stably for a long period of time. 4 Next, the effects of the present invention will be explained based on experimental examples.In the semiconductor package shown in the example diagram, the thermally conductive substrate was made of a composition shown in Table F, and the insulating frame was made of alumina ceramic (thermal expansion coefficient). 7. (l X 1 (
20 pieces each using 1-'/゛C)
(Inn 6th section) Next, the semiconductor device housed inside was exposed to temperature from room temperature to 150'C, and dirt was repeated for 10 cycles. , and counted the number of cases where the airtight was broken.
結泉を表−１に示す。The results are shown in Table-1.
本発明によれば上記実験結果からも判るように半導体ハ
ノケージの熱伝導性基体を特定の銅−モリブデン合金で
形成したことにより、 ｔｊｆｖ来の銅から成るものに
比し、その気密性の不良率を８０％以」二から３０％以
下にまで大幅に低減することが可能となり、半導体素子
の気密性が大きく改良される。According to the present invention, as can be seen from the above experimental results, by forming the thermally conductive base of the semiconductor hino cage from a specific copper-molybdenum alloy, the defective rate of its airtightness is lower than that of the conventional copper cage. This makes it possible to significantly reduce the amount of heat by 80% or more to 30% or less, and the airtightness of the semiconductor device is greatly improved.
また１本発明の半導体パッケージにおける熱伝導性基体
は含有する銅の量が５ｗｔ％以下では熱伝導率が小さく
、半導体素子から発生される熱を良好に吸収除去できず
、また５ｗｔ％以下、３０ｗｔ％以−ヒでは熱膨張係数
が絶縁性枠体のものと大きく相違し、半導体素子の気密
を保持することができない。Furthermore, if the amount of copper contained in the thermally conductive substrate in the semiconductor package of the present invention is less than 5 wt%, the thermal conductivity is low and the heat generated from the semiconductor element cannot be well absorbed and removed. % or more, the coefficient of thermal expansion is greatly different from that of the insulating frame, and the airtightness of the semiconductor element cannot be maintained.
従って、熱伝導性基体の銅の含有量ば５乃至３０ｗｔ％
の範囲に規定される。Therefore, the copper content of the thermally conductive substrate is 5 to 30 wt%.
stipulated within the range of
本発明は上述の実施例、実験例に限定されるものでなく
２例えば熱伝導性基体の銅−モリブデン合金に第三成分
を添加すること等２本発明の要旨を逸脱しない範囲であ
れば種々の変更は１１佳である。The present invention is not limited to the above-mentioned embodiments and experimental examples, but may be modified in various ways without departing from the gist of the present invention, such as adding a third component to the copper-molybdenum alloy of the thermally conductive substrate. The number of changes is 11.
図は本発明の半導体パソゲージの一実施例を示す１１ノ
ｉ而図である。
１：！・ハ伝シｕ性基体 ２：絶縁性枠体特許用１
頭人
京都セラミック株式会社
代表者 稲盛和夫The figure is an 11th diagram showing an embodiment of the semiconductor path gauge of the present invention. 1:!・Harden-resistant substrate 2: Insulating frame patent use 1
Kazuo Inamori, Representative of Tojin Kyoto Ceramic Co., Ltd.
Claims (1)
ケージにおいて、前記熱伝導性基体を銅５乃至３０ Ｗ
ｔ％とモリブデン７０乃至９５ｗｔ％とを有する合金
により形成したごとを特徴とする半導体パッケージ。In a semiconductor package comprising an insulating frame attached to a thermally conductive substrate, the thermally conductive substrate is made of copper of 5 to 30 W.
A semiconductor package characterized in that it is formed of an alloy having 70 to 95 wt% of molybdenum and 70 to 95 wt% of molybdenum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57173770A JPS5961948A (en) | 1982-09-30 | 1982-09-30 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57173770A JPS5961948A (en) | 1982-09-30 | 1982-09-30 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5961948A true JPS5961948A (en) | 1984-04-09 |
Family
ID=15966820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57173770A Pending JPS5961948A (en) | 1982-09-30 | 1982-09-30 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5961948A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0420244U (en) * | 1990-06-07 | 1992-02-20 | ||
| US7083759B2 (en) * | 2000-01-26 | 2006-08-01 | A.L.M.T. Corp. | Method of producing a heat dissipation substrate of molybdenum powder impregnated with copper with rolling in primary and secondary directions |
-
1982
- 1982-09-30 JP JP57173770A patent/JPS5961948A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0420244U (en) * | 1990-06-07 | 1992-02-20 | ||
| US7083759B2 (en) * | 2000-01-26 | 2006-08-01 | A.L.M.T. Corp. | Method of producing a heat dissipation substrate of molybdenum powder impregnated with copper with rolling in primary and secondary directions |
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