JPS5961634U - Phase lock droop circuit - Google Patents

Phase lock droop circuit

Info

Publication number
JPS5961634U
JPS5961634U JP15580282U JP15580282U JPS5961634U JP S5961634 U JPS5961634 U JP S5961634U JP 15580282 U JP15580282 U JP 15580282U JP 15580282 U JP15580282 U JP 15580282U JP S5961634 U JPS5961634 U JP S5961634U
Authority
JP
Japan
Prior art keywords
frequency dividing
phase
locked loop
phase lock
droop circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15580282U
Other languages
Japanese (ja)
Inventor
登 荻野
裕三 佐藤
Original Assignee
八木アンテナ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 八木アンテナ株式会社 filed Critical 八木アンテナ株式会社
Priority to JP15580282U priority Critical patent/JPS5961634U/en
Publication of JPS5961634U publication Critical patent/JPS5961634U/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のフェーズロックドループ回路の構成図、
第2図はこの考案の一実施例に係るフェーズロックドル
ープ回路の構成図である。 21・・・電源電圧端子、22・・・分周用IC,25
・・・PLL用IC,2g・・・コンデンサ、30・・
・ツェナー・ダイオード、33・・・水晶振動子。
Figure 1 is a configuration diagram of a conventional phase-locked loop circuit.
FIG. 2 is a block diagram of a phase-locked loop circuit according to an embodiment of this invention. 21... Power supply voltage terminal, 22... Frequency division IC, 25
... PLL IC, 2g... Capacitor, 30...
・Zener diode, 33...crystal oscillator.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 分周用IC及びこの分周用ICの出力を受けて動作する
フェーズロックドループICを有する回路において、前
記分周用ICと前記フェーズロック゛  ドループ用I
Cとを直列接続し、電源電圧を前記両ICに分割して印
加することにより、前記分周用ICの動作電流の一部で
前記フェーズロックドループ用ICを動作させることを
特徴とするフェーズロックドループ回路。
In a circuit including a frequency dividing IC and a phase-locked loop IC that operates in response to an output of the frequency dividing IC, the frequency dividing IC and the phase-locked loop IC operate in response to an output of the frequency dividing IC.
The phase-locked loop is characterized in that the phase-locked loop IC is operated with a part of the operating current of the frequency dividing IC by connecting the two ICs in series and applying the power supply voltage to both ICs in a divided manner. droop circuit.
JP15580282U 1982-10-15 1982-10-15 Phase lock droop circuit Pending JPS5961634U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15580282U JPS5961634U (en) 1982-10-15 1982-10-15 Phase lock droop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15580282U JPS5961634U (en) 1982-10-15 1982-10-15 Phase lock droop circuit

Publications (1)

Publication Number Publication Date
JPS5961634U true JPS5961634U (en) 1984-04-23

Family

ID=30343987

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15580282U Pending JPS5961634U (en) 1982-10-15 1982-10-15 Phase lock droop circuit

Country Status (1)

Country Link
JP (1) JPS5961634U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619453U (en) * 1979-07-25 1981-02-20

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619453U (en) * 1979-07-25 1981-02-20

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