JPS5961369A - High speed expanding processing method of image data - Google Patents

Abstract

PURPOSE:To attain quick and efficient processing with a simple constitution, by providing a register between a code analysis section and an expansion processing section, and a memory selecting control section between the expanding processing section and a line memory. CONSTITUTION:A code analysis section 1 analyzes a compression code and sets the result to a register 2. The expansion processing section 3 restores and expands an image to line memories 51-53 selected at a memory selection control section 4 basing on the internal code set to the register 2, and transmits an end signal to the code analysis section 1 of the pre-stage at the point of time of the processing of the internal code. Further, the expansion processing 3 transmits a line updating signal to a memory selection control section 4 with the content of the register 2. The memory selection control section 4 connects two line memories out of the three line memories to the expansion processing section 3 and the remaining one memory is connected to an output circuit. Further, the memory to be connected is rotated with a line updating signal from the expansion processing section 3.

Description

[Detailed Description of the Invention] [Background of the Invention] The data handled by the BA1 Sakaki machine has also expanded from text and numerical information to syllables and images. Image data, by its very nature, has a large amount of data, so it is often subjected to compression processing.

If the compressed data is to be displayed on a display, for example, it is necessary to decompress and restore it at high speed from the viewpoint of a man-machine interface.

A facsimile machine is a well-known device that handles image data. Fax is CCI T
The image data is compressed based on the river width method of the national gap standard based on the T recommendation. Compression encodes runs according to certain rules, but since this compressed code is bit data with a flexible length, it would take a long processing time to decompress it with a general-purpose encoder (byte machine). The load is also large and becomes 7. Therefore, it may be possible to create standby hardware and execute decompression and restoration processing.

The present disclosure relates to a circuit configuration of hardware dedicated to high-speed decompression (M-element processing), which is indispensable due to the above-mentioned background.

[Prior art to the invention]

The decompression process sequentially performs the following processes.

■ Analysis of compressed code ■ Restores a new line based on the above analysis results and the expanded data that has already been decompressed if necessary.

■ Store restored data in memory for the next line.

■ If the compressed data is not finished, continue from ■.

Executing the above processing on a single microprocessor1
In the case of 7, only one of the above items can be executed at a certain point, and processing speed cannot be expected. Also, when assembling with a dry wired system, the manual input of compressed data, the output of the restoration results, and the internal processing are asynchronous. The drawback is that the processing speed is limited to -1tt.

[Purpose of the invention]

The present invention 1ν1 minimizes the influence of input and output as much as possible due to the above-mentioned penalties. This paper attempts to provide a circuit configuration for high-speed processing.

[Structure of the invention]

In a device for decompressing compressed image data such as a facsimile, a first means for analyzing the code of compressed data;
It has a second means for expanding the result of expansion into the line memory based on the analysis result, and a third means for outputting the expanded contents of the line memory, and the first step 11 and the second means. By providing at least 13 line memories (with an e-line register and using the second means and the third means) in between, The third method is to enable 11-column operation and to expand and restore image data in a commercial manner.

[Embodiments of the invention]

Detailed AI + 'It?' while showing the diagram below. Figure 1 shows a schematic block diagram of an embodiment of the present invention.The analysis section 1 checks the pressure code bit by bit and determines the meaning of the code (for example, if it is '000111') White 1) is the internal code, and register 2 is the analysis result.
Set to . After that, 1) 1 is the next i.
When the code is searched and found, if the processing of the previously set internal code has not been completed, the 11th state will be entered, and if it has been completed, the processing will continue.

The decompression processing unit 3 restores and expands the image in the line memories 51, 52, and 53 selected by the memory selection control unit 4 based on the internal code set in the register 2, and at the end of the processing of the internal code, Wandering corner 1
Sends a completion signal to the analysis unit 1. Also, the processing unit 3 selects the memory according to the contents of the register 2.
Send the S4 line update number 1. The memory selection control unit 4 sends two of the three line mesoris to the decompression processing unit 3.
t, and connect the remaining one to the output circuit. Decompression processing unit 3
Change the line [by signal, connect memory 10-
Tate (switch the line that was the target line during the expansion process to the output line, switch the line that has finished output to the line that is to be viewed slightly, and switch the restored line to the line that is to be viewed)
Note that register 2 may also be constructed entirely using an F'IFO memory.

FIG. 2 shows an example of the configuration of the register 2. A J-type flip-flop 21 indicates whether the output of the register is valid or not. Decompression processing section 3fd When this No. 4g is valid, decompression processing is performed according to the internal code, and when the processing is completed, it outputs processing end 41'+3 and clears the previous FF 21. f, T No. 1'? Code Agency 1 from f$i Part 1
Analysis (when the Mh register is empty due to Jl<4M, that is, when the previous 'F3JFF21 is cleared), the corresponding F
1.21 cents, but at the same time NAND gate 24
The output of 5'R is also applied to registers 22 and 23 (
Set, r], code search Kl & fj 4g”
r outputs 0 FIG. 3 shows an example of the memo IJ W selection %il @ll 4. A 2-bit counter 41 (implemented as a ternary counter) is used to generate a line oil change signal from the extension processing section 3, which is used to generate a line oil change signal that is necessary for one line oil/and restoration processing. Take a step forward. Output line λG selection
+% is made by the 2-bit register 42, and 1lfj
H+i The output of the 2-bit counter 41 is input and a value delayed by one cycle is output. Table 1 shows the correspondence between each of the seven selections 1v and the valley line memories 51 to 53.

The operation of FIG. 3 will be explained with reference to Table 1. First, in the system clear state, both the 2-bit counter 41 and the 2-bit register 42 indicate 00'.

Here, the line assembly new signal is given. Tokara/ri41
The count terminal of is triggered and the output DCLI.

0 becomes 01''.

The register 42 has the value "00" of the previous cycle of the color/return 41.
is loaded.

Furthermore, when the line history Mr. title is given, the counter 41
The count up is performed unless the output of
Further, when the output is "11", the load terminal of the counter 41 is triggered, and the human power B and A "0°1'° are loaded. Further, the register 42 is always loaded with the count value of the previous cycle.

The output of the counter 41 is stored in the restoration line memory 11,j
The output of the register 42 indicates the line memory for output.

〔Effect of the invention〕

As described above, in the present invention, the register 2 is provided between the code analysis unit 1 and the arc processing unit 3 to enable parallel, independent, and asynchronous operation of both, and the connection between the extension processing unit 3 and the line memory 5 is also provided. By providing a memory selection control section 4 in between and allocating the line memory to be used, high speed and efficient processing can be achieved with a 17i1 nested configuration.

[Brief explanation of the drawing]

Figure N41 is a block diagram of an embodiment of the present invention, Figure 2 is a detailed block diagram of the register, and Figure 3 is a detailed block diagram of the memory selection system. In the figure, 1 is a code analysis section, 2 is a register, 3 is a decompression processing section, 4 is a memory selection control section, and 5 is a Li line memory.

Claims (1)

[Claims] In a device for decompressing image compressed data such as a facsimile, a first means for analyzing 't-J' of the compressed data, a second means for expanding the decompression result into a line memory based on the analysis result, and a third means for outputting the contents of the line memory that has been expanded, a register is provided between the first means and the second means, and the line memory is used by the second means and the third means. Provide at least three
An image data high-speed decompression processing method in which a stage, a second means, and a third f stages are capable of parallel operation.