JPS5961328A - Frame synchronism system - Google Patents

Abstract

PURPOSE:To discriminate quickly the frame synchronism establishment by inserting a CRC (cyclic redundancy check) code to each frame. CONSTITUTION:A data of a terminal device is multiplexed at a multiplexing section 1, a frame signal is inserted to a frame signal inserting section 3, a CRC code is inserted at a CRC code inserting section 21, it is transmitted via an MODEM, the frame signal is detected from a receiving signl at a frame signal detecting section 6', a control section 22 performs CRC check, and when the signal is not coincident, the frame signal detecting section is reset, and when coincident, the CRC code is eliminated at a CRC code eliminating section 24, the signal is separated multiplexedly at a distribution section 7 and outputted to a terminal device via an interface.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a frame synchronization system, and in particular, in a time division multiplex communication system using fixed length frames, it is possible to establish synchronization without detecting a frame synchronization signal multiple times. The present invention relates to a method in which frame synchronization is determined by checking the frame synchronization signal and subsequent frame data in a fixed table (,'f(,C).

Background of the Technology, Prior Art, and Problems To communicate fixed-length frame data using a time division multiplexer, the transmitting side inserts a frame synchronization signal F between frames to generate an alignment signal, as shown in Figure 1. After confirming that the data can be correctly detected on the receiving side, the data including the frame synchronization signal F is received. In addition, as shown in C in Figure 1, there are control signals, such as those for loop testing, which are inserted into a predetermined area of each frame, and it is checked to ensure that they can be detected correctly on the receiving side. Control according to the lever control signal, for example, a loop test, is executed to prevent erroneous control such as a loop test operation due to a line error.

As shown in FIG.
E-2...I) Each input data from the T E-ru is connected to the corresponding interface Irb-1, Ir.
L-2...■ Send to multiplexer l via loop n,
Time division multiplexing is performed here. That is, the input data from each terminal device is chronologically divided into predetermined time intervals and allocated to predetermined data areas of the first frame, second frame, etc. shown in FIG. 2 is a counter that counts the time during which the frame synchronization signal F and the above input data are positioned in a predetermined area of the frame, and for each count value, data is sent from the multiplexer l to the frame signal inserter 3, and the frame The frame synchronization signal F is inserted between the frames. Further, the counter 2 controls the output time of the control signal C generated from the control signal generation section 4 whose type of control signal to be generated is instructed by the control section 5, and transfers this control signal C to the multiplexing section 1 and and insert it into the designated area in Figure 1. The data sent from the frame signal insertion section 3 is then transmitted to the receiving side via a line via the modem DCE-1.

On the receiving side, a received signal including the frame synchronization signal F, control 1 signal C, etc. is sent to the frame signal detection section 6 and the distribution section 7 via the modem IJ CH-2. Here, when the frame signal detection section 6, which has been placed in an operable state by the control section 8, detects the frame synchronization signal F, this detection signal is sent to the up/down counter 9, where +1 is counted. . Further, this detection signal is sent to the control unit 8, and thereby the frame signal position counter 10
is operated, the time of one frame data area is counted, and a signal based on this counted value resets the frame signal detection section 6 to prepare for the next synchronization signal detection. Then, when the subsequent frame synchronization signal F is detected by the frame signal detection section, the up/down counter 9 counts +1, and conversely, when the frame signal detection section 6 does not detect the frame synchronization signal F. , the up/down counter 9 counts -1. In this way, the up/down counter 9 repeats up/down depending on whether or not the frame synchronization signal F is detected, but when it is received normally and the count value reaches the final value. A control signal based on this is sent to the control section 8, assuming that frame synchronization has been achieved. The control section 8 uses a signal based on the above-mentioned count value to send the data and control signal C obtained by removing the above-mentioned frame synchronization signal F from the signal input to the distribution section 7 to the terminal devices DTB-1' to DTh, -rule'.
and control the distribution section 7 to distribute the control signal to the control signal reception section 11 to output the interface IrL-1', IrL-2' - mark I
The respective terminal devices jlDT via rz-n'
H-1', DTH-2'...I) TE-rule' and corresponding transmitting side terminal device DTB-2,...
The data input from the DTE-R is outputted, and the control signal C is outputted to the control signal receiving section 11. Note that the control signal receiving section 11 increments the up/down counter 12 by 1 when the same control signal is successively and correctly received. However, if the same control signal is not received within a certain period of time after this counting, the up/down counter 12t-1.

And the up/down counter 1 counted sequentially like this
When the count value of 2 reaches the threshold value, that is, when the control signal C is confirmed, this confirmation signal is sent to the control signal receiving section 1.
1, and this control signal receiving section 11 controls the control section 13 to perform control instructed by the control signal, for example, a loop test.

By the way, in the above device, the frame synchronization signal F
It is assumed that synchronization has been established when the synchronization and control signal C are detected a certain number of times. , not only does the amount of hardware become large, but frame synchronization cannot be established quickly.
It also makes it difficult to quickly transmit control signals.

Purpose of the Invention The purpose of the present invention is to detect the frame synchronization signal and check the CI and C of the subsequent data in order to improve the problem that the early establishment of frame synchronization and correct transmission of the control signal C as described above could not be performed quickly and easily. The object of the present invention is to provide a frame synchronization method that solves the above problems.

Structure of the Invention In order to achieve this object, the frame synchronization method of the present invention time-divisions input data and multiplexes it into multiple frames, inserts a frame synchronization signal at a predetermined position in each frame, and synchronizes these data and signals. In a time division multiplex communication system in which synchronization of the frames is established by detecting the frame synchronization signal in the reception 1111, the transmission side inserts CB and C codes into each frame.
A code insertion means is provided, and the received data is Cf (・C
It is characterized in that it is equipped with a C Il, C check means for checking, and when the frame/synchronization signal is detected on the receiving side, the data of the frame to which this synchronization signal belongs is checked by the CI (e) check means. .

Embodiment of the Invention Before describing in detail one embodiment of the present invention, the principle of the present invention will be briefly explained.

As shown in FIG. 3, in the present invention, C)L C(Cyclcc BIethbr
LrLacyChecA) Add the code. Then, on the receiving side, when the frame synchronization signal 1"f: detection 1 is detected, CH and C checks are carried out for the subsequent frame. After a certain period of time, it is compared with the C code and if it matches, the information of that frame It can be determined that all of the information in the frame has been received normally, so each piece of information in that frame, such as Kenzan 1 signal C, has been received normally.Therefore, if this CH and C check is normal and the next frame is When the synchronization signal Fi is detected, it can be determined that the frame has been synchronized, and the probability of error is extremely small.If the CI
(If it is determined that there is an error in the C check, the frame synchronization signal A is restarted from the detection of the signal F. In this way, the frame synchronization signal F is detected and the CH of this frame is detected.
C check passed and next cuff 1/-me synchronization 4f
If it is No. J, the control signal F of this frame can be judged to be reliable and can be used as the control signal C. 4 is a block diagram of this embodiment, in which the same reference numerals as in other figures indicate the same components.

Reference numeral 21 denotes a CI and C signal insertion unit, which inserts CH, C signal between the end of the data area of the frame shown in FIG.
This is to insert a C code. And this CI(,(
? The code is calculated and generated in the C signal insertion section 21.

Reference numeral 22 denotes a control unit which checks the data i CIt C after the frame synchronization signal F is generated, and compares this result with the CR and C codes, and if the results match, sends the control signal C to the distribution unit 7. This is performed once.

Reference numeral 23 denotes a control signal receiving section which is activated by the control signal from the control section 22 and receives the control signal C shown in FIG. 3 from the distribution section 7, thereby controlling the control section 13. be.

24 is a CI (, C code deletion unit), and when a match is found as a result of the above CR and C checks, e of the next frame is
The H and C codes are deleted and the data of this frame is distributed to the distribution unit 7.
It is intended to be communicated to the public.

Reference numeral 61 denotes a frame signal detection unit which has the same function as the frame signal detection unit 6 in FIG. l(, which operates the C code deletion unit 24.

Next, the operation of this embodiment will be explained. 7. (1) Establishment of frame synchronization
) TE-0, DTE-1, . . . 1) When the data becomes available for manual input from the TE-R, the counter 2 operates.

In this state, the data input from the terminal device is divided and multiplexed in time series and allocated to predetermined positions in the data area shown in FIG. A control signal C generated by a signal based on the allocated data and a predetermined count value of the counter 2 and inserted into a predetermined position in the data area shown in FIG. Here, a frame synchronization signal F is added to the beginning, and the signal is sent to the code insertion section 21, and from there, it is further sent to the modem DCE-1.

At this time, C [C?C? Add FLC code. In this way, the signals and data of the first frame are sent to the modem DCFi-1, but the second frame's )1/-m synchronization signal F2 data, control signal C, and C11/C code are also sent to the modem DCFi-1 in the same way.
−1. The same applies to the third and subsequent frames. The signal F and data sent to the modem DCE-1 can be transmitted to the receiving side via a line. On the receiving side, when the frame signal detection section 6' detects the frame synchronization signal F,
Data of the same frame as this signal F, control signals C and C11, (? code) are sent to the control unit 22, where CL(, C check is performed. Then, this result and CL(, C code If a match cannot be found, the frame signal position counter 10 is operated and the frame signal detection unit 6' is reset after a predetermined period of time, and the detection of the frame synchronization signal F is attempted again. When the frame signal detection section 6' detects the next frame synchronization signal, it operates the CB/C code deletion section 24 and distributes the data and signal from which the CI? and C codes have been removed from the modem OCV-2. 7. At this time, the frame In position counter 10 inputs the data and control signal C from which the frame synchronization signal C has been removed.

Then, based on the coincidence signal from the control section 22, 5)
The array R1+7 interfaces the data In, -1',
■Rule 2'...Terminal device υ'LL with I rule'
3-1', DTI sea 2', ... I) TE-rule'
Output to.

(2) Transmission of control signal When the frames are synchronized by the above CRC check, the control section 22 operates the control signal receiving section 23 and causes it to receive the control signal C from the distribution section 7. As a result, the control section 13 is operated, and control based on this control signal, for example, a loop test, is performed. At this time, the control signal C is CR
Since the C check is performed, it can be trusted. Note that the synchronization establishment in (1) above may be performed multiple times. This depends on the bit length of this synchronization signal. The more bits there are, the more synchronizations should be established.

Effects of the Invention According to the present invention, since the establishment of frame synchronization is determined by checking C1 and C, the establishment can be determined quickly.0 Also, since the establishment of synchronization can be determined quickly, as a result, synchronization can be established quickly, and the control signal is transmitted quickly and accurately, and there is no up/down counter to establish synchronization, which was previously required.
Comparison circuits, counters, etc. for control signals can be omitted.

[Brief explanation of drawings]

FIG. 1 is a schematic explanatory diagram of the format of a conventional frame synchronization method, FIG. 2 is a time division multiplexing device thereof, FIG. 3 is a schematic explanatory diagram of the format of a frame synchronization method according to an embodiment of the present invention, and FIG. FIG. 1 is a configuration diagram of an embodiment of the present invention. In the figure, +]'L'g-i,...1) TE-le, 1)
TE-1',...DTE-a' are terminal devices, I
n, -11,, ・I rule, ■rL-1', ・・・
In-rule' is an interface, l is a multiplexing unit, 2 is a counter, 3 is a frame signal insertion unit, 4 is a control signal generation unit, 5.8.13.22 is a control unit, DCE-1, Dcg
-2 is a modem, 6.6' is a frame signal detection section, 7 is a distribution section, 9.12 is an up/down counter, IO is a frame signal position counter, 1L23 is a control signal reception section, 02I is a CB/C code Insertion part, 24 is Cl (, C code deletion part. Patented by M1 person Taka±1rfi Co., Ltd. Patent attorney Akira Yamatani

Claims (1)

[Claims] (1) The input data is time-divided and multiplexed into multiple frames, a frame synchronization signal is inserted at a predetermined position in each frame, and these data and signals are transmitted, and the receiving side detects the frame synchronization signal and performs the above 71. In a time-division multiplex communication system that establishes node synchronization, the transmitting side has a C code that inserts a C code into each frame.
A B/C code insertion means is provided, and the received data is sent to the receiving side using CH.
, C checking C I (, comprising a C checking means,
The frame liJ input method is characterized in that when the frame synchronization signal is detected on the receiving side, the data of the frame to which the synchronization signal belongs is checked by the cttc checker 2 means.