JPS5961151A - Insulated type semiconductor device - Google Patents
Insulated type semiconductor deviceInfo
- Publication number
- JPS5961151A JPS5961151A JP17165382A JP17165382A JPS5961151A JP S5961151 A JPS5961151 A JP S5961151A JP 17165382 A JP17165382 A JP 17165382A JP 17165382 A JP17165382 A JP 17165382A JP S5961151 A JPS5961151 A JP S5961151A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- radiating substrate
- resin
- heat dissipation
- fitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
技術分野
本発明は放熱板裏面に外装樹脂Ｈによる絶縁層を＋＋１
成１した半導体装置に関する。[Detailed description of the invention] Technical field The present invention provides an insulating layer made of exterior resin H on the back surface of the heat sink.
The present invention relates to a semiconductor device that has been manufactured.
背最技術
第１図及び第２図は樹脂モールド型半導体装置の一例を
示すもので、１は半導体ペレット２を固定した放熱基板
で、数例用の穴１ａを穿設している。３は図示例では３
本１組のリードで、中央のり一部３ａを基板１に固定し
、両側のリード３ｂ。1 and 2 show an example of a resin molded semiconductor device. Reference numeral 1 denotes a heat dissipation substrate to which a semiconductor pellet 2 is fixed, and a hole 1a for several examples is bored therein. 3 is 3 in the illustrated example.
One set of leads fixes the center glue part 3a to the board 1, and the leads 3b on both sides.
３Ｃの一端をベレット２の近傍に配置している。One end of 3C is placed near the pellet 2.
４はベレット２とリード３ｂ 、３ｃとを電気的に接続
した金属細線、５はベレット２を含む主要部分を樹脂材
にて被覆し外装した樹脂外装部を示す。Reference numeral 4 indicates a thin metal wire electrically connecting the pellet 2 and the leads 3b and 3c, and 5 indicates a resin exterior portion in which the main portion including the pellet 2 is covered with a resin material.
この半導体装置はベレット２の発生熱を効率よく放出す
るために外部の放熱器に取付穴１ａを利用して固定され
る。この場合、放熱基板ｌはベレット２の裏面電偽と電
気的に接続されているなめ、第３図に示すように放熱基
板ｌと放熱器６の間にマイカ板−等の絶縁ンート７を挾
み、取付穴１ａに絶縁ブツシュ８を介してネジ９て固定
し、放熱器６と放熱基板ｌの絶縁を保っている。ざらに
熱抵抗を低下きせるために放熱器６と絶縁シート７及ヒ
絶縁シート７と放熱基板１の間にシリコーングリス等を
充填している。This semiconductor device is fixed to an external heat radiator using the mounting hole 1a in order to efficiently release the heat generated by the pellet 2. In this case, since the heat dissipation board l is electrically connected to the back surface electrode of the pellet 2, an insulating piece 7 such as a mica plate is inserted between the heat dissipation board l and the heat sink 6 as shown in FIG. The heat sink 6 is fixed to the mounting hole 1a with a screw 9 through an insulating bush 8 to maintain insulation between the heat sink 6 and the heat sink board l. Silicone grease or the like is filled between the heat sink 6 and the insulating sheet 7 and between the insulating sheet 7 and the heat dissipating board 1 in order to roughly reduce the thermal resistance.
これにより半導体ベレット２は放熱性の良好な放熱器６
に固定濫れるが、取付作業が煩届な上、絶縁シート７や
絶縁ブツシュ８が必要であるという欠点があった。As a result, the semiconductor pellet 2 becomes a heat sink 6 with good heat dissipation.
However, there are disadvantages in that the installation work is cumbersome and an insulating sheet 7 and an insulating bushing 8 are required.
そのため第１図半導体装１−の樹脂外装部５を放熱基板
ｌの裏面及び数例穴りａ内周まてＩｇ長影形成、直接放
熱器に取付可能とし、絶縁シート７や絶縁ブツシュ８を
省き作業を良好にしたものがある。Therefore, the resin exterior part 5 of the semiconductor device 1- in FIG. There is something that makes the work easier.
この半導体装置は例えば第４図に示す樹脂モールド金型
を用い製造される。図において１０は下金型で、放熱基
板１を収容する凹部１０ａより数例穴１ａを貫通する突
起１１を突設し、凹部１０ａの底面１０ｂと放熱基板ｌ
の裏面とが一定間隔を保つようにリード３を支持してい
る。１２は」二金型で、下面に下金型１０の四部１０ａ
と対応する四部１２ａを形成、し、突起１１の先端を収
納する凹孔１３を穿設している。また上下金７１ｉＱ’
ＩＯ，１２は密着しり一部３を挾持固定している。凹部
１０ａ。This semiconductor device is manufactured using, for example, a resin mold shown in FIG. In the figure, reference numeral 10 denotes a lower mold, in which protrusions 11 are protruded from the recess 10a that accommodates the heat dissipation board 1, penetrating several holes 1a, and the bottom surface 10b of the recess 10a and the heat dissipation board l
The lead 3 is supported so that a constant distance is maintained between the lead 3 and the back surface of the lead 3. 12 is a two-mold mold, with four parts 10a of the lower mold 10 on the bottom surface.
Four portions 12a corresponding to the four portions 12a are formed, and a recess 13 for accommodating the tip of the protrusion 11 is bored therein. Also upper and lower gold 71iQ'
IO, 12 clamps and fixes the close contact portion 3. Recessed portion 10a.
１２ａ（キャビティ）、突起１１ｔ／ｉ放熱基板１から
−４の間隔、間隙を形成している。このキャビティ内に
図示しないがゲートから樹脂を注入し硬化させることに
より、絶縁型半導体装置がＴ’Ｊられる。12a (cavity) and the protrusion 11t/i form a spacing of -4 from the heat dissipation substrate 1. The insulated semiconductor device is T'J'ed by injecting resin into this cavity from the gate (not shown) and curing it.
しかしながら、この半導体装置は放熱基板裏面の樹脂層
の厚みがばらつき易く、この部分の厚みが薄いと、耐電
圧不良となり、厚いと放熱効果が低下するという欠点が
あった。However, in this semiconductor device, the thickness of the resin layer on the back surface of the heat dissipation substrate tends to vary, and if the thickness of this part is thin, the withstand voltage will be poor, and if it is thick, the heat dissipation effect will be reduced.
これはキャビティと放熱基板１０間隙を金型によるリー
ド３の締付けたけて規正しているために生しるもので、
完全に除去することができなかった。This occurs because the gap between the cavity and the heat dissipation board 10 is regulated by tightening the leads 3 using the mold.
could not be completely removed.
そのためζ第５図に示すようにキャビティの放熱基板１
と対向する面に部分的突起１４を設け、これて間隔を規
正し樹脂層・の厚みを一定にすることもできるが、この
半導体装置は放熱基板１の裏面の一部が露呈し、しかも
樹脂層の厚みが薄いため、放熱器に固定した場合、放熱
基板１の露呈部から放熱器までの樹脂層に沿う沿面距離
が短かく耐電圧が十分得られないという問題があった。Therefore, as shown in ζFig.
It is also possible to provide a partial protrusion 14 on the surface facing the heat dissipating substrate 1 to regulate the interval and make the thickness of the resin layer constant, but in this semiconductor device, a part of the back surface of the heat dissipation substrate 1 is exposed, Since the thickness of the layer is thin, when it is fixed to a heat radiator, there is a problem that the creepage distance along the resin layer from the exposed part of the heat radiating substrate 1 to the radiator is short and a sufficient withstand voltage cannot be obtained.
発明の開示
本発明は」二記決点に鑑み提案きれたもので、耐電圧や
放熱効果を低下させることなく放熱板裏面に均一な厚み
の絶縁層を形成した半導体装置を挽）供する。DISCLOSURE OF THE INVENTION The present invention has been proposed in view of the following two points, and provides a semiconductor device in which an insulating layer of uniform thickness is formed on the back surface of a heat sink without reducing withstand voltage or heat dissipation effect.
本発明は放熱基板上に載滌した半導体ペレ′ントと一端
を半導体ベレットの近傍に配置しｆｃ ’） −）”と
を電気的に接続し、半導体ベレ′ント並びに放ｆｌｐ基
板の裏面を含む主要部分を樹脂相にて外装したものにお
いて、上記放熱基板裏面に異径凹部をほぼ同心的に形成
すると共に、大径の異径凹部にタト装樹脂林をほぼ充実
させたことを特徴とする。The present invention electrically connects a semiconductor pellet mounted on a heat dissipating substrate with one end disposed near the semiconductor pellet, fc') -)", and includes the semiconductor pellet and the back surface of the flp substrate. The main part is covered with a resin layer, and is characterized in that concave portions of different diameters are formed almost concentrically on the back surface of the heat dissipation board, and that the large concave portions of different diameters are almost completely covered with resin forest. .
本発明は上記構成により次のような効果を有する。The present invention has the following effects due to the above configuration.
１ 樹脂モールド時に放熱基板の滴径凹部に企画すキャ
ヒテイに設けた突起を仲人するたけでキャビティ内壁と
放熱基板との間隔を一定にてきるため、樹脂層（絶縁層
）の厚みを均一にできる。1 During resin molding, the distance between the inner wall of the cavity and the heat dissipation board can be made constant by simply adjusting the protrusion provided on the cavity in the droplet diameter concave part of the heat dissipation board, so the thickness of the resin layer (insulating layer) can be made uniform. .
２ 大径の異径凹部を外装樹脂相にてほぼプロ実させる
ことにより、放熱基板の裏面側の樹脂が被世／１［ない
部分から樹脂外装表面１てり）沿面距離を長くでき、耐
電圧の低下がなし・。2 By making the large and different diameter recesses almost fully formed in the exterior resin layer, the resin on the back side of the heat dissipation board can extend the creepage distance (from the missing part to the resin exterior surface 1), increasing the durability. No voltage drop.
発明を実施するための最良の形態
以下に本発明の実施例を第６図乃至第１１図力・ら説明
する。第６図及び第７図にお（／１で１５は半導体ベレ
ット１６を固定した放熱基板で、数例用穴１５ａは裏面
側が大径、表面側力ｉ ／Ｊ’ｌ径のゲ妊径穴（異径凹
部）１５ｂ、１５ｃを同心的に穿設している。１７は図
示例では３本１組のＩＪ −ドて、ｌコ央のり一部１’
７ａの一端をＬ字状に屈曲し、端音すを基板１５に固定
し、両側の１ノー）”１７ｂ、１７ｃをリード１７ａと
平行配列して一端部をペレ・ント１６の近傍に配置して
いる。１８はベレ゛ント１６とリード１７ｂ 、１７ｃ
とをそれそね電気０勺に接続した金属細線、１９けペレ
゛ント１６、ＩＪ −）−１７の基部、金属細線１８を
被覆すると共に放熱基板１５の外周面及び数例７ｉ：ｌ
５ ａの内１間面全被ＩＩした樹脂外装部（絶縁層）
を示す。この樹月旨外装により取イ」用の穴２０は、放
熱基板１５の数例穴１５ａと同軸的に形成、きれる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to FIGS. 6 to 11. In FIGS. 6 and 7, 15 is a heat dissipation board to which a semiconductor pellet 16 is fixed, and the hole 15a for several examples has a large diameter on the back side and a hole with a diameter of 1/J'l on the surface side. (Concave portions with different diameters) 15b and 15c are concentrically bored.In the illustrated example, 17 is a set of three IJ-dores, and a part 1' of the l-column center glue.
One end of lead 7a is bent into an L-shape, the lead end is fixed to the board 15, and the leads 17b and 17c on both sides are arranged parallel to the lead 17a and one end is placed near the lead 16. 18 is the verent 16 and the leads 17b and 17c.
The thin metal wires connected to the electric wires 19, the bases of the 16 and IJ-)-17, the thin metal wires 18, and the outer circumferential surface of the heat dissipation board 15 and several examples 7i:l
5 Resin exterior part (insulating layer) covered entirely on one side of a.
shows. The hole 20 for removal is formed and cut coaxially with the hole 15a of the heat dissipation board 15 by this outer covering.
この半導体装置は第４図に示す樹脂モールド置が用いら
れるが、取（ｑ穴１５ａＫ挿入する突起１１’を、第８
［７１ｉＣ示スヨうに異径穴］、５ｂ、１５ｃの段部
で係合し、各穴１５ｂ、１５ｃより小径にしたことのＶ
、相異する。この突起１１′により放熱基板１５の裏面
とキャビティの間隔ｌは一定に設定される。This semiconductor device uses the resin molding arrangement shown in FIG.
[Different diameter holes as shown in 71iC], 5b and 15c are engaged at the stepped portions, and the V is made smaller in diameter than each hole 15b and 15c.
, different. The distance l between the back surface of the heat dissipating substrate 15 and the cavity is set to be constant by this protrusion 11'.
また数例穴り５ａ内周面の樹脂の厚みｔ１＋ ｔ２は放
熱基板１５裏面の絶縁層の厚みｅより十分大きく設定さ
れる。In some cases, the thickness t1+t2 of the resin on the inner peripheral surface of the hole 5a is set to be sufficiently larger than the thickness e of the insulating layer on the back surface of the heat dissipation board 15.
これにより放熱基板１５裏面の樹脂層（絶縁層）の厚み
を均一にでき、耐電圧を保ち放熱性を均一にできる。Thereby, the thickness of the resin layer (insulating layer) on the back surface of the heat dissipation board 15 can be made uniform, and the withstand voltage can be maintained and the heat dissipation performance can be made uniform.
尚、本発明は上記実施例にのみ限定されることなく、例
えば異径凹部は１通孔たけでなく、第９図に示すように
有底てもよい。この場合、放熱器への取付用穴は別設さ
れる。特に異径凹部は同心的に形成することが好ましい
が、若干偏心させることもてきる。また第１０図及び第
１１図に示すように異径凹部１５ｂ、１５ｃの連結部を
テーパ状にしてもよい。芒らには第１２図に示すように
キャビティ内に突設する突起１１″の大径部１１’ａと
小径部］１′ｂ との間の段部から大径部１１′ａの
周面に切欠部１１’ｃを設けるこ々によって、半導体装
置の異径凹部１５ｂ、１５ｃ 内周面の樹脂層を連通
し放熱基板１５に対する接着力を向上させ、捷た樹脂層
から露呈する放熱基板の面積を小さくすることもてきる
。It should be noted that the present invention is not limited to the above-mentioned embodiments; for example, the recessed portions having different diameters may not only have one hole, but may have a bottom as shown in FIG. 9. In this case, the mounting hole for the heat sink is provided separately. In particular, it is preferable that the recesses of different diameters be formed concentrically, but they may also be formed slightly eccentrically. Further, as shown in FIGS. 10 and 11, the connection portion between the different diameter recesses 15b and 15c may be tapered. As shown in FIG. 12, the awn includes a step between the large diameter part 11'a and the small diameter part 1'b of the protrusion 11'' protruding into the cavity, and the circumferential surface of the large diameter part 11'a. By providing the notch 11'c in the semiconductor device, the resin layers on the inner circumferential surfaces of the recesses 15b and 15c of different diameters are communicated with each other to improve the adhesion to the heat dissipation board 15, and the heat dissipation board exposed from the torn resin layer is improved. It is also possible to reduce the area.
第１図は半導体装置の一例を示す一部透視平面図、第２
図は第１図Ａ−Ａ面図、第３図は第１図半導体装置の取
イ」例を示す側断面図、第４図は絶縁型半導体装置の製
造方法を示す樹脂モールド装置の側断面図、第５図は第
４図装置の変形例を示す部分側断面図、第６図は本発明
の一実施例を示す一部透視平面図、第７図は第６図Ｅ−
Ｂ面図、第８図は第６図装置の製造方法を示す樹脂モー
ルド装置の要部側断面図、第９図乃至第１１図は本発明
の変形例を示す要部側断面図、第１２図は本発明の他の
実施例を説明するために用いられるモールド袋物、の突
起を示す斜視図である。
１５・・・・ 放熱基板、
１５ａ、１５ｂ、１５ｃ 異径凹部、１６・・・・
半導体ベレット、
１７・・・リード、
１９・・ 樹脂外装部。
２
第４図
］３
第５図
第 ６ 図FIG. 1 is a partially transparent plan view showing an example of a semiconductor device, and FIG.
The figure is a side view taken along line A-A in Figure 1, Figure 3 is a side sectional view showing an example of the semiconductor device in Figure 1, and Figure 4 is a side sectional view of a resin molding device showing a method for manufacturing an insulated semiconductor device. 5 is a partial side sectional view showing a modification of the device shown in FIG. 4, FIG. 6 is a partially transparent plan view showing an embodiment of the present invention, and FIG.
B view, FIG. 8 is a side sectional view of the main part of the resin molding device showing the manufacturing method of the device shown in FIG. 6, FIGS. The figure is a perspective view showing a protrusion of a molded bag used to explain another embodiment of the present invention. 15... heat dissipation board, 15a, 15b, 15c different diameter recesses, 16...
Semiconductor pellet, 17... Lead, 19... Resin exterior part. 2 Figure 4] 3 Figure 5 Figure 6
Claims (1)
ペレットの近傍に配置したリードとを電気的に接続し、
２１を導体ベレット並びに放熱基板の裏面を含む主要部
分を樹脂脂相にて外装したものにおいて、］・記放熱基
板裏ｍＩＫ異径門部をほぼ同心的に月ヅ成すると共に、
大径の異径凹部に外装樹脂相をほぼ充実させたことをｑ
！Ｊ徴とする絶縁型半導体装置The semiconductor pellet placed on the heat dissipation board 2 is electrically connected to a lead whose one end is placed near the semiconductor pellet,
21, in which the main parts including the conductor pellet and the back surface of the heat dissipation board are covered with a resin phase, ]-The back mIK of the heat dissipation board is formed in a substantially concentric manner, and
The fact that the exterior resin phase is almost completely filled in the large and different diameter recesses is q.
! Insulated semiconductor device with J characteristic
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17165382A JPS5961151A (en) | 1982-09-30 | 1982-09-30 | Insulated type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17165382A JPS5961151A (en) | 1982-09-30 | 1982-09-30 | Insulated type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5961151A true JPS5961151A (en) | 1984-04-07 |
| JPS638615B2 JPS638615B2 (en) | 1988-02-23 |
Family
ID=15927197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17165382A Granted JPS5961151A (en) | 1982-09-30 | 1982-09-30 | Insulated type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5961151A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016047083A1 (en) * | 2014-09-22 | 2016-03-31 | 株式会社デンソー | Method for manufacturing electronic device, and electronic device |
-
1982
- 1982-09-30 JP JP17165382A patent/JPS5961151A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016047083A1 (en) * | 2014-09-22 | 2016-03-31 | 株式会社デンソー | Method for manufacturing electronic device, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS638615B2 (en) | 1988-02-23 |
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