JPS596062B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, particularly a semiconductor device having a two-layer polysilicon structure.

Conventionally, this type of semiconductor device with a two-layer polysilicon structure has been used, for example, in a memory LS with an n-channel silicon gate structure.
It is often used in I. An example of a semiconductor device having this structure is shown in FIG. That is, in this FIG. 1, 1 is a silicon semiconductor substrate, 2 is a silicon oxide film, 3 and 4 are a first layer and a second layer polysilicon, respectively.
These first and second layer polysilicon layers 3 and 4 are usually used as gate electrodes of the first and second MOS transistors, respectively, with parts of them overlapping each other, and with this structure, for example, one transistor type dynamic R
The AM memory cell structure can be simplified and the area occupied on the chip can be reduced. However, the planar simplification of such a device is ultimately achieved by a complicated three-dimensional structure, and this complexity also leads to an increase in surface irregularities. This tends to cause problems such as wire breakage and short circuits.

In order to reduce this disconnection accident, measures such as reflowing the phosphor glass layer to make the surface smooth are adopted, and as for the short circuit phenomenon, insulation between the first layer polysilicon and the second layer polysilicon is used. The amount is reduced by changing the layer formation method, especially the film quality and thickness.・
Regarding the latter short-circuit phenomenon, the inventors' experiments have shown that the occurrence rate and inter-polysilicon breakdown voltage increase depending on the pattern shape of the first layer polysilicon below the second layer polysilicon. It turns out that the width changes.

An example of this experiment will be described next. Figure 2a is an example of an experiment.
The polysilicon pattern shown in 3b was used to compare the two.

In other words, in FIG. 2a, a first layer polysilicon 3 having a U-shape with each bent part at right angles is combined with a second layer polysilicon 4 which is overlapped with the first layer polysilicon 3, and
In Figure b, on the contrary, the second layer polysilicon 4 having a U-shape with each bend at a right angle is superimposed on the first layer polysilicon 3, and these are combined as shown in Figure 1 above. They were formed using the same method on the same 5-chip soil.
However, the manufacturing method is to generate a silicon oxide film 2' with a thickness of 500λ, which corresponds to X in FIG.
The first layer polysilicon 3 has a thickness of 5000λ by low pressure CVD method.
Then, by normal photolithography, the unnecessary portions of this first layer polysilicon 3 are removed by etching, and a silicon oxide film 2 for inter-polysilicon insulation corresponding to Y in FIG. 1 is produced. At the same time, a silicon oxide film 2 corresponding to z is also generated. At this time, Z
A silicon oxide film 2 with the same thickness as the Y part has already been formed in the Y part, and in order to further form an oxide film on top of it, the growth rate is slower than that in the Y part. Since it is grown on the first layer polysilicon 3 that is heavily doped with phosphorus or the like, its growth rate becomes faster. To give specific numbers, 950℃, 0 wet
By oxidation for 2 and 30 minutes, Y is 1400λ and Z is 8
It becomes 50λ. Further, a second layer of polysilicon 4 was deposited thereon, and elements were then formed according to normal processes. However, the first layer polysilicon 3 and the second layer polysilicon 4 constructed in this way
When we measured the dielectric breakdown voltage between
In the case of the configuration shown in FIG. 2b in which the second layer polysilicon layer 4 is U-shaped, the voltage is about 80V, and the former is about % of the latter.

Considering the conditions, this difference in breakdown voltage can only be considered to be due to the difference in pattern shape, and when this was observed in detail, it was found that in the inner corner part 5 of the pattern of the first layer polysilicon 3 in the former case, It was found that cracks 6 as shown in FIG. 3 had occurred. The cause of the occurrence of the crack 6 in the inner corner portion 5 of the pattern is considered to be as follows.

That is, during oxidation after the first layer polysilicon layer 3 is formed, this oxidation progresses laterally from the edge of the polysilicon pattern through the oxide film at the bottom of the pattern, as shown by reference numeral 7, thereby causing the edge of the pattern to oxidize. As the part bulges upward, the side part is simply lifted up as the part indicated by the dotted line in Fig. It gives rise to Further, this crack 6 becomes longer as oxidation progresses at the portion 7, and the width becomes larger as the angle θ of the inner corner portion 5 becomes smaller. And like this, the inner corner 5
When a crack 6 occurs, polysilicon oxidation begins on the surface of the crack that was exposed at the time of occurrence, and the oxide film in this crack becomes thinner than the oxide film in other parts, so that the subsequent second layer polysilicon oxidizes. After the deposition of polysilicon 4, the breakdown voltage between the second layer polysilicon 4 and the crack inevitably decreases.

This invention was made to improve the above-mentioned drawbacks of the conventional technology, and by making the inner angle of the bent part pattern of the first layer polysilicon larger than the right angle, cracks can be prevented. This is designed to minimize the occurrence of such occurrences.

An embodiment of the present invention will be described below with reference to FIG.

This FIG. 4 corresponds to the above-mentioned FIG. 2 a, and
The same reference numerals in the drawings represent the same or equivalent parts. In this embodiment, the angle of the inner corner portion 5 of the pattern is set to be a larger angle than a right angle. Specifically, the inner corner portion 5 is chamfered with a straight line and By forming two inner corner portions 5a, 5b, the angle of each inner corner portion 5a, 5b is set to 135 mm.

As a means for reducing the cracks in this case, firstly, the silicon oxide film under the first layer polysilicon 3 is made thinner, and the oxidation of the polysilicon itself is reduced.
The second method is to suppress the progress of oxidation at the inner corner portion 5, or to increase the angle θ at the inner corner portion 5 as in the above embodiment, but the former method directly affects the performance of the formed element. Therefore, the latter method is used in the present invention, and the angle of the inner corner 5 is 90 as described above, according to experiments conducted by the inventors. , the dielectric breakdown voltage decreased significantly, but it was observed that it significantly increased when the voltage was 135 or higher.

Note that even if the angle θ of the inner corner portion 5 is 90, a round will be formed during the actual photolithography and etching process, and the breakdown voltage will be high due to this round, but the accuracy of the photolithography will be reduced. The problem gradually decreases as the technology improves, and it is thought that this problem will become more serious as the refinement technology progresses, and in particular, the importance of the means according to the present invention will increase.

Although the above description has been about a semiconductor device with a MOS structure,
Of course, the present invention can be applied to all other semiconductor devices having a two-layer polysilicon structure.

As detailed above, according to the present invention, a semiconductor device having a two-layer polysilicon structure in which a second layer polysilicon is superimposed on a first layer polysilicon having a bent pattern shape with an insulating layer interposed therebetween. , the dielectric breakdown voltage between the first layer and the second layer polysilicon can be increased by an extremely simple means of forming the inner angle of the bent portion pattern to be larger than the right angle, and It has features of extremely great practical value.

[Brief Description of the Drawings] Figure 1 is a cross-sectional view showing an overview of a semiconductor device with a two-layer polysilicon structure, Figures 2A and b are plan views showing a conventional polysilicon structure, and Figure 3 is the upper part of the same. FIG. 4 is an explanatory plan view corresponding to FIG. 2a, showing an embodiment of the polysilicon structure according to the present invention. DESCRIPTION OF SYMBOLS 1...Silicon semiconductor substrate, 2...Silicon oxide film, 3, 4...First layer, second layer polysilicon, 5...Inner corner part .

Claims (1)

[Claims] 1. A silicon oxide film is formed in an oxidizing atmosphere on a first layer polysilicon having a bent pattern formed on an insulating layer, and a second layer polysilicon is formed on the first layer polysilicon through this silicon oxide film. In the method of manufacturing a semiconductor device having a two-layer polysilicon structure, the inner angle of the bent portion pattern of the first layer polysilicon is formed at a larger angle than a right angle. .