JPS5960264A - Signal detection circuit - Google Patents

Abstract

PURPOSE:To enable the compensation of offset voltage at a high accuracy for a short time by holding and computing A/D conversion output information. CONSTITUTION:A switch 7 is connected to a calibration circuit 9 to hold a digital value of a composite offset voltage of a brdige 1 and an A/D converter 6 therein 9. Then, the switch 7 is connected to a data holding circut 8 to hold an A/D conversion output with a pressure applied thereto therein 8. The circuit 8 and 9 shall be a binary-coded information memory circuit and the number of bits equal in the number of digits to the output of the converter 6. The binary subtraction circuit 10 subtracts an offset level of the circuit 9 from the held value of the circuit 8 to obtain a true signal value.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal detection circuit, and more particularly to a signal detection circuit that compensates for offset voltage.

Conventionally, offset voltage compensation in a signal detection circuit A'1 (
There were methods such as resistor trimming and charge storage in a capacitive element, but resistor trimming requires a lot of man-hours, is time consuming, and is expensive. The method using a small capacitive element has the disadvantage that it is not possible to completely compensate for the offset voltage within a finite time.

The purpose of this research is to provide a signal detection circuit that can compensate offset voltage in a short time, at low cost, and with high precision.

According to the present invention, a signal detection circuit can be obtained that includes an A/D converter, two memory circuits that hold information on the output of the A/D fi converter, and an arithmetic circuit that processes the information in the memory circuit.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. S
In this example, a block 1 surrounded by a broken line is a bridge made of a diffused resistor in an example of detecting a t-diaphragm pressure-up sensor signal. Terminals 2 and 3 are power supply terminals, and terminals 4 and 5 are output terminals. The voltage signal obtained from the output terminal is input to the A/D converter 6, and the digital output is transferred to the data holding circuit 8 or the calibration circuit 9 by the switch 7. 10 is a binary subtraction circuit that performs subtraction between the data holding circuit 8 and the calibration circuit 9.

Next, the method of signal detection will be described. Even when no pressure is applied to the output terminals 4 and 5 of the bridge 1, an offset voltage is generated due to variations in resistance value and distortion during assembly. Further, the A/D converter 6 also has an offset voltage due to variations in elements.

If there is an offset Ichikawa, the positive 6 of the signal (It
71 cannot be detected, so first connect the switch 7 to the calibration circuit 9 and hold the digital value of the combined offset voltage of the bridge 1 and the A/D converter 6 in the calibration circuit 9. The switch 7 is connected to the data holding circuit 8, and the A/D conversion output with pressure applied is sent to the data holding circuit 8.
to hold. The data holding circuit 8 includes the composite offset voltage in addition to the true signal voltage. Data holding circuit 8
and the calibration circuit 9 are both like flop-flops.
The value 4 yen is sent by the information storage circuit, and the number of pits is 6 by the A/D converter.
The number of digits is the same as the output of . The data holding circuit 8 and the calibration circuit 9 can be operated manually by either a row of lights or parallel lights.

Finally, the binary (stratification) circuit 10 subtracts the offset amount held in the calibration circuit 9 from the value held in the data holding circuit 8 to obtain the true signal value.

The timing of calibration may be done at the first measurement level.
You may do this only when you insert u.

The following conversion type also works. Further, blocks 1 to 10 can be assembled on one silicon substrate.

The sensor portion shown in block 1 is not limited to the St diaphragm type pressure sensor, but may be any other sensor. FIG. 2 shows a block diagram of another embodiment of the invention. Block 1 shown as broken is a Hall element, terminals 2 and 3 are current terminals, and terminals 4 and 5 are voltage terminals. In the case of a Hall element, in which a signal voltage proportional to the magnetic flux level is generated between the voltage terminals '1) and 1 when a magnetic field is applied perpendicular to the plane of the paper, an offset voltage is generated due to misalignment of the voltage terminal positions. Blocks 6 to 10 are the same as the blocks in Figure 1, and the offset voltage calibration method is the same.The calibration method according to the present invention can be performed in an extremely short time compared to laser trimming, etc., and moreover, the power is cut off after -m calibration. Until then, the offset amount is held in the calibration circuit, so there is no need for calibration, and the true signal can be obtained with high precision just by subtracting. With ordinary advanced circuit technology, an A/D converter with a resolution of about 1 mV easily leaks f1'j, so the offset voltage can be reduced to 1 mV.

[Brief explanation of the drawing]

FIG. 1 shows a St diaphragm type I which is an embodiment of the present invention.
FIG. 2 is a block diagram of the signal detection circuit of the F-type magnetic sensor, and FIG. 2 is a block diagram of the signal detection circuit of the pole element magnetic sensor which is the third embodiment of the present invention. 1...Sensor 2, :3...Electric whale terminal (11 is flow terminal) 4.5...
Output terminal 6...A/D converter 7...Switch 8...Data holding circuit 9...Positive circuit
]0...Subtraction circuit 31

Claims (1)

[Claims] Holding information on the A/D converter and the output of the A/D converter 2
A signal detection circuit characterized in that it includes two conventional circuits and an arithmetic circuit for processing information in the memory circuit.