JPS595934B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device that employs an interrupt overrun method.

Normally, in information processing equipment, when a calculation result overflows, a program interrupt is generated to notify the software, but since such an interrupt is made using the calculation result, it tends to become a critical path in terms of time, and the entire system is This could be a factor in determining the machine cycle.

Therefore, an overrun method is sometimes used to delay the occurrence of an interrupt by one cycle or more. In this case, since the next instruction will be executed, it is necessary for the interrupt processing hardware to return the completed instruction to the state before execution.
On the other hand, even if an error occurs during the execution of an instruction, in order to increase availability, a method is often used to return to the state before the instruction was executed and re-execute it. Reverting operation is required. By the way, in order to return to the state before the instruction was executed, the data up to that point must be saved to a buffer register, but the data save buffer for interrupt overrun recovery and the data save buffer for instruction re-execution are separated. Moreover, having a buffer amount sufficient to satisfy each request to the maximum extent would result in an increase in hardware, resulting in an excessive investment for the system as a whole. The present invention was made in view of the above-mentioned circumstances, and it is an object of the present invention to share a data save buffer for interrupt overrun recovery and a data save buffer for instruction re-execution, and to minimize the amount of the buffer. The objective is to provide an information processing device that enables

Since the present invention is particularly effective when applied to instruction disassembly control, an embodiment thereof will be described below, but first an outline of the instruction disassembly method will be explained.

As is well known, large-scale data processing devices employ a pipeline system to process instructions at high speed. In this method, independent hardware is prepared for instruction decoding, operand address calculation, operand reading, and operation execution, and multiple instructions are processed in parallel. in this case,
Arithmetic processing is often handled by microprograms, and other processing is done by hardware. The unit that decodes the command, calculates the operand address, and controls the reading of the operand is called the advance control unit.
The part that executes calculations is called a calculation unit. Normally, the processing of one instruction is preprocessed by a preceding control unit, and then a microprogram is started and terminated. Complex instructions with variable operand length follow a similar flow, but in order to speed up such cases in particular, the instruction unit decomposes a complex instruction into a series of simple instructions, and It uses a control system that starts the microprogram as many times as necessary. This is the instruction disassembly method. In this case, since the same microprogram is activated many times, necessary information such as the end of an instruction is controlled by hardware. Considering an interrupt overrun, if the next instruction is an instruction in this instruction disassembly format, part of the disassembled instruction group will be executed due to the interrupt overrun, so it is necessary to return to the state before execution. Is required. The same holds true when considering re-execution of an instruction. The feature of the present invention is that interrupt overrun recovery logic and instruction re-execution logic are shared.
In particular, this is applied to instruction disassembly control. 1st
The figure shows the overall configuration of an embodiment of an information processing apparatus of the present invention.

In the figure, 1 is a preceding control device that controls instruction decoding, operand address calculation, and operand reading, 2 is an arithmetic unit, 3 is a control storage device that stores a microprogram, 4 is a data save control unit, and 5 is for data save. 6 is a buffer register, 6 is a main storage device, and 7 is an input/output control device. Typically, instructions are read from the main memory 6 and conveyed to the advance control device 1 via a signal line 110. The advance control device 1 decodes the instruction, sends the address to the main memory 6 through the signal line 108 to start operand reading, and further sends the microprogram to the control memory 3 through the signal line 100 to run the necessary microprogram. Send command address. The operand activated by the preceding control device 1 is conveyed to the preceding control device through the signal line 110, and after necessary queuing is performed, it is set in a predetermined work register of the arithmetic unit 2 through the signal line 101. On the other hand, in the control storage device 3, a predetermined microprogram is activated based on the microinstruction address sent from the preceding control device 1, and controls the arithmetic unit 2, data save control section 4, and data save buffer register 5. When the command is finished,
The control memory 3 issues an EOP (end of operation) and receives a microinstruction address from the preceding controller 1 again. When other than EOP, control storage device 3
is a microinstruction that specifies the next microinstruction address. The data saving buffer register 5 is commonly used for saving data for instruction re-execution and interrupt overrun recovery, and in this embodiment, it has a configuration of 8 bytes x 4. Saving data is sent from the arithmetic unit 2 through the signal line 105, and read data for recovery is sent from the signal line 106.
3, a write pointer (information indicating which of the four registers is indicated) and a write pulse, or a read pointer and a read pulse are sent. The data save control unit 4 controls the buffer register 5.
The above-mentioned read/write pointer and read/write pulse are created based on an evacuation instruction by a microinstruction sent from the control storage device 3 through the signal line 107 and a control signal sent from the preceding control device 1 through the signal line 104. The input/output control device 7 controls the main storage device 6 and the terminal device (
(not shown), but since it is not directly related to the present invention, further explanation will be omitted. As mentioned above, the present invention is effective when applied to instruction disassembly control.

As part of this instruction disassembly control, a load multiple instruction (hereinafter abbreviated as LM instruction) will be taken up here. FIG. 2 shows the format of the LM command. That is,
The LM instruction consists of 32 bits (4 bytes), and the first 8
The bit (1 byte) is the instruction code, and the next 4 bits are R1.
The 4 bits are the R3 field, the 4 bits are the B2 field, and the last 12 bits are the D2 field. This instruction sets the value obtained by adding the contents of the general-purpose register specified by the B2 field and the contents of the D2 field as the first address on the main memory, and data after this address is transferred from the general-purpose register specified by the R1 field. This is an instruction to write to the general-purpose register specified by the R3 field. Each time, the advance control unit 1 reads the operand in units of 8 bytes (or 4 bytes), and the arithmetic unit 2 performs the processing of writing it to the general-purpose register each time. The instruction disassembly method attempts to process the operands by disassembling them into a series of load instructions. The data required to re-execute the instruction is as follows.

That is, the target is data that is destroyed after execution of this instruction and that is necessary for re-execution. Specifically, this includes the instruction itself (because it may be destroyed by a store instruction, etc.), general-purpose registers for the base (for index), floating point registers, etc., but in the case of LM instructions, the base register (
only the contents of the register specified by field B2). On the other hand, let's consider recovery from an interrupt overrun. When the next instruction is a long instruction, even if a completion type interrupt occurs after the previous instruction is executed, the next LM instruction will be partially executed. The amount of execution depends on the design policy of the device, but generally it can be considered that the overrun will be one to two cycles. In this case, the first one or two cycles of the LM instruction will be executed. Since only 8 bytes (corresponding to 2 general-purpose registers) are destroyed in one cycle, it is necessary to save the contents of 8 to 16 bytes of general-purpose registers.

In this way, the data required for re-execution of the LM instruction and the data required for recovery from interrupt overruns are combined into the contents of the base register and the contents of the general-purpose registers that are destroyed in the first 1 to 2 cycles. .

Now, assume that data is read and written to and from the main memory in units of 8 bytes, and that each general-purpose register group has a 4-byte structure.

Therefore, in the case of the LM instruction, 8 bytes of data read from the main memory are written to the general-purpose register indicated by the R1 field and the general-purpose register at the address +1 indicated by the R1 field each time. To save data prior to this write operation, the general-purpose register indicated by the R1 field and the R1 field +1
The data in the general-purpose register indicated by will be read. According to the instruction format in Figure 2, the number of general-purpose registers is 1.
There are 6, so there is a possibility of reading a maximum of 16x4-64 bytes with the LM instruction. It is preferable to save all of this data, but generally speaking, having a buffer for saving this amount will increase the amount of hardware, making it an excessive investment for the system as a whole (because it is effectively used only by LM instructions) ). Therefore, in the embodiment of the present invention shown in FIG. 1, the data save buffer register 5 only has 32 bytes (8 bytes x 4) as described above, and in the case of an LM instruction, the general-purpose register Out of the data read from the , data that needs to be saved is identified, and control is performed to save only that data to the data save buffer register 5 . Specifically, in the case of an LM instruction (generally in the case of instruction disassembly control), the pointer of the data save buffer register 5 is updated sequentially from the first to the second cycle so that the save data is saved; After the cycle, the pointer is controlled not to be updated, and data is uploaded to the save buffer indicated by the same pointer.

This is because, as described above, in the case of an interrupt overrun, when the next LM instruction is executed, the first one or two cycles thereof are executed. Furthermore, in the case of the LM command,
When the contents of the base register are destroyed, control is performed to unconditionally update the pointer of the data save buffer register 5 and save the data. Whether or not the contents of the base register are destroyed depends on the contents of the R1 field and B2.
This is done by comparing the contents of the fields. On the other hand, in the case of instructions other than instruction disassembly control, the pointer of the data save buffer register 5 is updated each time, and the data is saved in a first-in/first-out format. As a result, all the data necessary for interrupt overrun recovery and re-execution is saved, and the data save buffer can be realized with a small amount of data. Hereinafter, with reference to FIG. 1, a specific configuration example of the advance control device 1 and the data save control section 4, which are particularly related to the present invention, will be explained.

FIG. 3 is a diagram showing the advance control device 1 of FIG. 1 in more detail.

In the figure, 11 is an instruction buffer, 12 is an instruction register, 13 is a general-purpose register group, 14 is an address control circuit, 1
5 is an adder that performs address calculations, etc., 16 is an address register that holds the addition result, 17 is a +2 circuit used to control instruction disassembly, 18 is a stage control circuit that controls the start of instruction decoding, success of decoding, etc., and 19 is an address register that holds the addition result. Comparator group, 2
0 is a stage control circuit for LM instructions, and 21 is an instruction buffer for passing control to the arithmetic unit. Instructions are read from main memory 6 and stored in instruction buffer 11 via signal line 110.

Thereafter, at an appropriate time, the instruction 4 is transferred from the instruction buffer 11.
A byte is extracted and set in the instruction register 12.
The following explanation will be given assuming that the LM instruction is set in the instruction register 12 in Cx. The 0p code of the instruction (LM instruction) set in the instruction register 12 is subjected to necessary queuing and set in the instruction queue buffer 21.
to the control storage device 3 through the signal line 100 at an appropriate time;
It is sent as a microinstruction address to run the required microprogram. On the other hand, the operand address is calculated using adder 15 and set in address register 16. That is, the B2 field of the instruction register 12 is selected by the address control circuit 14, and the contents of the general-purpose register 13 specified by the B2 field are transferred to the adder 15.
The content of the D2 field of the instruction register 12 directly becomes the other input of the k adder 15, and the value obtained by adding the two is set in the address register 16 as the operand address. This operand address is sent to the main memory device 6 through the signal line 108, and as a result, the data (8 bytes) read from the main memory device 6 is transferred to the general register indicated by the R1 field of the instruction register 12 and the next one. The data is divided into 4 bytes and written to the general register. In the meantime, the operand address of the address register 16 is incremented by 8 by the adder 15 and set to 0 again in the address register 16. Also, the value of the R1 field of the instruction register 12 is incremented by 2 by the +2 circuit 17 and set to the R1 field. be returned. Thereafter, the contents of the instruction buffer 21 are sent to the control storage device 3 again, and the operand address of the address register 16 is sent to the main storage device 6 to execute loading of the next operand data. Thereafter, the same operation is repeated. That is, the I instruction is processed as a series of load instructions for 8-byte operands. As will be described later, one of the comparators 19 compares the R1 field and R3 field of the instruction register 12.
It is used to compare the contents of the fields, and if they match, the stage control circuit 18 is sent through the signal line 130.
The end of the LM command is issued to.

This causes the stage control circuit 18 to transition to a state such as starting decoding of the next instruction. The remaining comparators 19 are newly prepared according to the present invention, and set the signal line 131 to "1" when the contents of the base register are destroyed. The L stage control circuit 20 is also prepared according to the present invention, and when the 0P code of the instruction register 12 is input and the LM instruction is issued, the signal line 140 is continuously set to "1", and the signal line 141 is set to LM. The LM stage control circuit 20 is set to "1" only in the first cycle of the instruction.
The operation timing is determined by the signal line 1 from the stage control circuit 18.
34. FIG. 4 is a diagram showing the comparator group 19 and rinse stage control circuit 20 of FIG. 3 in more detail.

In the figure, 190 is a comparator with R1=R3 or R1+1R3, which is used to detect the end of processing of the LM instruction. That is, when R1-R3 or R1+1-R3,
The output signal line 130 of the comparator 190 becomes "1".19
1 is a comparator with R1+1=B2, and 192 is a comparator with R1-B2.

193 is a comparator for R1-R3, and comparators 191 and 192
used to control the output of

That is, when R1=B2 is established by the comparator 192,
The signal line 131 becomes "1" unconditionally, but in other cases, under the condition that R1-R3 is not established by the comparator 193, when R1+1-B2 is established by the comparator 191, the signal line is 131 becomes "1". After being easily understood, when the signal line 131 becomes "1", it means that the operand data is written to the base register. In other words, the previous contents of the base register are destroyed. On the other hand, 30 is a decoding circuit for the LM instruction, and 31 is a latch circuit. When the decoding circuit 30 decodes the LM instruction, the signal line 1
1 is latched in the latch circuit 31 by a timing signal applied from the stage control circuit 18 through the stage control circuit 34. When the latch circuit 31 becomes "1", the signal line 140 also becomes "1". That is, the fact that the signal line 140 is "1" means that the LM instruction has been successfully decoded. 3
Reference numeral 2 denotes a differentiating circuit which sets the signal line 141 to ``1'' only during a predetermined period when 140 rises from ``0'' to ``1''.

That is, the period when the signal line 141 is "1" indicates the first cycle of execution of the LM instruction. The data save control section 4 in FIG.
It receives the states of 31, 140, and 141 and controls the updating of the pointer of the data save buffer register 5.

In FIG. 1, the signal lines 104 are 130, 140, 14
1 shows all signal lines. FIG. 5 shows an embodiment of the data save control section 4, which is a feature of the present invention.
The operations shown in FIG. 5 can be summarized as follows. First, when an instruction other than instruction disassembly control is indicated, the pointer of the data save buffer register is updated each time. Therefore, in this case, new data is saved to the buffer indicated by the updated pointer, and old data is erased, and the data save buffer register 5 as a whole is always filled with its capacity, that is, 8X4-32.
The latest bytes of saved data are saved. Next, L.M.
When an instruction in the instruction disassembly control format, which is represented by an instruction, is indicated, the pointer is updated for the first two cycles based on the principle described above, and is controlled not to be updated thereafter. Therefore, in the case of the LM instruction, save data is saved for the first two cycles. Furthermore, in the processing of the LM instruction, if the contents of the base register are updated (destroyed), the pointer is updated unconditionally. Now, in Figure 5, 30
, 31 is h from the beginning in instruction disassembly control such as LM instructions.
Pointers 40 and 41 that count up to a cycle are latches that hold the input pointer of the data save buffer register. 32 is a selection circuit for the input of the latch 30; 33
43 is a circuit that controls the operation of latch 30;
44 is a microinstruction decoding circuit for the signal line 107, and 34 and 42 are +1 circuits.

The latches 30, 31 actually consist of two bits, so the signal lines 200, 201, 202 are actually two. The latches 40 and 41 are also actually composed of 2 bits.
The selection circuit 32 selects the inverted state of the signal line 140 and the signal line 14.
When the signal line 142 indicating the logical sum with the state of is "1",
In other words, it is not an instruction disassembly control like the LM instruction (signal line 1
40 is "O") or the first cycle (
When the signal line 141 is "1", select the signal line 131, and when the signal line 131 is "O", output "00" to the signal line 202, and when the signal line 131 is "1" outputs “011” to the signal line 202. As explained in FIG. 4, the fact that the signal line 131 is "1" means that the contents of the base register are destroyed.
42 is "O", that is, after the second cycle in the instruction disassembly control, the selection circuit 32 returns the contents of the signal line 200 to the signal line 202.In other words, the pointer consisting of latches 30 and 31 It is initialized to 00'' or 101'' in the first cycle of instruction disassembly control or when it is not instruction disassembly control, and from the second cycle of instruction disassembly control onwards, the count value is incremented.In the case of an I instruction (generally ), when the pointer constituted by the latches 30 and 31 advances to ``11'', from then on
This state is maintained, and the control circuit 33 is in charge of this control.

FIG. 6 is a diagram showing the control circuit 33 of FIG. 5 in more detail.

In FIG. 6, the condition that the signal line 330 that sets the latch 30 in FIG.
40-"0"), the first cycle of the I command (141-"1"), the output signal line 201 of the latch 31 becomes "1" in the I command.
Either F' or not.

Whether it is an LM instruction or not can be determined by decoding the microinstruction on the signal line 107. Among these conditions, in the case of a non-LM instruction or the first cycle of an LM instruction, as shown in FIG. 5, the signal line 142 is ``1'', so the latch 30 is initialized to 600'' or ``0r''. Also, in the case after the second cycle of the LM instruction,
When the signal line 201 is not "11", the value obtained by incrementing the contents of the latch 31 by +1 circuit is set in the latch 30.
On the other hand, when the signal line 201 is '1r' in the LM command, the signal line 330 is O', and the setting operation of the latch 30 is prohibited. That is, in the case of an I instruction, once the pointer formed by latches 30 and 31 reaches the value ``1r'', it is held in the 11r'' state until the processing of the instruction is completed. The pointer composed of latches 40 and 41 in FIG. 5 increments by 1 when the output signal line 201 of latch 31 is other than 11r.
When the signal line 201 becomes "1F", the previous state is maintained.

Furthermore, if the signal line 131 is "1" due to a certain command, it is caused to advance regardless of the state of the signal line 201. A control circuit 43 controls the pointer made up of latches 40 and 41. FIG. 7 is a diagram showing the control circuit 43 of FIG. 5 in more detail.

In FIG. 7, signal line 430 sets latch 40.
The conditions for ``1'' are when the contents of the base register are destroyed by the LM instruction (131-6F''), when data saving is instructed by a microinstruction other than the LM instruction, and when the signal line 201 is Any of the cases other than ``1F''. The microinstruction on the signal line 107 is decoded to determine whether it is an LM instruction and whether the microinstruction instructs data saving. When the signal line 430 becomes 1r', it means that the data save buffer register pointer made up of latches 40 and 41 goes up by one. Returning to FIG. 5, the save data set signal for the data save buffer register is sent through the output line 440 of the decode circuit 44. Further, the input pointer value of the data save buffer register at this time is sent through the signal line 441. From the above explanation, the input pointer value of the save buffer indicated by the signal line 441 is updated by 1 in the case of not the instruction disassembly FbI leg, but in the case of instruction disassembly control until the latches 30 and 31 reach "1F". It can be seen that the command is updated at the beginning of K and is not updated thereafter.Furthermore, in the case of a special instruction, if the base register is updated, even if latches 30 and 31 are set to ``11'', It can be seen that the pointer value of the signal line 441 is updated.
In Figure 5, when the base register is destroyed (131
-'1'), the latch 30 is initialized to '0F' for the following reason.

In order to re-execute the LM instruction, it is necessary to save the contents of the base register. Furthermore, the data must be saved not only until the end of the I instruction, but also for two machine cycles after the LM instruction (because even if a machine check occurs with the LM instruction, it will be executed for two cycles before it stops).
If latch 30 is initialized to '00',
If the first cycle is a base register update cycle,
Since it is not possible to save two cycles, it is initialized to "0r" only in that case.As described above, according to the present invention, the data necessary for recovering from an interrupt overrun and re-executing an instruction is stored in both. All data are saved in a common buffer register, and this type of save buffer register can be executed with a small capacity.

It should be noted that the illustrated configuration is merely one example, and the present invention is not limited to this.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the information processing apparatus of the present invention, FIG. 2 is a diagram showing an example of the format of a load multiple (LM) instruction, and FIG. FIG. 4 is a diagram showing the comparator group 19 and I stage leg circuit 20 in FIG. 2 in more detail, and FIG. 5 is a diagram showing the data save control section 4 in FIG. 1 in more detail. FIG. 6 is a diagram showing the control circuit 33 of FIG. 5 in more detail, and FIG. 7 is a diagram showing the control circuit 43 of FIG. 5 in more detail. DESCRIPTION OF SYMBOLS 1... Advance control device, 2... Arithmetic device, 3... Control storage device, 4... Data save control unit, 5......・Data save buffer register, 6...main storage device, 7...input/output control device.

Claims (1)

[Claims] 1. If an error occurs during the execution of an instruction, control is provided to return to the state before execution of the instruction and re-execute it, and control to overrun the execution of the instruction by delaying detection of an interrupt so that it can be executed later. In an information processing device that employs control for recovering an instruction executed in an overrun, a data saving buffer means commonly used for saving data for re-executing the instruction and saving data for recovering from an overrun of the interrupt; , a pointer means for indicating an address of the data evacuation buffer means, and a control means for detecting the data evacuation necessary for recovering from the interrupt overrun and re-executing the instruction, thereby controlling the increment of the pointer means. An information processing device comprising: 2. In the information processing device according to claim 1, when the control means detects an instruction in an instruction disassembly control format (a control format in which an instruction is disassembled into a series of simple instructions and processed), An information processing apparatus characterized in that the pointer means is sequentially incremented for several cycles from 1 to 3, and that increment is prohibited thereafter. 3. The information processing apparatus according to claim 2, wherein the control means unconditionally increments the pointer means when the contents of the base register are destroyed.