JPS595907B2 - display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display device that controls the driving time and driving frequency of a display element such as a liquid crystal display according to changes in ambient waterfall.

When the ambient humidity of a display element, such as a liquid crystal display device, is high, the viscosity decreases, resulting in a faster response speed and lower threshold value.When the ambient humidity is lower, the higher the viscosity, the slower the response speed and lower threshold value. It has humidity characteristics that increase as the value voltage increases.

The driving method for displaying this liquid crystal display device using multiflex driving is to apply a voltage higher than the threshold voltage during display, and apply a voltage lower than the threshold voltage during non-display. 3 Uniformization methods have been proposed in the past, but as seen in the strainability characteristics mentioned above,
Liquid crystal displays have high temperature dependence, and display operations that provide good contrast in a predetermined density range, but if the surrounding density exceeds a predetermined density range, crosstalk may occur or If the density is below the density range, problems such as insufficient contrast or required display operations may occur. For this reason, in order to make the liquid crystal display perform a good display operation by multiflex driving, it is necessary to compensate for the degree of flooding by changing the applied voltage or changing the application time depending on the ambient humidity. Conventionally, as an example of strain compensation, it has been proposed to divide the power supply voltage by a resistance element such as a resistor and a thermistor, and use the resulting divided voltage as the driving voltage. Due to the division, power consumption is large and it is impractical for small electronic devices such as wristwatches and electronic desktop calculators that use batteries as a power source. Therefore, the present invention changes the drive time and drive frequency of the display element according to the ambient temperature, and when the response speed is low at low temperatures, the drive time width is lengthened and the drive frequency is lowered, while the response speed is fast. At times of high concentration, the drive time width is shortened and the drive frequency is increased to suppress excessive power supply and prevent the occurrence of crosstalk. The present invention proposes a display device that always provides a display with good contrast under a wide range of conditions, and the details thereof will be explained below based on the illustrated embodiments. Figure 1 shows
FIG. 2 is a diagram showing a case where an embodiment of the display device according to the present invention is used in an electronic timepiece.

Reference numeral 1 denotes an oscillation circuit using a crystal resonator or the like, and the original signal obtained by the oscillation circuit 1 is frequency-divided by a frequency division circuit 2j comprising a plurality of frequency division stages. The frequency dividing circuit 2 outputs a 1Hz reference signal as one frequency divided signal, and this signal is
It is fed to a "seconds" counter consisting of a sexagesimal counter 3. The "second" counter is a decimal counter 4.
and a hexadecimal counter 5. The carrier of the 8 minute counter is supplied to a 6 o'clock counter consisting of a decimal counter 6 and a binary counter 7.

Counter 4 - corresponding to "minute" and 6 o'clock for time display
The contents of each count of 7 are cyclically set to 0 by the timing pulse output from the timing pulse generation circuit 16.
N, 0FF controlled time division gates 8, 9, 10, 11
are respectively inputted and time-divided.

Counters 4 to 4 time-divided by time-division gates 8 to 11
The count contents of 7 are input to the decoder 12 and code-converted into a segment signal suitable for display on the 7-segment liquid crystal display 14. The segment signal output from the decoder 12 is supplied to the segment electrode drive circuit 13. The segment electrode 1 drive circuit 13 is supplied with a segment electrode drive voltage output from a 1 drive voltage generation circuit 19, which will be described in detail later.The segment electrode drive voltage is controlled by a segment signal from the decoder 12 and is applied to the liquid crystal display. It is applied to the segment electrodes of the display 14. On the other hand, the digit electrode drive circuit 15 includes an electric voltage generation circuit 1
A digit electrode drive voltage is supplied from 9, and the digit electrode drive voltage is controlled by the timing pulse output from the timing pulse generation circuit 16 mentioned above to the liquid crystal display 1.
4 is applied to the digit electrode. Reference numeral 17 denotes a mudness detection circuit that continuously changes the duty ratio of the pulse according to the surrounding depth, and generates a temperature detection signal using the frequency division signal from the frequency division circuit 2 as a periodic signal. The above temperature detection signal has the code 18
The signal is supplied to the drive frequency control circuit shown by , and is also applied to the drive voltage generation circuit 19 . In addition to the above-mentioned power detection signal, a plurality of frequency-divided signals outputted from the frequency dividing circuit 2 are input to the drive frequency control circuit 18. , is appropriately selected and output according to the duty ratio of the mud degree detection signal. The output signal is supplied to the 7 drive voltage generation circuit 19 as a frequency control signal. The drive voltage generation circuit 19 has a reference numeral 20.
From the booster circuit shown in ``0VD'', corresponding to the power supply voltage ``
1VD], double voltage “2VD” and triple voltage “3VD]
Four DC voltages of VD] are applied. These value current voltages are controlled by the input mud level detection signal and frequency control signal to become a segment drive voltage and a digit electrode drive voltage, and are supplied to a segment drive circuit 13 and a digit electrode drive circuit 15, respectively. As a specific example is shown in FIG. 2, the timing pulse generation circuit 16 generates a frequency divided signal N+1 outputted from the n+1th frequency dividing stage of the frequency dividing circuit 2, and a frequency divided signal N+2 outputted from the n+2th stage of the frequency dividing circuit 2. By using A cyclically generated circuit, consisting of four AND circuits 21, 22, 23.
, 24.

The AND circuit 21 receives the frequency-divided signals N+1 and N+2, and the AND circuit 22 receives the frequency-divided signal N+1 inverted by the inverter 25 and the frequency-divided signal N+2 inverted by the inverter 26. , AND circuit 23 has
The frequency-divided signal N+1 and the frequency-divided signal N+2 inverted by the inverter 26 are input, and the frequency-divided signal N+1 and the frequency-divided signal N+2 inverted by the inverter 25 are further input to the AND circuit 24. . In Figure 3, the frequency divided signal N+
1, N+2, and the waveforms of timing pulses A-D output from AND circuits 21 to 24 are shown. Figure 4 shows
This is a circuit diagram showing a specific example of the deepness detection circuit 17 and drive frequency control circuit 18 of the display device shown in FIG. 1. In the diagram, the same blocks as those shown in FIG. Therefore, the same reference numerals are given.

The depth detection circuit 17 is a monostable multivibrator constructed of a NOR circuit 27, an inverter 28, a thermistor 29, resistors 30 and 31, and a capacitor 32. One input terminal of the NOR circuit 27 has a frequency dividing circuit. n of circuit 2
The frequency-divided signal N in the first stage is input manually.

The output terminal of NOR circuit 27 is connected to the input terminal of inverter 28 via capacitor 32. In addition, one end of the thermistor 29 and a resistor 3 are connected to the input terminal of the inverter 28.
Further, the thermistor 29 and the other end of the resistor 30 are connected in common, and one end of the resistor 31 is connected to the terminal 33 to which the power supply voltage is applied. The output terminal of the inverter 28 is connected to the output terminal 34 and to the other input terminal of the NOR circuit 27. Note that the change in resistance value of the thermistor 29 with respect to temperature change is nonlinear, but by connecting the resistors 30 and 31 in series and parallel, the change becomes almost linear. In the mud level detection circuit 17 having such a configuration, when the frequency division signal N which is a synchronizing signal is input, the combined resistance value of the thermistor 29 and the resistors 30 and 31 and the capacitance of the capacitor 32 are output from the output terminal 34. A temperature detection signal E having a duty ratio determined by the value is output.

When the ambient temperature is high, the resistance value of the thermistor 32 becomes small, and the combined resistance value and the capacitor 3
Since the time constant determined by the capacitance value of 2 becomes short, the duty ratio is small, and at low temperatures, the resistance value of the thermistor 30 becomes large and the duty ratio becomes large. In FIG. 5, the frequency division signal N is shown as a waveform N, the depth detection signal E at high depth is shown as a waveform Eh, and the temperature detection signal E and waveform El at low mud are shown. In this way, the output terminal 34 of the temperature detection circuit 17 outputs a temperature detection signal E whose duty ratio changes continuously according to changes in the surrounding muddy degree, and the temperature detection signal E is outputted to the drive frequency control circuit 18 and the drive voltage generation circuit 19. Supplied.

The drive frequency control circuit 18 indicated by reference numeral 18 has an inverter 35 that inverts the temperature detection signal E, and the output of the inverter 35 is input to the first input terminal of a three-input AND circuit 36.

On the other hand, the frequency-divided signal N+1 output from the n+1-th frequency dividing stage of the frequency dividing circuit 2 is directly applied to the P channel side gates of transmission gates 37 and 40 and the N channel side gates of transmission gates 38 and 39. On the other hand, it is applied to the N-channel side gate of the transmission gate 37 and the P-channel side gate of the transmission gate 38 via the inverter 41.
It is applied to the P-channel side gate of the transmission gate 39 and the N-channel side gate of the transmission gate 40 via. code 4
Reference numeral 3 denotes an input terminal to which a signal F having a cycle of 1 minute is outputted from a sexagesimal counter (indicated by reference numeral 3 in FIG. 1) which is a second counter, and a signal F inputted from the input terminal 43 is inputted. is supplied to the transmission gate 37 and also applied to one input terminal of the NOR circuit 44.

The output terminal of the transmission gate 37 and the output terminal of the transmission gate 38 are commonly connected and connected to the input terminal of the inverter 45, and also to the input terminal of the transmission gate 39, and further connected to one input terminal of the NOR circuit 47. be done. The output terminal of the inverter 45 is connected to the other input terminal of the NOR circuit 44 and, via the inverter 46, to the input terminal of the transmission gate 38. The output terminal of transmission gate 39 and the output terminal of transmission gate 40 are commonly connected and connected to the input terminal of inverter 48 . The output terminal of inverter 48 is connected to the other input terminal of NOR circuit 47 and is also connected to the input terminal of transmission gate 40 via inverter 49 . The output terminal of the NOR circuit 44 is connected to the reset terminal of a counter 50 consisting of a two-stage flip-flop, and the output terminal of the NOR circuit 47 is connected to the second input terminal of the three-way AND circuit 36. The third input terminal of the three-input AND circuit 36 is applied with the frequency division signal N-3 from the N3th frequency division stage of the frequency division circuit 2, and the output terminal is connected to the input terminal of the counter 50. Ru.

The output from the output terminal Q1 that outputs the count contents of the counter 50 is applied to each input terminal of an AND circuit 51 and an AND circuit 53, and is also applied to an AND circuit via an inverter 54.
applied to the input terminal of circuit 52. Similarly, counter 5
The output from output terminal Q2 that outputs the count content of 0 is A
It is applied to the input terminals of each of the ND circuit 52 and the AND circuit 53, and is also applied to the input terminal of the AND circuit 51 via the inverter 55. The output of the AND circuit 51 is input to an AND circuit 56 to which the frequency division signal M from the m-th frequency division stage of the frequency division circuit 2 is input. The output of the AND circuit 52 is input to an AND circuit 57 to which the frequency division signal L from the 'th frequency division stage of the frequency division circuit 2 is input. The output of the AND circuit 53 is input to an AND circuit 58 to which the frequency division signal K from the K-th frequency division stage of the frequency division circuit 2 is input. The outputs of the AND circuits 56, 57, and 58 are respectively input to the three-input 0R circuit 59. The output of the three-input 0R circuit 59 is supplied to the drive voltage generation circuit 19 via the output terminal 60. Note that among the frequency-divided signals K, L, and M, the frequency-divided signal K has the highest frequency, and the frequency-divided signal M has the lowest frequency, and the frequency-divided signal M has a higher frequency than the frequency-divided signal N. . In the drive frequency control circuit 18 having such a configuration, when the signal F having a period of 1 minute is inputted through the input terminal 43, the signal G is output from the output terminal of the NOR circuit 44 as shown in FIG. , a signal H is output from the output terminal of the NOR circuit 47, respectively. The signal G becomes a reset pulse for the counter 50, and the signal H whose phase is delayed by the pulse width of the frequency-divided signal N+1 from the signal G is combined with the temperature detection signal E inverted by the inverter 35 and the frequency-divided signal N-3. The signal is input to a 3-input AND circuit 36. Therefore, the counter 50 receives the humidity detection signal E only during the period when the signal H is output.
A frequency-divided signal N-3 is input in accordance with the duty ratio of . FIG. 7 shows a waveform diagram when the number of pulses input to the counter 50 is 1, where N+1 is the frequency-divided signal N+
1, H is the signal H output from the NOR circuit 47, N
-3 is a waveform diagram showing the frequency divided signal N-3, Ei is the inverted temperature detection signal E, and I is a waveform diagram showing the pulse input to the counter. When the pulse I shown in FIG. 7 is input to the counter 50, the output terminal Q1 of the counter 50 changes to logic 8r', and the output terminal of the AND circuit 51 becomes logic '1'.

Therefore, the frequency-divided signal M input to the AND circuit 56
is output from the AND circuit 56, appears at the output terminal 60 via the 0R circuit 59, and becomes the frequency control signal J. Similarly,
Every minute, the frequency-divided signal N-3 is counted by the counter 50 according to the duty ratio of the inverted temperature detection signal E.
In response to the contents of this count, the frequency-divided signals L and K are also selected and supplied to the drive voltage generation circuit 19 as the frequency control signal J.

FIG. 8 is a waveform diagram of frequency-divided signals K, L, and M, and waveform N in the figure shows the waveform of frequency-divided signal N.

FIG. 9 is a circuit diagram showing a specific example of the drive voltage generation circuit 19, segment electrode drive circuit 13, and digit electrode drive circuit 15 shown in FIG. The same reference numerals are given to the parts to make the explanation easier to understand. The drive voltage generation circuit indicated by reference numeral 19 has an input terminal 61 to which a muddyness detection signal E is applied, and the vorticity detection signal E is inputted to a level shifter 62 via the input terminal 61.

The output of the level shifter 62 is the N of the transmission gates 63 and 65.
Directly applied to the channel side gate and the P channel side gate of the transmission gates 64 and 66, and inverted by the inverter 67 to the P channel side gate of the transmission gate 63;
The voltage is applied to the N-channel side gate of the transmission gate 64, and is further inverted by the inverter 68.
It is applied to the P channel side gate of No. 5 and the N channel side gate of transmission gate 66. The input terminal of the transmission gate 63 receives a DC voltage of "1VD" output from the booster circuit 20, and the input terminals of the transmission gates 64 and 66 receive a "0V" DC voltage.
A DC voltage of “D” is input, and a DC voltage of “2VD” is input to the input terminal of the transmission gate 65.
Output terminals 3 and 64 are commonly connected and connected to input terminals of transmission gates 69 and 72. Also transmission gate 6
Output terminals 5 and 66 are connected in common and are also connected to input terminals of transmission gates 70 and 71. transmission gate 6
N channel side gates 9 and 71 and transmission gates 70 and 72
The frequency control signal J input via the input terminal 73 is amplified by the level shifter 74 and input to the P channel side gate of the transmission gate 69 and the N channel side gate of the transmission gate 70. The output of the level shifter 74 is inverted by an inverter 75 and inputted to the channel side gate, and the output of the level shifter 74 is inputted to the P channel side gate of the transmission gate 71 and the N channel side gate of the transmission gate 72. is inverted and input by . The drive voltage generation circuit 19 also receives the NΦ circuit 77 to which the mud level detection signal E and the frequency control signal J are input, and the output of the level shifter 62 and the output from the level shifter 74 which has been inverted by the inverter 78. A
It has an ND circuit 79 and a level shifter 80 that amplifies the output of the AND circuit 77. The output of the level shifter 80 is connected to a terminal 81, the output terminals of the transmission gates 69 and 70 are both connected to a terminal 82, the output terminals of the transmission gates 71 and 72 are both connected to a terminal 83, and the output of the AND circuit 79 is connected to a terminal 84. The terminals 81 to 84 serve as output terminals of the drive voltage generation circuit 19. The segment signals outputted from the decoder 12 and inputted to the segment voltage drive circuit 13 are amplified by level shifters 85a to 85g, and then are converted into control signals for gate circuits 13a to 13g corresponding to segment electrodes a to g, respectively. becomes.

Gate circuits 13a-13g include two transmission gates 86, 87 and 1, as shown in detail for 13a.
each inverter 88. The P channel side gate of the transmission gate 87 and the N channel side gate of the transmission gate 87 are connected to each other, and the level shifter 85
The segment signal of the decoder 12 amplified by a is directly applied, and a level shifter inverted by an inverter 88 is applied to the N-channel side gate of the transmission gate 86 and the P-channel side gate of the transmission gate 87, which are connected to each other. 8
The output signal from 5a is applied. Also, transmission gate 86
The output from the terminal 82 of the drive voltage generation circuit 19 described above is applied to the input terminal of the transmission gate 87, and the output from the terminal 81 is applied to the input terminal of the transmission gate 87. Transmission gate 86, 8
The 7 output terminals are commonly connected and connected to corresponding segment electrodes a to g, respectively. The digit electrode drive circuit 15 that drives the digit electrode YlX4 of the liquid crystal display 14 is connected to the digit electrode
Gate circuits 15X1 to 15X4 corresponding to 1 to X4, respectively
and level shifters 89A to 89D corresponding to gate circuits 15X1 to 15X4. Gate circuit 15X, ~
15X4 is each composed of two transmission gates 90, 91 and one inverter 92, as shown in detail for 15X. The N-channel side gate of the transmission gate 90 and the P-channel side gate of the transmission gate 91 are connected to each other, and the level shifters 89A to 89D amplify the timing pulses A, B, C, and D from the timing pulse generation circuit 16, respectively. The outputs are directly applied to each, the P channel side gate of transmission gate 90 and the N channel side gate of transmission gate 91 are connected to each other, and the outputs of level shifters 89A to 89D are inverted by inverter 92 and inputted. Further, the output from the terminal 84 of the driving voltage generation circuit 19 is applied to the input terminal of the transmission gate 90, and the output from the terminal 83 is applied to the input terminal of the transmission gate 91. The output terminals of transmission gates 90 and 91 are commonly connected and connected to corresponding digit electrodes X1 to X4, respectively. Note that the level shifters 62, 74, 80, 85a
~85g, 89A~89D are "3VD" from the booster circuit 20.
], the input signal is level-shifted to a voltage of 3VD, and the reference voltage D of the booster circuit 20 is set to 2VD.
With the circuit that doubles or triples the
”, “2VD”, and “3VD” DC voltages are output. The operation mode of the embodiment according to the present invention having such a configuration will be explained. Now, when the surrounding depth is high, the input terminal 61 of the drive voltage generation circuit 19 receives the mudness detection signal E as shown by the waveform Eh in FIG. 10, and the input terminal 73 receives the frequency control signal J. (Signal of waveform K shown in Figure 8)
are applied respectively.

Therefore, signals indicated by 81a to 84a in FIG. 10 are outputted to the output terminals 81 to 84, respectively. That is, from the terminals 82 and 83, the voltages "1VD" and "2VD" are outputted alternately with the period of the signal J only for the period of the pulse width of the temperature detection signal E, and from the terminals 81 and 84, the mud level detection signal is outputted. "0VD" and "3VD" only during the pulse width period of E.
" voltage is output alternately at the period of signal J. terminal 81
84 to 84 as shown in FIG. 10, the voltage applied to the segment electrode a and the digit electrode How it changes depending on the timing pulse A is shown in FIG. In FIG. 11, N+1 is the frequency-divided signal N+
1 waveform, A is the waveform of sampling pulse A, 12a is a waveform representing the segment signal of the decoder 12 for segment electrode a, Ya is the voltage waveform applied to segment electrode a, and X and a are applied to digit electrode X1. voltage waveform,
XY is a waveform representing the voltage applied between the segment electrode a and the digit electrode X1. As understood from the waveform X-Y, the segment signal 12 output from the decoder 12
When both a and timing pulse A are not output, there is a gap between segment electrode a and digit electrode X1.
1V0'' pulse voltage is supplied, the liquid crystal display 14 does not display, and only when the segment signal 12a output from the decoder 12 and the timing pulse A are output together, the connection between segment electrode a and digit electrode In between is ``3''
A pulse voltage of "VD" is supplied, and the liquid crystal display 14 performs a display operation. Note that FIGS. 10 and 11 show the temperature detection circuit 1.
7 to 5 show waveforms when the mud degree detection signal E shown by waveform Eh is output. FIG. 12 is a waveform diagram showing the change in the driving pulse when the mud level detection signal E changes depending on the surrounding mud level. E is output, and accordingly, the frequency division signal K is output from the drive frequency control circuit 18.
is selected and output as the frequency control signal J. The waveform of the drive pulse is shown when the frequency division signal M is selected and output as the modulus frequency control signal J.

As can be seen from Fig. 12, the depth detection signal E is El-Eh.
As the frequency changes, the divided signals K, L, and M as the frequency control signal J are selected in stages, so the driving time width of the driving pulse that drives the liquid crystal display 14 changes continuously, and the driving time width of the driving pulse that drives the liquid crystal display 14 changes continuously. The frequency changes in stages.

That is, when the surrounding mud degree is high, the duty ratio of the temperature detection signal E output from the mud degree detection circuit 17 using a thermistor is small and the driving frequency control circuit 1 accordingly
The frequency of the signal J output from 8 is also high. Therefore, when the driving time width of the liquid crystal display 14 is short and the driving frequency is high but the ambient muddyness is low, the duty ratio of the temperature detection signal E is large, and therefore the driving time width of the liquid crystal display 14 becomes long. , the driving frequency becomes lower. In this way, at high temperatures, the driving time width becomes shorter and the frequency becomes higher, reducing the effective driving power and preventing the occurrence of crosstalk.
At low temperatures, the driving time width becomes wider and the driving frequency becomes lower, so that the effective driving power increases, the delay in response speed is compensated for, and a display with good contrast can be obtained under a wide range of vorticity. Next, the fact that vorticity compensation of a display element is actually possible by changing the drive time and drive frequency, which is the objective of the display device according to the present invention, will be explained with reference to the drawings shown below.

FIG. 13 is a curve diagram showing the results of an experiment to confirm how the driving voltage of the display element and its range change with respect to changes in the degree of mud.

Here, when the duty ratio of the driving pulse of the display element is set to 1, the curve P shows the boundary where the display disappears at a voltage lower than this, and the curve P2 shows the boundary where the display disappears when a voltage higher than this is applied. This is a curve showing the limit at which talk occurs. Curve Q1 is a curve that shows the limit at which the display disappears at a voltage lower than this when the duty ratio of the driving pulse of the display element is set to 0.5, and curve Q2 is a curve that shows the limit at which the display disappears when a voltage higher than this is applied. This is a curve showing the limit at which talk occurs. According to this experimental result, for example, when driven with a duty ratio of 1 and a drive voltage of 4.5V, O~2
Although good contrast can be obtained in the muddy range of 0℃,
It can be seen that crosstalk occurs when the temperature exceeds 20°C. Therefore, by keeping the driving voltage constant (4.5V),
In order to further expand the display temperature range, the deep temperature should be set to 20℃.
When the temperature exceeds that temperature, if you drive with a duty ratio of 0.5, display operation is possible up to 45°C, and even up to 50°C.
It can be seen that in order to increase the temperature to above ℃, the duty ratio should be reduced. FIG. 14 is a curve diagram showing the relationship of 1 drive voltage with respect to changes in duty ratio in ordinary mud. Curve R1 is a curve showing the limit 1 drive voltage at which the display disappears when the duty ratio is changed. curve R
2 is a curve showing the limit driving voltage at which chromatographic distortion occurs in the display when the duty ratio is changed.

Figure 15 shows a constant frequency (125Hz) at room temperature.
), curve S1 is a duty ratio of 1, curve S2 is a duty ratio of 0.88, and curve S3 is a duty ratio of 0.76.
, curve S4 has a duty ratio of 0.64, and curve S5 has a duty ratio of 0.64. The relationship between drive voltage and transmittance for each case of A ratio of 0.5 is shown.

FIG. 16 is a diagram showing the relationship between drive voltage and transmittance when the drive frequency is changed at room temperature. Curve T1 is at a drive frequency of 12.5Hz, curve T2 is at a drive frequency of 125Hz, and curve T3 is at a drive frequency of 12.5Hz. The relationship between drive voltage and transmittance is shown for each case where the frequency is 1.25 KHz. Note that the duty ratio in FIG. 16 is 1. 13th,
As can be seen from the actual and experimental results shown in Figures 14, 15, and 16, changing the duty ratio of the drive pulse, that is, the drive time width, or changing the drive frequency to compensate for the temperature of the display element will reduce the drive voltage. It is clear that it has the equivalent function of changing.

Although the details of the display device according to the present invention have been described above based on the illustrated embodiments, the present invention is not limited to the illustrated embodiments, and various changes and improvements can be made.

As described above, according to the display device according to the present invention, since the driving time width and driving frequency of the display element are automatically changed according to changes in the ambient humidity, the response speed at high temperatures or at low temperatures can be increased. It is possible to compensate for the decrease in response speed at times, provide the best display with good contrast under a wide range of conditions, and suppress excessive power supply during times of high muddy conditions. can be achieved,
This has a great effect on implementation.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an electronic timepiece to which a display device according to the present invention is applied, FIG. 2 is a circuit diagram showing a specific example of the timing pulse generation circuit in FIG. 1, and FIG. , FIG. 4 is a circuit diagram showing a specific example of the temperature detection circuit and drive frequency control circuit shown in FIG. 1, and FIG. 5 is a diagram showing waveforms for explaining the operation of the timing pulse generation circuit. 6, 7, and 8 are waveform diagrams for explaining the operation of the drive frequency control circuit shown in FIG. 4. , FIG. 9 is a circuit diagram showing a specific example of the drive voltage generation circuit and drive circuit shown in FIG. 1, and FIG. 10 is a waveform for explaining the operation of the drive voltage generation circuit shown in FIG. 9. 11 is a waveform diagram for explaining the operation of the drive circuit shown in FIG. 9, and FIG. 12 is a waveform diagram showing the driving time width and driving frequency for driving the liquid crystal display according to changes in the peripheral depth. A waveform diagram showing the changing state, Fig. 13 is a curve diagram showing the relationship between vorticity change and drive voltage, Fig. 14 is a curve diagram showing the relationship between duty ratio and 1 drive voltage, and Fig. 15 is a curve diagram showing the relationship between duty ratio and drive voltage. FIG. 16 is a curve diagram showing the relationship between driving voltage and transmittance when changing the driving frequency. FIG. 16 is a curve diagram showing the relationship between driving voltage and transmittance when changing the driving frequency. 1...Oscillation circuit, 2...Divide circuit, 3
~7...Counter, 8-11...Time division gate, 12...Decoder, 13...
- Segment electrode drive circuit, 14... Liquid crystal display as a display element, 15... Digit electrode drive circuit, 16... Timing pulse generation circuit, 17.
... deepness detection circuit, 18 ... drive frequency control circuit, 19 ... drive voltage generation circuit, 20.
...Booster circuit, 29...Thermistor as a temperature-sensitive resistance element.

Claims (1)

[Claims] 1 A temperature detection circuit that detects the ambient temperature and generates a temperature detection signal whose duty ratio changes according to the detected temperature, the temperature detection signal and a signal with a predetermined frequency are input, and the temperature detection circuit The temperature detection signal and the frequency control signal are inputted to a drive frequency control circuit that generates a frequency control signal whose frequency changes according to the frequency, and the drive frequency control circuit generates a frequency control signal whose frequency changes according to the pulse width of the temperature detection signal. and a drive voltage generation circuit that generates a drive voltage with a frequency equal to that of the signal, and the drive voltage generated from the drive voltage generation circuit determines the drive time width and drive frequency of the display element, and the drive voltage is determined according to the ambient temperature. A display device characterized by automatically controlling the brightness of a display element.