GB2076576A

GB2076576A - Liquid Crystal Driving Circuit

Info

Publication number: GB2076576A
Application number: GB8114611A
Authority: GB
Original assignee: Tokyo Shibaura Electric Co Ltd
Current assignee: Toshiba Corp
Priority date: 1980-05-19
Filing date: 1981-05-13
Publication date: 1981-12-02
Also published as: JPS56162794A; DE3119281A1

Abstract

A liquid crystal matrix driving circuit has a display data generator (28), a column driver (26) driving the column electrodes of a liquid crystal display unit (20) according to data from the data generator (28), and a row driver (30) driving the row electrodes cyclically. A further control circuit (32) generates a control signal of duty-cycle which may be manually variable. Row and column drivers (30,26) output zero voltage to the respective electrodes in response to the control signal from the control circuit (32). The duty cycle may be varied to compensate for temperature changes. <IMAGE>

Description

SPECIFICATION Liquid Crystal Driving Circuit The present invention relates to a liquid crystal driving circuit for driving liquid crystal in a multiplex manner.

A liquid crystal display unit which is driven in a multiplex manner has, in general, a liquid crystal body, N number of row electrodes formed on one surface of the liquid crystal body, M number of column electrodes formed on the opposite surface of the liquid crystal body, and a driving circuit for selectively exciting at least one liquid crystal segment at an intersection of the column and row electrodes by applying control voltages having a plurality of levels to the respective column and row electrodes.In this case, a voltage-averaging method is adopted for controlling the excitation of the liquid crystal segments by varying the mean value over time or the root-mean-square (rms) value of the voltage applied across the column and row electrodes in the individual liquid crystal segment so that a desired liquid crystal segment may be excited irrespective of the polarity of the applied voltage.

Figures 1 and 2 are a plan view and a sectional view, respectively, of the liquid crystal unit generally used. This liquid crystal unit includes liquid crystal 10, transparent plates 12-1 and 1 2-2 arranged in opposite to each other so as to form part of a casing (not shown) of the liquid crystal 1 0, and row electrodes 14-1 to 14-3 and column electrodes 1 6-1 to 16-M disposed on the transparent plates 12-1 and 12-2, respectively.Voltage signals having a period T and three levels of O, E and 2E as shown in Figures 3A to 3C are applied to the row electrodes 14-1 to 14-3. Voltage signal applied to the row electrode 14-1 changes the voltage level from E to 2E at a time tri from the voltage level 2E to the voltage level E at a time t2 (T/6 after the time t1), from the voltage level E to the voltage level 0 at a time t3 (T/3 after the time t2), from the voltage level 0 to the voltage level E at a time t4 (T/6 after the time t3), and from the voltage level E to the voltage level 2E at a time t5 (T/3 after the time t4, that is, T after the time t1).The voltage signals applied to row electrodes 14-2 and 14-3 have the same waveforms as that of the voltage signal applied to the row electrode 14-1, and they have the respective, delays of T/6 and T/3 with respect to the voltage signal applied to the row electrode 14-1.

Voltage signals having voltage levels of 0 and 2E are selectively applied to the column electrodes 1 6-1 to 16-M. These voltage signals also have a period T and have such waveforms as to selectively excite the liquid crystal segments at the intersections of the row electrodes 14-1 to 14-3 and the column electrodes 1 6-1 to 16-M in cooperation with the voltage signals applied to the row electrodes 14-1 to 14-3. In this case, the rms value of the voltage applied across the column and row electrodes depends upon the voltage level of the voltage signal of the column electrode when the voltage signal applied to the row electrode is at O or 2E level.This is because, when the voltage signal applied to the row electrode is at the voltage level E, the voltage across both electrodes becomes either +E(V) or -E(V) and its absolute value becomes constant whether the voltage signal applied to the row electrode is O or 2E. The maximum rms value of the voltage across both electrodes is obtained when a voltage at the level 0 or 2E is applied to the column electrode while the voltage applied to the row electrode is at the voltage level 2E or O. The minimum rms value is obtained when the voltage applied to the row electrode is at the voltage level 0 or 2E while the voltage at the voltage level 2E or O is applied to the column electrodes.For example, when the voltage as shown in Figure 4B is applied to the column electrode as the voltage as shown in Figure 4A is being applied to the row electrode, the voltage across both electrodes becomes as shown in Figure 4C, and the maximum rms value "'V MAxi obtained may be given by the following equation::

When the voltage as shown in Figure 4D is applied to the column electrode while the voltage as shown in Figure 4A is being applied to the row electrode, the voltage across both electrodes becomes as shown in Figure 4E and the minimum rms value MINI obtained may be given by the following equation

It is known that when an AC voltage having an rms value V is applied across the column and row electrodes, the relationship between the lighting contrast of the liquid crystal and the rms value becomes as shown in Figure 5 (it is assumed here that 100% contrast may be obtained when a maximum voltage is applied across the column and row electrodes). This relationship between the lighting contrast and the rms value is dependent on the ambient temperature.For instance, the lighting contrast-rms value V characteristics as shown by the solid line are obtained at a temperature T1. It thus follows that the characteristic as shown by the broken line is obtained at a temperature T2 which is higher than the temperature T1 . The rms values VONI and TOFF1 required for lighting and extinguishing the liquid crystal segment at the temperature T1 are greater than the rms values VON2 and VOFF2 required for lighting and extinguishing the liquid crystal segment at the temperature T2.Therefore, in order to suitably drive the liquid crystal display unit shown in Figures 1 and 2 within the temperature range of T1 to T2, the maximum and minimum rms values57MAx and as given by equations (1) and (2) must satisfy the relation: VMIN1 < VOFF2 < VON1 (3) Although it is possible to satisfy this requirement when the temperature range is narrow, it is difficult to satisfy this relation over the entire normal temperature range. This particularly applies to the case when the ratio of the multiplexing is greater, that is, when the number of the row electrodes is greater. This is because when the number of the row electrodes increases, the ratio of the maximum rms value VMAX1 to the minimum rms value VMIN1 becomes closer to 1.

In order to solve these problems, it has been conventionally known to adjust the maximum and minimum rms values by varying the levels of the liquid crystal driving voltages as shown in Figure 6.

Referring to Figure 6, a liquid crystal driving circuit 18 has three resistors 18-1 to 18-3 seriesconnected between a power source terminal Vcc and ground. The resistor 1 8-1 is a variable resistor, and the resistors 18-2 and 18-3 have the same resistance R. By suitably varying the resistance of the variable resistor 18-1, the voltage levels E and 2E of the voltage signal generated for driving a display unit 1 9 from the liquid crystal driving circuit 1 8 are controlled.Supposing that VMAX1 and VEIN1 respectively designate the maximum and minimum rms values for a voltage applied to the liquid crystal display unit 19 when the variable resistor 18-1 is set to have 0 resistance, then the maximum and minimum rms values VMAX2 and VMiN2 when the resistance of the variable resistor 1 8-1 is set to R1 are given by the following equations:: 2R VMAX2 VMAX1 (4) 2R+R1 2R VMIN2= VEIN1 (5) 2R+R1 As may be apparent fr9m equations (4) and (5), by adjusting the resistance of the variable resistor 1 8-1 according to the ambient temperature, it becomes possible to set the maximum rms value VMAXZ to be larger than the lighting rms value VON and to set the minimum rms value VEIN2 to be smaller than the extinguishing rms value VOFF. However, when the liquid crystal driving circuit 18shown in Figure 6 is used, current constantly flows through the resistors 18-1 to 18-3, resulting in a large power consumption by this circuit.It is, therefore, unsuitable to use this liquid crystal driving circuit with an electronic circuit which requires small power consumption, such as an electronic watch circuit.

The primary object of the present invention is to provide a liquid crystal driving circuit which is capable of varying the rms value of the liquid crystal driving voltage and which consumes little power.

According to an aspect of the present invention, there is provided a liquid crystal driving circuit comprising a control circuit which generates a control signal of variable duty-cycle having a first level and a second level, a first electrode driving circuit which produces a reference voltage of a predetermined level in response to the control signal of the first level from the control circuit and which produces a first electrode driving signal corresponding to display data in response to the control signal of the second level from the control circuit, and a second electrode driving circuit which produces the reference voltage of the predetermined level in response to the control signal of the first level from the control circuit and which produces a second electrode driving signal in response to the control signal of the second level from the control circuit.

In accordance with the present invention, since the liquid driving voltage is periodically disabled according to control signals from the control circuit, the rms value of the liquid crystal driving voltage may effectively be adjusted.

This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figures 1 and 2 are a schematic plan view and a schematic sectional view of a prior art liquid crystal display unit, respectively; Figures 3A to 3C show the waveforms of the voltage signals applied to three row electrodes, respectively, of the liquid crystal display unit shown in Figures 1 and 2; Figures 4A to 4E show the waveforms of signals for explaining the mode of operation of the liquid crystal display unit shown in Figures 1 and 2; Figure 5 shows the relationship between the liquid crystal driving voltage and the display contrast at different temperatures;; Figure 6 shows a prior art liquid crystal driving circuit having a function to adjust the amplitude of the liquid crystal driving voltage to thereby adjust the rms value of the liquid crystal driving voltage; Figure 7 is a circuit diagram of a liquid crystal driving circuit according to an embodiment of the present invention; Figure 8 is a circuit diagram of a row driver used for the liquid crystal driving circuit shown in Figure 7; Figures 9A to 9E show the waveforms of signals for explaining the mode of operation of the row driver shown in Figure 8; Figure 10 is a circuit diagram of one of a plurality of column driving units in a column driver used for the liquid crystal driving circuit shown in Figure 7; Figures 11 A to 11 H show the waveforms of signals for explaining the basic operation of the liquid crystal driving circuit shown in Figure 7; and Figures 1 2A to 121 show the waveforms of signals for explaining the operation of the liquid crystal driving circuit shown in Figures 7, 8 and 10.

Figure 7 shows a liquid crystal driving circuit for driving a liquid crystal display unit 20 which has substantially the same construction as that shown in Figures 1 and 2. The liquid crystal driving circuit has a pulse generator 22 for generating a pulse signal having a frequency of 256 Hz, a frequency dividing circuit 24 having three series-connected 1/2 frequency dividers 24-1 to 24-3 to frequency divide the pulse signal from the pulse generator 22, and a column driver 26 for driving column electrodes (not shown) of the liquid crystal display unit 20 according to display data from a display data generator 28 in response to pulses from the frequency dividing circuit 24, and a row driver 30 for driving row electrodes (not shown) of the liquid crystal display unit 20 in response to pulses from the frequency dividing circuit 24.The liquid crystal driving circuit also has a duty-cycle control circuit 32 for controlling the duty cycle of output pulse signals from the row and column drivers 30 and 26. This duty-cycle control circuit 32 has an up-down counter 32-1 and switches 32-2 and 32-3 coupled to the up- and down-counting terminals of the up-down counter 32-1 for counting up or down the content of the counter 32-1 upon each operation. Output terminals C1 and C2 of the up-down counter 32-1 are coupled to first and second input terminals of an AND gate 32-4. A third input terminal of the AND gate 32-4 is coupled to an output terminal of an inverter 32-5 for inverting the pulse signal from the pulse generator 22.The second output terminal C2 of the counter 32-1 is coupled to one input terminal of an AND gate 32-6 whose other input terminal is coupled to an output terminal of an inverter 32-7 for inverting an output signal of the frequency divider 24-1. The first output terminal C1 of the counter 321 and the output terminals of the inverters 32-5 and 32-7 are coupled to input terminals of an AND gate 32-8. The output terminals of these AND gates 32-4, 32-6, and 32-8 are coupled to the row and column drivers 30 and 26 through an OR gate 32-9. When the output signal "1" is generated from the OR gate 32-9, the row and column drivers 30 and 26 set all of the column and row electrodes of the liquid crystal display unit 20 at the reference level, for example, OV.

Figure 8 shows a detailed circuit diagram of the row driver 30. Suppose that, in this example, the liquid crystal display unit 20 has two row electrodes, and the row driver 30 is so constructed as to drive these two row electrodes. The row driver 30 has NAND gates 40 to 42 for receiving at one input terminals thereof a control signal from the duty-cycle control circuit 32 through an inverter 43. The NAND gate 40 receives, at the other input terminal, a pulse signal of 64 Hz from the frequency divider 24-2. The NAND gate 41 receives, at the other input terminal, an inverted signal of the pulse signal of 32 Hz from the divider 24-3. The NAND gate 42 receives, at the other input terminal, an inverted signal of the pulse signal from the divider 24-2.The row divider 30 has p-channel MOS transistors 44 and 45 and n-channel MOS transistors 46 and 47 whose current paths are coupled in series between ground and a power source terminal V2E for receiving voltage 2E, p- and n-channel MOS transistors 48 and 49 each coupled between a power source terminal VE for receiving voltage E and a first row electrode 50; p-channel MOS transistors 51 and 52 and n-channel MOS transistors 53 and 54 whose current paths are coupled between the power source terminal V2E and ground; and p- and n-channel MOS transistors 55 and 56 each coupled between the power source terminal VE and a second row electrode 57. The gates of the MOS transistors 45, 46, 52 and 53 are commonly connected to the output terminal of the NAND gate 41.A junction between the MOS transistors 45 and 46 is coupled to the first row electrode 50, and a junction between the MOS transistor 52 and 53 is coupled to the second row electrode 57.

The output terminal of the NAND gate 40 is directly coupled to the gates of the MOS transistors 47 and 48, and is also coupled to the gates of the MOS transistors 44 and 49 through an inverter 58. The gates of the MOS transistors 54 and 55 are directly coupled to the output terminal of the NAND gate 42 which is also coupled to the gates of the MOS transistors 51 and 56 through an inverter 59.

According to the row driver 30 shown in Figure 8, when the output signal "1" is received from the control circuit 32, the signal "0" is applied to the NAND gates 40 to 42 through the inverter 43 to disable these NAND gates. Then, the output signal "1 " is generated from the NAND gates 40 to 42 to render the MOS transistors 44, 46, 47, 51, 53 and 54 conductive and to render the other MOS transistors nonconductive. Accordingly, the first and second row electrodes 50 and 57 are grounded.

When the output signal "0" is generated from the control circuit 32, the NAND gates 40 to 42 are all enabled to generate signals shown in Figures 9A to 9C. As has been described above, when the output signal "1" is generated from the NAND gates 40 and 41, the first row electrode 50 is grounded as shown in Figure 9D. When the output signal "1" is generated from the NAND gates 41 and 42, the second row electrode 57 is grounded as shown in Figure 9E. When the output signal "1" is generated from the NAND gate 41 and the output signal "0" is generated from the NAND gate 40, the MOS transistor 47 is rendered nonconductive and the MOS transistors 48 and 49 are rendered conductive so that the voltage E is applied to the first row electrode 50 as shown in Figure 9D.When the output signals "1" and "0" are generated from the NAND gates 41 and 42, respectively, the MOS transistor 54 is rendered nonconductive and the MOS transistors 55 and 56 are rendered conductive so that the voltage E is applied to the second row electrode 57 as shown in Figure 9E. When the output signal "0" is generated from the NAND gate 41, the MOS transistors 45 and 52 are rendered conductive. When the output signal "1" is generated from the NAND gate 40 under this condition, the MOS transistor 44 is rendered conductive and the voltage 2E is applied to the first row electrode 50 as shown in Figure 9D. When the output signal "0" is generated from the NAND gate 40, the MOS transistors 48 and 49 are rendered conductive, and the voltage E is applied to the first row electrode 50.When the output signal "1" is generated from the NAND gate 42 under this condition, the MOS transistor 51 is rendered conductive and the voltage 2E is applied to the second row electrode 57. When the output signal "0" is generated from the NAND gate 42, the MOS transistors 55 and 56 are rendered conductive and the voltage E is applied to the second row electrode 57 as,.own in Figure 9E.

Figure 10 shows one of the circuits in the column driving units which are respectively coupled to the column electrodes of the liquid crystal display unit 20. This column driving unit has AND gates 60 and 61 for receiving, at their one input terminals, display data DD1 and DD2, and a NOR gate 62 coupled to the output terminals of the AND gates 60 and 61. The AND gate 60 receives, at its other input terminal, an inverted signal of a pulse signal of 64 Hz from the divider 24-2, and the AND gate 61 receives, at its other input terminal, a pulse signal from the divider 24-2. An output terminal of the NOR gate 62 is coupled to one input terminal of a NAND gate 63 which receives at its other input terminal a pulse signal of 32 Hz from the divider 24-3.The output terminal of the NOR gate 62 is also coupled to an input terminal of an OR gate 64 for receiving the pulse signal from the divider 24-3. Output signals from the NAND gate 63 and the OR gate 64 are supplied to a NAND gate 65 together with an inverted signal of an output signal of the control circuit 32. An output signal of the NAND gate 65 is supplied to one of the plurality of column electrodes of the liquid crystal display unit 20 through an inverter 66. The column driver 26 has a column selection section for selectively biasing a plurality of column electrodes for selecting at least one of the column electrodes. Since the column selection is one that is well known, it is not shown here for simplicitv.

In accordance with the column driving unit shown in Fig. 10, when the output signal "1" is generated from the control circuit 32 or the frequency divider 24-3, the output signal "1" is generated from the NAND gate 65, and a voltage of OV is applied to the column electrode. A case will now be considered wherein the output signal "0" is generated from the divider 24-2. In this case, when the display data DD1 is "1", the output signal "1" is generated from the NAND gate 65, and a voltage of OV is applied to the column electrode. When the display data is "0", the output signals "1" and "0" are generated from the NAND gates 63 and 65 respectively while the output signal "1" is generated from the NOR gate 62 and the output signal "1" is generated from the divider 24-3.Then, a voltage of 2E is applied to the column electrode.

A case will now be described wherein the output signal "0" is generated from the control circuit 32, and the output signal "1" is generated from the divider 24-2. In this case, when the display data DD2 is "1", the output signal "1" is generated from the NAND gate 65 and a voltage of OV is applied to the column electrode. When the display data DD2 is "0", the output signal "1" is generated from the NOR gate 62, and a voltage of 2E is applied to the column electrode as has been described.Thus, the voltage 2E is applied either when the output signal from the control circuit 32, the output signal from the frequency divider 24-2, and the display data DD1 are all "0" and the output signal from the frequency divider 24-3, is "1 "; or when the output signal from the control circuit 32 and the display data DD2 are "0" and the output signal from the frequency dividers 24-2 and 24-3 are "1".

The mode of operation of the liquid crystal driving circuit shown in Figures 7, 8 and 10 will be described with reference to the waveforms of the signals shown in Figures 11 A to 11 H and 1 2A to 121.

Figures 11 A to 11 D show the waveforms of the pulse signal of 256 Hz from the pulse generator 22 and of the output pulse signals from the 1/2 frequency dividers 24-1 to 24-3. Figures 11 E to 11 H show the waveforms of the signals generated from the OR gate 32-9 when the output signals from the output terminals C1 and C2 of the up-down counter 32-1 are "0" and "0", "1 " and "0", "0" and "1 ", and "1" and "1", respectively. Assuming, for instance, that the output signals from the output terminals C1 and C2 of the up-down counter 32-1 are both "0". In this case, all the AND gates 32-4, 32-6 and 32-8 are disabled so that an output signal of OV level is generated from the OR gate 32-9 as shown in Figure 11 E. When the output signals "1" and "0" are generated from the output terminals C1 and C2, respectively of the counter 32-1 by operating the switch 32-2, the AND gates 32-4 and 32-6 are disabled and the AND gate 32-8 is enabled. Thus, an output signal of 25% duty-cycle and 128 Hz frequency is generated from the OR gate 32-9 as shown in Figure 11 F. When the output signals "0" and "1" are generated from the output terminals C1 and C2, respectively of the counter 32-1 by operating the switch 32-2, the AND gates 32-4 and 32-8 are disabled and the AND gate 32-6 is enabled. Thus, an inverted signal of the output signal of the frequency divider 24-1 as shown in Figure 11B, that is, an output signal of 50% duty cycle and 128 Hz frequency is generated.When both the output terminals C1 and C2 of the counter 32-1 are set at "1" by operating the switch 32-2, all the AND gates 32-4, 32-6 and 32-8 are enabled, and the signal shown in Figure 11 H, corresponding to the iogical product of an inverted signal of the pulse signal shown in Figure 11 A and the signal shown in Figure 11 G is generated.

When low level signals are consecutively generated from the OR gate 32-9, the row driver 30 generates a driving voltage as shown in Figure 12A of three levels 0, E and 2E as has been described with reference to Figures 9A to 9E.

When the content of the up-down counter 32-1 becomes "01" and a control signal of 25% duty cycle as shown in Figure 1 2B is generated from the duty-cycle control circuit 32, the driving signal from the row driver 30 is forcibly set to 0V level and has a waveform as shown in Figure 11 D while the control signal is at a high level. When the content of the up-down counter 32-1 becomes "10" and a control signal of 50% duty cycle as shown in Figure 12D is generated from the duty-cycle control circuit 32, the driving signal from the row driver 30 is forcibly set to 0V level and has a waveform as shown in Figure 12E while the control signal is at a high level.

Figure 12F shows an example of the column drive voltage generated from the column driving unit shown in Figure 9 when the control signal (Figure 11 F) of 25% duty-cycle is generated from the control circuit 32. Thus, a driving voltage as shown in Figure 12F is applied across the row electrode to which the row drive voltage shown in Figure. 1 2C is applied and the column electrode to which the column drive voltage shown in Figure 12F is applied.

Figure 12H shows the column drive voltage generated from the column driving unit of Figure 9 which has received the display data similar to that when the column drive voltage shown in Figure 12F is generated as the control signal of 50% duty-cycle is generated from the control circuit 32. Thus, a driving voltage as shown in Figure 121 is applied across the row electrode to which the row drive voltage shown in Figure 12E is applied and the column electrode to which the column drive voltage shown in Figure 12H is applied.

As may be apparent from Figures 12G and 121, the rms value of the liquid crystal driving voltage is controlled by varying the duty-cycle of the control signal from the control circuit 32. For instance, when the maximum and minimum rms values of the liquid crystal driving voltage obtained when the duty-cycle of this control signal is 0% are designated with by VMAX0 and VMIN0, the maximum and minimum rms valuesvMAxp and VMINP of the liquid crystal driving voltage obtained when the duty cycle of the control signal is P% may be given by the following equations:: 100-P,',,' VMAXP VMAXO (6) 100 1 OO-P, VMINP= VMINO (7) 100 As may be apparent from equations (6) and (7), the maximum and minimum rms valuesVMAxp and VMINP of the liquid crystal driving voltage may be varied by adjusting the duty-cycle of the control signal from the duty-cycle control circuit 32. It thus becomes possible to set the maximum rms value VMAXP to be larger than the lighting rms value VON at a given temperature and to set the minimum rms value VMINP to be smaller than the extinguishing rms value VOFF at this temperature.Furthermore, since it is possible to vary the rms value of the liquid crystal driving voltage, it is also possible to adjust the display contrast of the liquid crystal. It is to be noted that the adjustment of the rms value of the liquid crystal driving voltage is performed by periodically setting the driving voltages from the row and column drivers 30 and 26 at 0V in response to the control signals from the control circuit 32. Since the driving voltages from the row and column drivers 30 and 26 are digitally controlled, the liquid crystal driving circuit shown in Figure 7 may be so constructed as to consume less power.

Although the present invention has been described with reference to one of its preferred embodiments, the present invention is by no means limited to this embodiment. For example, instead of the up-down counter 32-1 and the switches 32-2 and 32-3 of the control circuit 32, it is possible to adopt a binary data generating circuit which has a keyboard for writing numerical data, a decoder for decoding the keyed-in data from the keyboard, and a register for storing the data from the decoder and for generating binary signals. Although control signals of four different duty-cycles are generated from the control circuit 32, it is possible to generate a signal of N bits from the counter 32-1 to generate control signals of 2N different duty-cycles from the control circuit 32.

Furthermore, the frequency of the output pulse signal from the pulse generator 22 need not be 256 Hz, but can be a pulse signal of a frequency higher than this frequency.

Although the row driver for driving two row electrodes is shown in Figure 8, it is easy to modify this row driver to drive three or more row electrodes.

Claims

1. A liquid crystal driving circuit comprising a control circuit which generates a control signal of variable duty-cycle and having a first level and a second level, display data generating means, a first electrode driving circuit which produces a reference voltage of a predetermined level in response to the control signal of the first level from said control circuit and which produces a first electrode driving signal corresponding to display data in response to the control signal of the second level from said control circuit, and a second electrode driving circuit which produces the reference voltage of said predetermined level in response to the control signal of the first level from said control circuit and which produces a second electrode driving signal in response to the control signal of the second level from said control circuit

2.A liquid crystal driving circuit according to claim 1, wherein said control circuit has a data input circuit which is manually operated, a register for storing bit data according to an input signal from said data input circuit, and a control signal generator which receives the bit data from said register to generate a control signal having a duty-cycle determined by the bit data.

3. A liquid crystal driving circuit according to claim 2, wherein said first and second electrode driving circuits each generate the electrode driving signal in response to pulses of predetermined frequencies and said control signal generator generates said control signals according to pulses of frequencies higher than said predetermined frequencies.

4. A liquid crystal display device comprising a liquid crystal display unit having liquid crystal, at least one first electrode arranged on one surface of said liquid crystal, and at least one second electrode arranged on the surface opposite to said one surface of said liquid crystal, display data generating means, a control circuit for generating control signal of variable duty-cycle and of first and second levels, and a driving circuit which sets said first and second electrodes at a predetermined potential in response to said control signal of said first level from said control circuit and which supplies driving signals corresponding to the display data to said first and second electrodes in response to the control signal of the second level from said control circuit.

5. A liquid crystal display device according to claim 4, wherein said control circuit has a data input circuit which is manually operated, a register for storing bit data according to an input signal from said data input circuit, and a second signal generator which receives the bit data from said register to generate a control signal having a duty-cycle determined by the bit data.

6. A liquid crystal display device according to claim 5, wherein said first and second electrode driving circuits each generate the electrode driving signal in response to pulses of predetermined frequencies and said control signal generator generates said control signals according to pulses of frequencies higher than said predetermined frequencies.

7. A liquid crystal driving circuit, substantially as hereinbefore described with reference to embodiment.