JPS5958856U - P-ROM writer - Google Patents
P-ROM writerInfo
- Publication number
- JPS5958856U JPS5958856U JP15133582U JP15133582U JPS5958856U JP S5958856 U JPS5958856 U JP S5958856U JP 15133582 U JP15133582 U JP 15133582U JP 15133582 U JP15133582 U JP 15133582U JP S5958856 U JPS5958856 U JP S5958856U
- Authority
- JP
- Japan
- Prior art keywords
- write
- circuit
- rom
- data
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
因は本考案の一実施例を示し、第１図は全体プロ゛シク
図、第２図は読出し書込み回路の構成を示すブロック図
である。 −
１・・・マイクロコンピュータ、２・・・読出し書込み
回路、３・・・Ｐ−ＲＯＭ、８・・・Ｉ１０アドレスデ
コーダ、１０・・・データ入出力回路、１１・・・リー
ドラインコントロール回路、１２・・・電源回路。。This figure shows one embodiment of the present invention; FIG. 1 is an overall process diagram, and FIG. 2 is a block diagram showing the configuration of a read/write circuit. - 1... Microcomputer, 2... Read/write circuit, 3... P-ROM, 8... I10 address decoder, 10... Data input/output circuit, 11... Read line control circuit, 12...Power supply circuit. .
Claims (1)
的に接続され、各読出し書込み回路にＰ−ＲＯＭが接続
され、前記各読出し書込み回路はＩ１０アドレスデコー
ダとデータ入出力回路゛とり一ドライトコントロール回
路とこれらを駆動する電源回路とから成り、Ｐ−ＲＯＭ
へのデータの書込みは、ＩＩＯアドレスデコーダにてマ
イクロコンビュ゛−夕がデータを送るべき書込み回路を
特定し、この特定された書込み回路内のデータ入出力回
路にて書込むべきデータをラッチし、書込み指令によっ
てリードライトコントロール回路がデータ入出力回路に
ラッチされたデータをＰ−ＲＯＭに書込むべくなされる
ことを特徴とするＰ−ＲＯＭライター。A plurality of read/write circuits are connected in parallel to a microcomputer, a P-ROM is connected to each read/write circuit, and each read/write circuit has an I10 address decoder, a data input/output circuit, a write control circuit, and a P-ROM. It consists of a power supply circuit that drives the P-ROM
To write data to the IIO address decoder, the microcomputer specifies the write circuit to which data should be sent, the data input/output circuit in the specified write circuit latches the data to be written, and A P-ROM writer characterized in that a read/write control circuit is configured to write data latched by a data input/output circuit to a P-ROM in response to a write command.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15133582U JPS5958856U (en) | 1982-10-02 | 1982-10-02 | P-ROM writer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15133582U JPS5958856U (en) | 1982-10-02 | 1982-10-02 | P-ROM writer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5958856U true JPS5958856U (en) | 1984-04-17 |
Family
ID=30335384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15133582U Pending JPS5958856U (en) | 1982-10-02 | 1982-10-02 | P-ROM writer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5958856U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5769593A (en) * | 1980-10-17 | 1982-04-28 | Advantest Corp | Write-in device of read only memory |
-
1982
- 1982-10-02 JP JP15133582U patent/JPS5958856U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5769593A (en) * | 1980-10-17 | 1982-04-28 | Advantest Corp | Write-in device of read only memory |
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