JPS5958839A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5958839A JPS5958839A JP57168902A JP16890282A JPS5958839A JP S5958839 A JPS5958839 A JP S5958839A JP 57168902 A JP57168902 A JP 57168902A JP 16890282 A JP16890282 A JP 16890282A JP S5958839 A JPS5958839 A JP S5958839A
- Authority
- JP
- Japan
- Prior art keywords
- fuse
- circuit
- output terminal
- power supply
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Read Only Memory (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 本発明は、回路素子を必要に応じて電気的に
接続したり、切断したシするためのヒユーズ回路を備え
た半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (a) The present invention relates to a semiconductor device including a fuse circuit for electrically connecting or disconnecting circuit elements as necessary.
（ｂ） 従来技術と間組点
第１図は従来のヒユーズ回路を示す図である〇その構成
は、８Ｉ！１図（ａ）に示すように゛電源ＶＩｔＶｆ間
にスイッチングトランジスタＱ□、抵抗Ｒ，ヒーーズＦ
が直列に接続されておシ、抵抗Ｒとヒ一ズＦの接続点が
出力端子ＯＵＴである。ヒユーズの切断は、出力端子Ｏ
ＵＴと電源７２間に電圧を与えてヒユーズに大電流を流
して溶断させている。ヒユーズ回路としては、原理的に
（儂スイッチングトランジスタＱ、は不要であるがヒユ
ーズＦが切断されずに接続されている回路においてはト
ランジスタＱ１がないと電源ＶＩ＋Ｖ！間を電流が流れ
続けて消費電力の増大をもたらす。従って、このような
ヒユーズ回路が組込まれた半導体装置がアクティブ状態
の時にはトランジスタＱ１のゲートＧに所定の電位を与
えてトランジスタＱＩｆｔオンとしてヒユーズＦの接続
、切断の状態を出力端子ＯＵＴから他の回路に伝え、一
方、半導体装置がスタンドバイ状態の時にはトランジス
タＱ１をオフとして電源Ｖ＊ｔＶｔ 間の電流路を断っ
ている。このような、いわゆるパワーダウンモードを採
用したヒユーズ回路においては、第１図（ｂ）に示すよ
うにヒユーズＦが接断されている場合、スタンドバイ時
にはトランジスタＱ、もオフとなっているため、出力端
子ＯＵＴはどの電源にも接続されていない状態、即ちフ
ローティング状態となる。(b) Prior art and assembly point Figure 1 shows a conventional fuse circuit. Its configuration is 8I! As shown in Figure 1 (a), a switching transistor Q□, a resistor R, and a heater F are connected between the power supply VItVf.
are connected in series, and the connection point between the resistor R and the fuse F is the output terminal OUT. To disconnect the fuse, use the output terminal O
A voltage is applied between the UT and the power source 72 to cause a large current to flow through the fuse and blow it out. As a fuse circuit, in principle (my switching transistor Q) is unnecessary, but in a circuit where fuse F is connected without being disconnected, if transistor Q1 is not present, current will continue to flow between the power supplies VI + V!, resulting in power consumption. Therefore, when a semiconductor device incorporating such a fuse circuit is in an active state, a predetermined potential is applied to the gate G of the transistor Q1, and the transistor QIft is turned on, and the connection/disconnection state of the fuse F is output to the output terminal. OUT to other circuits, and when the semiconductor device is in standby mode, the transistor Q1 is turned off to cut off the current path between the power supplies V*tVt. If fuse F is disconnected as shown in Figure 1(b), transistor Q is also off during standby, so output terminal OUT is not connected to any power source. That is, it becomes a floating state.
従って、出力端子ＯＵＴの電位は不安定な状態となり、
出力端子ＯＵＴに接続される回路を誤動作させてしまう
事態が生じる。Therefore, the potential of the output terminal OUT becomes unstable,
A situation may occur in which a circuit connected to the output terminal OUT malfunctions.
（ｃ） 発明の目的
本発明の目的は、従来のこのような欠点を解消し、スタ
ンドバイ時にもヒユーズ回路の出力端子の電位が安定と
なるようにすることにある。(c) Object of the Invention An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to make the potential of the output terminal of the fuse circuit stable even during standby.
（ｄ） 発明の構成
上記の目的を達成するための本発明は、第１および第２
の電源間にヒーーズ回路が接続され、該ヒユーズ回路は
該第１の電源に１端が接続された抵抗手段と、該抵抗手
段の他端に接続された出力端と、該他端と該第２の電源
間に接続されたヒユーズおよびスイッチング手段の直列
回路を備えたことを特徴とする。(d) Structure of the Invention The present invention for achieving the above object consists of the first and second
A fuse circuit is connected between the power supplies of the fuse circuit, and the fuse circuit includes a resistor means having one end connected to the first power supply, an output end connected to the other end of the resistor means, and a resistor means having one end connected to the first power supply, an output end connected to the other end of the resistor means, and a resistor means having one end connected to the first power supply, an output end connected to the other end of the resistor means, and a resistor means having one end connected to the first power supply. It is characterized by comprising a series circuit of a fuse and a switching means connected between two power supplies.
（ｅ） 発明の実施例
以下、本発明の一実施例を説明する。第２図は、本発明
の一実施例を示す図である。本実施例は抵抗網の構成を
決定するためにヒユーズ回路を用いた例である。(e) Embodiment of the Invention An embodiment of the invention will be described below. FIG. 2 is a diagram showing an embodiment of the present invention. This embodiment is an example in which a fuse circuit is used to determine the configuration of the resistor network.
第１図と同じ符号は同じものを示す。The same reference numerals as in FIG. 1 indicate the same things.
本発明によるヒユーズ回路は、一端が電源Ｖ。The fuse circuit according to the present invention has one end connected to the power supply V.
に接続された抵抗Ｒ，，Ｒ；の他端に出力端子が接続さ
れ、かつこの他端と電源Ｖ、との間にヒ一ズＦとスイッ
チングトランジスタＱ＋＋Ｑ＋’ｅ直列に接続した。An output terminal was connected to the other end of the resistor R, , R; and a fuse F and a switching transistor Q++Q+'e were connected in series between the other end and a power supply V.
従って右側のヒユーズ回路のようにヒユーズが切断され
ている場合でもスタンドバイ時において出力端子ＯＵＴ
は電源ｖＩによシ一定電位に維持され安定である。Therefore, even if the fuse is disconnected like in the fuse circuit on the right, the output terminal OUT is
is maintained at a constant potential by the power supply vI and is stable.
図においてＩＮＶ＋＋ ｌＮＶｔは夫々インバータ、
Ｑ、〜Ｑ、は夫々ｐチャネルトランジスタ、Ｒ１−Ｒ４
は抵抗網を構成する抵抗である０例えば左側のヒユーズ
が切断されていないヒユーズ回路ではアクティブ時にス
イッチングトランジスタＱ。In the figure, INV++ and lNVt are inverters,
Q, ~Q, are p-channel transistors, R1-R4, respectively.
is the resistance that constitutes the resistor network 0. For example, in a fuse circuit where the left fuse is not cut, the switching transistor Q is activated when it is active.
がオンとなるので出力端子ＯＵＴの電位は低レベル（例
えはＶ、＝−ＳＶ）となるのでトランジスタＱ！はオン
、その反転レベルがゲートに与えられるトランジスタＱ
、はオフとなシ、抵抗Ｒ３はトランジスタＱ！の左にあ
る図示しない回路に接続される。一方、右側のヒユーズ
回路ではヒユーズが切断されているので出力端子ＯＵ
Ｔは高レベル（例えばＶ、＝ＯＶ）となるので、トラン
ジスタＱ４がオン、Ｑａがオフとなシ、抵抗１（４はト
ランジスタＱ４ ｋ介して接地される。スタンドバイ時
も出力蕗）子ＯＵＴは高レベルであってこの状態が保持
される。is turned on, the potential of the output terminal OUT becomes a low level (for example, V, = -SV), so the transistor Q! is on, and the transistor Q whose inverted level is given to the gate
, is off, and resistor R3 is transistor Q! It is connected to the circuit (not shown) on the left side. On the other hand, in the fuse circuit on the right, the fuse is disconnected, so the output terminal OU
Since T is at a high level (for example, V, = OV), transistor Q4 is on and Qa is off, and resistor 1 (4 is grounded through transistor Q4k. Also output during standby) child OUT is at a high level and this state is maintained.
（ｆ） 発明の効果
本発明によればスタンドバイ時にヒユーズ回路の出力端
子が一定電位に維持されるのでヒユーズ回路に接続され
た回路の誤動作を防止することができる。(f) Effects of the Invention According to the present invention, since the output terminal of the fuse circuit is maintained at a constant potential during standby, malfunction of the circuit connected to the fuse circuit can be prevented.
第１図は従来のヒーーズ回路を下す図、第２図は、本発
明の一実施例を示す図である。
図において、Ｖ１＋Ｖ２ は第１．第２の電源、ＲＩ。
Ｒｒは抵抗、ＦはヒユーズＮＱＩＩＱ＋ はスイッチン
グトランジスタ、ｏｕｆｉ％出力峙；出力水す。FIG. 1 is a diagram showing a conventional heating circuit, and FIG. 2 is a diagram showing an embodiment of the present invention. In the figure, V1+V2 is the first. Second power source, RI. Rr is a resistor, F is a fuse, NQIIQ+ is a switching transistor, oufi% output voltage; output water voltage.
Claims (1)
れ、該ヒユーズ回路は該第１の電源に一端が接続された
抵抗手段と、該抵抗手段の他端に接続された出力端と、
該他端と該第２の電源間に接続されたヒユーズおよびス
イッチング手段の直列回路を備えたことを特徴とする半
導体装置。1st and 2nd '11! A fuse circuit is connected between the power sources, the fuse circuit having a resistor means having one end connected to the first power supply, an output end connected to the other end of the resistor means,
A semiconductor device comprising a series circuit of a fuse and switching means connected between the other end and the second power source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57168902A JPS5958839A (en) | 1982-09-28 | 1982-09-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57168902A JPS5958839A (en) | 1982-09-28 | 1982-09-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5958839A true JPS5958839A (en) | 1984-04-04 |
| JPH0454977B2 JPH0454977B2 (en) | 1992-09-01 |
Family
ID=15876675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57168902A Granted JPS5958839A (en) | 1982-09-28 | 1982-09-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5958839A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5372472A (en) * | 1976-12-08 | 1978-06-27 | Nec Corp | Semiconductor device |
| JPS5617059A (en) * | 1979-07-20 | 1981-02-18 | Fujitsu Ltd | Semiconductor switching element |
-
1982
- 1982-09-28 JP JP57168902A patent/JPS5958839A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5372472A (en) * | 1976-12-08 | 1978-06-27 | Nec Corp | Semiconductor device |
| JPS5617059A (en) * | 1979-07-20 | 1981-02-18 | Fujitsu Ltd | Semiconductor switching element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0454977B2 (en) | 1992-09-01 |
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