JPS595764A - Slicing circuit - Google Patents

Abstract

PURPOSE:To obtain invariably optimum slice levels even when the DC level of a signal varies, by providing two slice levels higher and lower than the center of the signal level and adjusting the slice levels automatically on the basis of the time width of a signal level exceeding the slice levels. CONSTITUTION:A video signal (V) is sliced by the 1st and the 2nd comparators 11 and 12 at the 1st and the 2nd slice levels E1 and E2 to obtain digital signals S1 and S2. On the other hand, a waveform between the 1st and the 2nd slice levels E1 and E2 is approximated to a trapezoidal waveform as shown in a figure and its center level C is found from Z1=h.(Y-W)/(Y-X), where (h) and W are predetermined and variables X and Y are found by the high-level periods of said signals S1 and S2. For this purpose, addition data from full-adding circuits 39 and 32 are used as address values to read specific data out of an ROM40 and this data is A/D-converted to supply a DC sliced voltage corresponding to the Z1 to the 1st slicing circuit as a reference voltage.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention, for example, in a text multiplex reception device, slices a received text multiplex signal and shapes the waveform into a transistor logic (hereinafter referred to as TTL) level signal. The present invention relates to a slice circuit suitable for circuits.

[Technical background of the invention]

For example, a text multiplex receiver is configured to slice a received text multiplex signal, waveform shape it into a TTL level signal, and then perform predetermined processing. In this case, the slicing level for slicing the text multiplex signal greatly affects the quality of the obtained TTL level text multiplex signal, so it is necessary to set the level at which the text multiplex signal can be sliced in the optimum condition at all times. It is desirable that there be.

By the way, conventional slice circuits have a configuration in which the slice level is fixed at a certain level in advance, but the slice level is determined by detecting whether the slice level is above or below the center of the amplitude of the character multiplexed signal. Character multiplex signal 1-4
Most of the configurations were such that the level was determined by raising and lowering each packet by a fixed amount, and determining the level by sending several packets.

[Problems with background technology]

However, the former configuration has the disadvantage that the slice level cannot be adjusted even when the amplitude level of the character multiplexed signal changes due to transmission characteristics or the like or when the DC level changes. In addition, in the latter case, determining the slice level requires information for the number of text multiplex signal packets, which takes time, and it is not possible to obtain a high-quality TTL level signal during the slice level determination period. There was a problem.

[Object of the Invention] - This invention was made to deal with the above-mentioned situation, and even if the amplitude level of the character multiplex signal or the DC level on which this character multiplex signal is carried varies for each packet, each of! An object of the present invention is to provide a slicing circuit that can appropriately adjust the slicing level for each packet.

[Summary of the invention]

Therefore, if this invention is explained in principle by looking at the entire circumference of FIGS. 3 to 6, for example, as shown in FIG. The digital signal S1+5tffi as shown in FIG. A trapezoidal diagram is assumed by linearly approximating the signals between the second slice levels El, E, and the digital signals S1, S! The time width y of the time period.

Taking advantage of the fact that X corresponds to the lengths of the lower and upper bases of the trapezoid, respectively, as shown in FIG.
, and the center (C), and obtain data for setting the third slice level located at the center (C).

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to all the drawings. FIG. 1 is a circuit diagram of one embodiment. In the figure,
Video signal (v) on which character multiplex signal (D) is superimposed If
i 1st. supplied to the second condensator 11.12;
The first one has different levels. Second slice level E
It is sliced by l+E2 and waveform-shaped into a TTL level signal. Each 1st. second slice level EIIE,
are given by variable resistance circuits 13 and 14. The output signal of the first comparator 1 is the AND circuit 1, respectively.
Sendering will take place on 5.16. Further, the output signal of the second converter tie 2 is digitized by an AND circuit 171.18. The sampling period in the AND circuits 15 to 18 is determined by the dart pulse G1. Also, the sampling pulse SP has a frequency of 6475f
8o (however, /IIc is the color subcarrier frequency), and among the AND circuits 15 to 18, the AND circuit 16.
The sampling pulse SP is connected to the inverter circuit 1 in Ill.
The signal is inverted at 9 and is supplied as a 100 kHz sampling signal. The output signals of AND circuits 15 and 16 are respectively counted by 6-bit counter circuits 20 and 21. The output signals of the AND circuits 17 and 18 are respectively counted by 5-pit power counter circuits 22 and 23. The details of each counter circuit 20 to 23 will be described later, but the dirt pulse G
, is reset by ijrus (R). 6 pit force counter circuit 20°21
The count output signal is output by AND circuits 24 to 31 as f-)
and is supplied to the 4-bit full adder circuit 32. The count output signals of the 5-bit power counter circuits 22 and 23 are gated by AND circuits 33 to 38, and then sent to the 4-bit full adder circuit 39.
supplied to The f-) pulse G2 supplied to AND circuits 24 to 31 and 33 to 38 is
−) z! This is a pulse output at the trailing edge of the pulse G.

The addition output signals of the full adder circuits 32 and 39 are sent to the ROM circuit 40.
supplied to The ROM circuit 40 is a full adder circuit 32.39
The slice level of the first contorter I is controlled based on the output signal of The analog signal is converted into an analog signal by a converter circuit A (referred to as an A conversion circuit), and is supplied to the variable resistance circuit 13. The resistance value of the variable resistance circuit 13 is controlled by a control signal converted into an analog signal,
Toreyo#) The slice level of the first comparator 11 is converted from the first slice level E1 to the third slice level described above.

The operation in the above configuration will be explained. FIG. 2(a) shows a character multiplex signal (D)' superimposed on a video signal (V). Of this character multiplex signal (D), CR is a clock line signal, and FC is a fleming code. Same figure (
b) is the reset pulse (
R) and is derived, for example, at the leading edge side of the clock line signal CR. FIG. 3(c) shows the gate pulse G1 supplied to the AND circuits 15-18. This dirt pulse c
m is derived over four cycles of the eight-cycle clock line signal CR. The figure (d) shows the AND circuits 24 to 31.
．． Supplied to 33-38) f-) /# Lus G! is derived at the trailing edge side of the gate pulse G1.

First, the video signal (V) is processed at the first slice level E 1 +
Sliced at E2. This first. The second slice level E1+E1 is a character multiplex signal (
They are set to be located above and below the center (C) of the amplitude level of D). For example, the first slice level E.

is set below the center (C), and the second slice level E! is set on p from the center (C). the result,
1st. The output signals of the second comparators IJ and 12 are respectively digital signals S1+81 whose duty ratio is not 1:1, as shown in FIG. 4(b) or (,). Among these digital signals S, , S, a portion corresponding to, for example, a high level for four periods of the clock line signal (frequency 415fsc) CR is processed by AND circuits 15 to 18 to a frequency of 6415/, C (-period is approximately 21.8nLee) sampling pulse SPK. In this case, in order to increase sampling accuracy, the digital signal S
1 is sampled by AND circuits 15 and 16 using sampling pulses sp and sp of positive phase and negative phase, respectively.

Digital signal S! Similarly, the sampling pulses sp and sp of positive phase and negative phase are sampled.

As a result, the digital signal 5IsS! are about 10.
9 It will be sampled in n5ec increments.

The data sampled by the positive phase sampling pulse SP of the sampling data of the digital signal S1 is 6
A bit counter circuit 2° counts the bits, and a 6-bit counter circuit 21 counts the bits sampled with a sampling pulse of opposite phase. Digital signal S.

Similarly, the sampling data for each is 5 bits.

It is counted by counter circuits 22 and 23.

By the way, one period of the clock line signal CR is approximately 350
Since it is n5ec, the period during which it becomes a rubel by slicing is about 175 n5ee, which is half of that.

Therefore, if the clock line signal CR is sliced at the center of its amplitude level and sampled with the sampling link pulse SP of frequency 6415f, (one period is approximately 21.8 n5ec), approximately 8 pulses per period of the clock line signal are generated. Sampling data is obtained, approximately 32 in 4 cycles.
sampling data can be obtained. Considering the above points, from each AND circuit IS, 16, slightly more sampling data than 32 is obtained during the generation period of the dirt pulse G1, and conversely, from each AND circuit 17 and 18, slightly less sampling data than 32 is obtained. can get. Therefore, the counter circuits 20-23 are 6-bit, 5-pin, and 6-bit counter circuits, respectively, so that they can sufficiently count the sampling data output from the corresponding AND circuits 15-8.

The count outputs of each 6-bit counter circuit 20, 21 are added by a full adder circuit 32. 5 bits each, counter circuit 2
The count outputs of 2.23 are added by a full adder circuit 39. In this case, the AND circuits 15 to 18 sample the clock line signal CR for four periods to provide an integral effect, so the data of the lower two bits of each counter circuit 20 to 23 is Discard and add the data of the upper 4 bits, 3 pins, and
We are trying to supply this to the world. As a result, the count outputs supplied to each of the counter circuits 20 to 23 and the corresponding full adder circuits 32 and 39 are almost unaffected by noise.

The addition output signal of each full adder circuit 32.39 is the ROM circuit 4.
The address data will be 0. The ROM circuit 40 stores 8 bits of data for each address. and,
The data stored at the address specified by the address data described above is converted into an analog signal by the D/A conversion circuit 41 and supplied to the variable resistance circuit 13. The resistance value of the variable resistance circuit 13 is controlled by a signal supplied from the D/A conversion circuit 41, and the resistance value of the variable resistance circuit 13 is controlled by the signal supplied from the D/A conversion circuit 41.
1, the center (C) of the amplitude level of the character multiplex signal (D)
) is set.

Here, each address of the ROM circuit 40 and the control data stored in the address will be explained. As shown in FIG. 3, character multiplex signal CD>f: 1st. Second
slice level El.

E! When sliced at , the signal in between can be regarded as a sufficiently linear signal. By linearly approximating the signals in this way, the character multiplex signal (D) and the first . It can be considered as a partial trapezoid surrounded by the second slice level E1rE1. The length of the upper base of the trapezoid shown in FIG. Corresponds to the width. Further, the height h) corresponds to the potential difference between the first slice level Et and the slice level Ex of m2. Also, 1st. Second
The center (C) of the amplitude level of the clock line signal CR exists between the slice level E11E, and the time width of the center (C) within the trapezoid is equal to the time width of half a cycle of the clock line signal CR. Equivalent to. Further, in the figure, Zl indicates the distance between the first slice level E1 and the center (C), and corresponds to the potential difference between the two. If you know this value of 21, then the center of the amplitude level of the black and white signal CR (
A third slice level located at C) can be set.

Now, if this zl is expressed by the formula using X*Yehew't-, it becomes as follows. First, the lengths of each part of the triangle shown by diagonal lines on the left side of FIG. 5 are set as shown on the right side. Then, according to the triangle similarity condition, the following proportional equation (1) holds true.

t': (yX)/2=(hZl
) : h ・・=−・・(0 equation (1), then the following equation (2
) holds true.

vh=(h-Zt)・,(y-x)/2・−
. . . (2) From equation (2), ν is expressed as in the following equation (3).

v=(h −zt )(y x)/2h ・−−
-(3) Also, ν satisfies the following equation (4).

2 tl + x = w...
Song/Song (4) Equations (3) and (4) When F)v is eliminated, the following equation (5) holds true.

(w-x)/2=(h-Zx)・(yx)/
2h ---(5) Equation (5) 'k When solved for Z t, Z s is expressed by n-dimensional equation (6).

Zs=h・(y-w)/(y-x) Song (6
) In addition, )1, vg W HX * F IZ
The dimensions of 1 are assumed to be equal.

In equation (6), h and w are predetermined values. Also, X and 7 are respectively second. The high level of the first digital signal 5xtSH also corresponds to the count value of the sampling data, and can be regarded as the addition data of the 4-bit addition circuits 39 and 32, respectively.

Therefore, in the ROM circuit 4o, a full adder circuit 32.
By the way, each address of the ROM circuit 40 corresponds to the potential difference between the first slice level E1 and the second slice level E2. Corresponds to each division level when divided into multiple parts. If it is divided into (n-1) pieces, the division level is 1st. There is one slice level including the second slice level E1+E1, and there are n addresses. and,
For example, the first slice level E! corresponds to the first address, and the second slice level corresponds to the nth address. In this case, the data stored at each address consists of 8 bits, and the first slice level E,
The first address corresponding to
0000000 (hex.

O) is stored, and 8-bit data 111111 is stored at the nth address corresponding to the second slice level E.
11 are stored. Therefore, the first slice level E* and the slice level E of lL2! The potential difference between b and b is divided into 28-1=255 parts.
The number n of addresses of the RoM circuit 4o is set to 256. The ROM circuit 40 is a full adder circuit 32.39.
A predetermined address z1t- is designated from among the 256 addresses based on the added data, and the data stored at that address is supplied to the variable resistance circuit 13 via the D/A conversion circuit 41 as a control signal.

A predetermined address is designated according to the above-mentioned addition data whose contents differ depending on the amplitude level or DC level of the character multiplex signal (D). If data that allows the slice level of the first converter 11 to be set to the third slice level is stored at each address as different data depending on the content of the addition data, the 1 Contourator 11 slice level?
It can be set to slice level #3.

In this way, by setting the slice level of the first converter/lator 11 to the third slice level, the output signal of the first converter/lator 11 can be obtained as the output signal of the slice circuit. can.

As described above, according to this embodiment, the third slice level is set at the center (C) of the amplitude level of the character multiplex signal (D) during the period of the black and Klein signals CR of the character multiplex signal (D). Therefore, even if the amplitude level or DC level of the character multiplex signal varies, it is possible to always slice the character multiplex signal in an optimal state for each packet.

Note that the present invention is not limited to the above embodiments. For example, in the previous embodiment, the third slice level was set by detecting the value zl shown in FIG. 5;

It may be set by detecting a value. In this case, Zl is expressed by the following equation (7) using h*W e X Hy.

z*=h・(w-:t)/(y-x) Listen-song (
7) In addition, the configuration is not limited to the configuration in which the calculation result shown by equation (6) or (7) is set in advance in the ROM circuit 4o.
The configuration may be such that the calculation is performed using an arithmetic circuit that performs sequential calculations.

Furthermore, if the above-mentioned time width X + y is known, the center (C)'t- can be detected using various methods. Of course, the present invention is not limited to a configuration that outputs control data in accordance with arithmetic operations.

Furthermore, it goes without saying that the present invention is applicable to circuits other than slicing circuits for character multiplexed signals.

〔Effect of the invention〕

As described above, according to the present invention, even if the amplitude level of the character multiplex signal or the DC level on which the character multiplex signal is carried varies for each packet, the slice level can be adjusted appropriately for each packet. A slice circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the slice circuit according to the present invention, FIGS. 2(,) to (d) are signal waveform diagrams showing signals of each part of the circuit shown in FIG. 1, and FIG. 1st. Signal waveform diagram for explaining the second slice level, Fig. 4(a)
, (b) is the first. FIGS. 5 and 6 are signal waveform diagrams showing digital signals obtained by slicing the character multiplex signal at the second slice level, and are diagrams for explaining the operation of the circuit shown in FIG. 1. 11...First conno arm lever, 12...12 (7
): 1 amparator, 13.14...variable resistance circuit, 1
5-18.24-31.33-38...AND circuit,
20.21...6-bit counter circuit, 22°23.
...5-bit power counter circuit, 32.39...4-bit full adder circuit, 40...ROM circuit, 41...D/A
conversion circuit. Applicant's agent Patent attorney Takehiko Suzue 2nd drawing 3rd figure 4th figure 5th figure 325-

Claims (2)

[Claims] (1) a first slicing means for slicing an input signal at a first slice level located below the center of its amplitude level and converting the input signal into a first digital signal; a second slicing means for slicing at a second slicing level located above and converting the signal into a second digital signal; a time width detection means for detecting the time width of a high level period or a low level period of a second digital signal; A slice circuit comprising third slice level setting data output means for outputting data for setting a third slice level located at the center of the amplitude level of a signal. (2) The third slice level setting data output means is the first slice level setting data output means. The input signal between the second slice levels is approximated by a straight line, and the first slice level of the time width detection means is approximated by a straight line. 2. The slice circuit according to claim 1, further comprising calculation means for calculating the following equation (A) or (B) based on the time width detection result of the second digital signal. 21 =h・(y-w)/(y-X)・・・・・・・・・・
・・・・・・・・・・・・・・・(4) 2 laziness = h・(w
-x)/(y-x)・・・・・・・・・・・・・・・・
・・・・・・・・・(B)