KR970017445A

KR970017445A - Control Signal Duty Decision Circuit for VCR Tape

Info

Publication number: KR970017445A
Application number: KR1019950031376A
Authority: KR
Inventors: 김경환
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-09-22
Filing date: 1995-09-22
Publication date: 1997-04-30

Abstract

본 발명은 VCR용 비디오 카세트 테이프에 NTSC, PAL 방식으로 노멀, 비스 마크와 와이드 방식의 노멀 및 비스 마크 방식에 맞도록 소정 듀티로 기록된 콘트롤 펄스 신호를 판정하여 기록 타입을 알도록 하기 위해서, 콘트롤 펄스 신호의 상승 에지를 검출하여 1/fsc 폭의 단발 신호를 출력하는 수단과, 소정 듀티에 대응하여 상기 fcs를 분주한 신호를 클럭으로 하여, 콘트롤 펄스의 하이(로우) 레벨 구간 동안 인에이블되어 업(다운) 카운팅하는 다수의 카운터와, 카운터의 최상위 비트값을 입력으로 하며, 1/fsc 폭의 단발 신호를 클럭으로 하며, 카운터 마다 접속된 다수의 래치 및 다수의 래치 각각의 출력을 XOR 논리를 행하는 XOR 게이트로 구성되어 정상 속도 및 고속 탐색 배속에서도 테이프 타입을 판정하게 한 회로에 관한 것이다.According to the present invention, a control pulse signal recorded at a predetermined duty to fit a normal, bis-mark, and wide-type normal and bis-mark system in a NTSC, PAL method on a VCR video cassette tape is used to determine a recording type. Means for detecting a rising edge of the pulse signal and outputting a single signal having a width of 1 / fsc, and a signal obtained by dividing the fcs corresponding to a predetermined duty as a clock, and being enabled during the high (low) level period of the control pulse. A number of counters counting up and down, the most significant bit value of the counter is input, and a single signal having a width of 1 / fsc is used as a clock. And a circuit configured to determine a tape type even at a normal speed and a high speed search double speed.

Description

Control Signal Duty Decision Circuit for VCR Tape

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 VCR 테이프의 콘트롤 신호 듀티 판정 회로.1 is a control signal duty determination circuit of a VCR tape according to the present invention.

Claims

Means for detecting a rising edge of a control pulse signal recorded at a predetermined duty of a video cassette tape for VSI and outputting a single signal having a width of 1 / fsc; using a clock signal that divides the fcs corresponding to the predetermined duty, A plurality of counters enabled and counting up (down) during the high (low) level period of the control pulse; A plurality of latches inputted between the most significant bits of the counter, a single signal having a width of 1 / fsc as a clock, and connected to each counter; And an XOR gate for performing XOR logic on the output of each of the plurality of latches, so that a predetermined duty is determined by the gate output.

2. The control signal duty determination circuit of claim 1, wherein the predetermined duty is a duty ratio according to normal and vis marks for NTSC and PAL, and normal and vis marks for wide vision.

2. The control signal duty determination circuit of claim 1, wherein the control signal is a pulse formed by amplifying the signal output from the control head of the video cassette recorder and through a Schmitt trigger means.

2. The counter of claim 1, wherein the counter comprises: a first counter for up clocking and down clicking fsc / 5 and fsc / 5, respectively; and a third counter including fsc / 4 and fsc / 6 as the up clock and the down clock, respectively.

2. The control signal duty determination circuit of claim 1, wherein each of said plurality of latches is comprised of a D-type flip flop.

※ Note: The disclosure is based on the initial application.