JPS5957547A - Data control system - Google Patents

Abstract

PURPOSE:To attain plural input data into a series of outut data, by combining moduled logical units in multi-stage. CONSTITUTION:Modules BLK1, BLK3 of four logical blocks BLK1-BLK4 are connected to a module 10A and the BLK2, BLK4 are connected to a module 10B, respectively. The modules 10A, 10B are connected to a module C. The modules 10A-10C are set initially, and when a ready input is fed to the module 10C, a ready output is fed to the module 10A. The module 10A supplies a ready output to the BLK1 and receives an acknowledgement input from the BLK1, then an acknowledgement output is fed to the module 10C after a data is set to a register. The 10C transmits the acknowledgement output to a receiving side after the data is set to the register. The receiving side reads the data, transmits the next ready signal to the module 10C, and the 10C transmits a ready signal to the 10B. Similarly, the data of the blocks BLK1-BLK4 is transmitted to the receiving side.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a data control method that combines data from a plurality of logical blocks into a series of data.

(2) Prior art and problems In general, in data transfer, it is often required to transmit data from multiple data sources in a time-sharing manner in one transmission system. Consider the case where data from four logic processors is output as a series of data so that Conventionally, in such a case, the data from the four logic blocks BLKO to BL'K3 are manually input to the selector circuit SEL and compiled into a series of data according to the order determined by the selection signal formed by the counter ONT or the like. Output. By the way, when the data from each logic block is output in 8 bits in parallel, the data input to the selector only requires 3 terminals.
There will be two. Therefore, the system shown in Figure 1 can be integrated into one LSI.
It is difficult to accommodate on a chip.

Furthermore, when the number of input logic blocks increases, it is necessary to perform a new circuit design in accordance with the increase.

(3) Purpose of the Invention In view of the above-mentioned problem, the purpose of the invention is to convert data from two clocks into one output data in data control that reduces data from multiple logical blocks to a series of data. By comparing the device that stops people with Mosinir,
Provides a data control method that allows data in two logical blocks to be combined into one piece of data, and by gradually combining the two pieces of data into one piece of data, the data can be finally combined into one piece of data. It's about doing.

(4) Structure of the Invention In the present invention, a plurality of logical units having the same structure are combined in multiple stages to alternately select and output one set of output data from two sets of human data. A data control method that collects input data from logic blocks into a series of data that is selectively output in a certain order, the logic unit having two sets of input data terminals and one set of output data terminals. , one ready input terminal, two ready output terminals, two acknowledge input terminals, one acknowledge output terminal, and a reset input terminal, and the logic unit at each stage receives the ready input from the logic unit at the succeeding stage. A data control scheme is provided that is configured to receive and selectively output human data from two preceding logical units.

(5) Embodiment of the Invention A data control system as an embodiment of the invention will be described below with reference to the drawings.

FIG. 2 shows the data control system used in the present invention.
This is an example of the configuration of a logical unit (module) that combines two input data into one output data.
2 shows its internal circuit, and (B) shows only its input and output terminals. The circuit in FIG. 2(g) is an AND (NAND) gate circuit 11, 12, 13, 14. ! ,
7. I8, 19, 22, latch circuit 15.16, 20.
It consists of 21.

In the circuit of Fig. 2 (4), READY from outside
Select (SEL) latch circuit 2 in the module based on the logic of the IN signal and AOK-IN1/AOK=IN2 signal
0 and the clock signal of the data (DATA) register circuit 21 is enabled. This enable clock signal causes the output of the select latch circuit 20 to be inverted and the manual data to be set in the register circuit 21. Select latch circuit 20Q, data and hCr<・I
N1/AOK/IN2 human power selection and REA]
) Select all outputs of Y-OtJ'l'.

In this way, the select launch circuit 20 is a control latch for selecting data and control signals.
Initialized by ESgT signal.

Although only 1 bit of data is shown in the first figure, it is also possible to input 8 bits in parallel, for example. Such a module 10 is an I-chip LS
It can be configured as I.

The module 10 has input/output terminals as shown in FIG. 2(B), namely, ready (R, EADY) input/output, acknowledge (AOK) input/output, data (DATA).
) input/output and reset ()l, ESET) input terminals. Figure 3 shows the selection of data input, acknowledge input, and ready output in the circuit shown in Figure A1.

Next, using three modules 10 shown in FIG.
A method of combining data from one logical block into a series of data will be explained using FIG.

As shown in FIG. 4(A), four logical blocks B
Among LK 1-BLK・4, 13LK・1 and BLK・
3 is connected to module IOA, B L K 2 and B
LK.4 is connected to module IOB. Module 10A and IOB are connected to module 100.

Initially, the three modules IOA, 10B, . . . 100 are initialized by a reset signal. If a ready input is given to the module 100 from the data receiving side in this state, the module 10A
Ready output is sent to

The module IOA receives the ready output from the module 100 and puts the ready output into the logic block BLK・1.
When it receives the acknowledge input from the logic block BLK.1, it sets it in the chitake register and then sends the acknowledge output to the module 100. When module 100 receives an acknowledge input from module IOA, it sets data in a register and then sends an acknowledge output to the receiving side. On the receiving side, upon receiving the acknowledge signal from module 100, it reads the data and sends the next ready signal to module 10C. Mojir 100 is
This time, a ready signal is sent to module 10B. Thereafter, data from block BLK-2 is sent to the receiving side by the same operation as described above. Thereafter, in the same manner, as shown in Figure 4 (B), the logical blocks BLK1. B.L.K.
2. BLK・3. Data is received in the order of BLK・4 111
Sent to II.

(6) Effect between lights According to the present invention, a data control method is provided that can combine multiple input data into a series of output data by combining modular logic units in multiple stages. It can be done.

[Brief explanation of drawings]

Figure 1 shows a conventional data control method, and Figure 2 (
A) and (B) are diagrams showing the circuit and input/output terminals of the logic unit used in the data control method according to the present invention, FIG. 3 is a diagram showing the operation timing of the logic unit in FIG. 2, and FIG. 2) and (B) are diagrams showing a data control method according to the present invention using the logical unit structure of FIG. 2. (Explanation of symbols) 10: Logical unit (module), 11.12゜13
．． 14, 17, 18, 19, 20: AND gate circuit, 15, 16, 20, 21: latch circuit. Patent applicant Fujitsu Limited Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney 1) Yukio Patent attorney Akira Yamaguchi

Claims (1)

[Claims] By combining logic units with the same configuration in multiple stages that alternately select and output one set of input data from two sets of input data, input data from multiple logic blocks can be output in a fixed order. A data control method that collects data into a series of data that is selectively output,
The logic unit includes two sets of manual data terminals, one set of output data terminals, one ready input terminal, two ready output terminals, two acknowledge input terminals, one acknowledge occupation terminal, one acknowledge output terminal, and,
The data control device has a reset input terminal, and the logic units in each stage are configured to selectively output the input data from the two logic units in the previous stage in response to ready input from the storage unit in the latter stage. method.