JPS5957339A - Register control circuit - Google Patents

Abstract

PURPOSE:To leave the result of shift of the content of a register in a single processing unit by making to update the contents of a pointer with an output of an adder, in a register control circuit of a data processor. CONSTITUTION:In storing a data in a register 31, a data is fetched from a bus 36, and the contents of a pointer 33 representing the location of the uppermost order bit of the register 31 is reset by using a reset signal 39. When shifting the contents of the register 31, an external shift constant 37 and the contents of the pointer 33 are added with an adder 34, the result in written in the pointer 33 and inputted to a decoder 35. The decoder 35 decodes the result of the adder 34 and outputs it to a barrel shifter circuit 32 as a shift control signal 38. Further, the contents of the register 31 is inputted to the barrel shifter circuit 32 and outputted on a bus 36 according to the shift control signal 38.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a register control circuit for an IJ data processing device.

Conventional 4111 configuration and its problems Conventionally, operations such as bit shifting of data have been frequently used in data processing devices. Figures 1 and 2 below
A conventional shift circuit will be explained with reference to the drawings.

FIG. 1 shows a smaller version of a conventional shift register circuit.

In FIG. 1, Qv is a flip-flop that stores data bits, and each has the same structure. In the above configuration, when LOAD>JLOAD becomes active, DI. The contents of the signal line ~IJIn are taken in parallel to the flip-flop 0υ, and the contents are output to the signal line DOG ~DO11. Next, when a positive pulse is applied to the shift signal 5111FT (a negative pulse to 5IIIFT), the data bits east of each flip-flop are moved to the next flip-flop.

However, in the above configuration, only the data bits can be shifted by one pulse of the shift signal. Therefore, in order to shift any data bit, the shift signal must be changed. It had the disadvantage that it had to be applied to several fit shift registers and required multiple processing units.

FIG. 2 shows a conventional barrel shifter circuit. This is a skewer
It is possible to shift an arbitrary number of bits in units of processing. ? V
is a register that stores data, and @ is a barrel shifter that shifts input data by a given shift constant and outputs it. In the above configuration, when shifting data stored in register e, the contents of the register are output, and a shift constant is given to barrel shifter □. The barrel shifter receives the output of the register &IJ as input, shifts an arbitrary number of pits according to the shift period, and outputs the result.

However, in the above configuration, in order to preserve the result of shifting the contents of the register, the output of the barrel shifter must be set in the register again, and the two processing units M? It has the disadvantage of =a (7).

Effects of the Invention The present invention addresses the drawbacks mentioned above and provides register control by shifting the register's valley by an arbitrary number of bits during a single process (1'l) and leaving the shifted result in the register. It is intended to provide a circuit 7Il-Llu.

Structure of the Invention In order to achieve the above object, the present invention provides a register for storing data, a pointer for reducing the position of the most significant bit of the register, and a P' valley of the register by hand. A barrel shifter that shifts an arbitrary number of bits and outputs it to outside i', ls, an adder that adds the shift constant to be shifted and the contents of the above pointer, and the output of the above adder is decoded and shifted to the above shifter. It has a decoder that outputs IBI control number 11, and is configured to read the contents of the above pointer by the output of the second correction device.

Saraniki's invention is a register that stores one-word data.

A pointer indicating the position of the most significant bit of the above register,
A bidirectional barrel shifter that takes the contents of the above register as input and outputs it to the outside by shifting an arbitrary number of bits, and at the same time shifts the external data by an arbitrary number of bits and outputs it to the above register, and adds the shift constant to be shifted and the contents of the above pointer. with an adder.

A decoder decodes the output of the adder and outputs a shift control signal to the barrel shifter 1.

The content of the pointer is updated by the output of the adder.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 8th
The figure shows the configuration of a register control lri circuit in one embodiment of the present invention, which is a circuit that handles 4-bit data.

In FIG. 8, $11> is a register, 2) is a barrel shifter, and 1 or more have the same configuration as in FIG. 2.

trowel is a pointer, 0ψ is an adder, ni) is a decoder, ni) is a bus, @ is a shift constant, (to) is a shift control signal, (2
) is a reset signal.

The dw operation of the register control circuit configured as described above will be explained below. First, when storing data in the register 60, the data is fetched from the bus) and at the same time, the contents of the pointer 03, which decrements the position of the most significant bit of the register 9υ, are reset using the reset itr signal. Next, shift the hu in register 6■, add the shift constant 90 from the first part and the pointer 6 2> =
# Add with ＼ and put the result in the pointer,
and input it to the decoder ■. The decoder 轡 decodes the result of the adder ■.

Output to the barrel shifter as a shift control signal (7). Then, the contents of register C(1) are input to the barrel shifter so, and according to the shift control signal (to), the contents of register C(1) are input to the bus G+13.
Output to.

According to this embodiment, by adding the inner valley of the pointer indicating the position of the most significant bit of the register and the shift constant,
The contents of a register can be shifted by an arbitrary number of bits,
Moreover, it is possible to have the effect of leaving the shifted result in the register 6υ, and the operation is completed in a single processing unit.

Next, another embodiment of the present invention will be described based on the drawings. FIG. 4 shows a circuit in which the configuration of the register control circuit in one embodiment of the present invention is reduced and handles 4-bit data.

In FIG. 4, OD is a register, 0. Eyes, Po-f-nta.

fl, I is JJII yA g+ 1) is a decoder,
11 is the bus, -ka is the shift constant, and ) is the shift control 4
No. 4, - is reset 1 dl, and 1 or more have the same configuration as in Figure 611a. (The boundary is the barrel shifter between the two sides.

The operation of the register control circuit configured as described above will be explained below. Saizu, system reset I.
(at the same time as the reset signal), resets the inner part of the pointer Sakaki indicating the upper bit of the register OD. Next, when storing data in the register ha, input the data from the bus +Mj to the barrel shifter (1'4).Then, according to the shift control signal section, shift the data from the bus (-),
Write data to register 0]). If you want to shift the inner valley of register Uυ.

The operation is similar to that of the embodiment shown in FIG.

According to this embodiment, it is possible to shift the data by 1J bits by leaving the inner register, and to have the result stored in the register, thereby completing the first 11 operations in the middle of a single process.

Effects of the Invention As described above, according to the present invention, the voltage on 7+V (f
By holding the pointer that indicates 4<t-tfffl of the f bits and the adder that adds the V'valley and the shift constant.

In the 11th process of Kushi-, it is possible to shift f1 in the register by (El]h bits and leave the stored value 1↓ in the register, which has a great practical effect.

[BRIEF DESCRIPTION OF THE DRAWINGS] Figure 161 is a conventional shift register circuit diagram, Figure 2 is a conventional barrel shifter circuit diagram, and Figures 8 and 1 are block diagrams of an embodiment of the present invention. . ciuυ...Register, (9)@4...Barrel shifter, GK+ 411...Pointer, C'(HJ...
・Adder, in)--Decoder, in...Bus, @1
θ...Shift constant, 01dl...Shift control signal,
C31) -...Sulet Signal Agent Yoshihiro Moriki Figure 2 Figure 3

Claims (1)

[Scope of Claims] 1-1 A register that contains data 91'M, and a pointer that indicates the position of the general bit of the register. A barrel shifter that takes the contents of the above register as input, shifts the work bin, and outputs it to the outside. It has an adder that adds the shift constant to be shifted and the contents of the pointer, and a decoder that decodes the output of the adder 1 and outputs a shift control signal to the barrel shifter L, and The register control circuit 0 is characterized in that the contents are updated by the output of the adder.21 A register for storing the edict data, and a pointer that overrides the position of the inno bit at the top of the register. A bidirectional barrel shifter that takes input, shifts arbitrary bits, outputs it to the outside, and simultaneously shifts external data by an arbitrary number of bits and outputs it to the upper fftj register, and an adder that adds the shift constant to be shifted and the contents of the above pointer. and a decoder that decodes the output of the adder and outputs shift control 1g13 to the barrel shifter, and the content of the pointer is updated by the output of the adder described in [1]. register control circuit.