JPS5956771A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive to form at high withstand voltage by dispersing the field concentration at a drain or source diffused layer end part at two points by a method wherein a channel part and the insulation film thereon are formed by self-alignment, and a gate electrode and the source and drain diffused layers are formed by self-alignment. CONSTITUTION:An SiO2 film 17 and an Si3N4 film 18 are formed on a P type Si substrate 11, and then the Si3N4 film 18 is left only at a fixed part. A diffused layer 13 is formed by implanting P<+> ions with the Si3N4 mask 18 as the mask. An SiO2 film 19 is formed on the layer 13 by exposing the substrate to an oxidizing atmosphere, and an SiO2 film 20, an Si3N4 film 21, and a polycrystalline film 22 which are available for tunnel are successively deposited after removing the Si3N4 film 18 and the SiO2 film 17 under the film 18. After removing the films 20, 21, and 20 by being left to the position of overlaying the layer 13, the P<+> ions are implanted into the surface of the substrate with the left polycrystalline Si film 22 as the mask, resulting in the formation of a diffused layer 12.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device (JS type 716 conductor device) and a manufacturing method thereof, and particularly relates to an MNO3 element and a manufacturing method thereof.

Typical structures conventionally known in MIS type semiconductor devices are shown in FIG. 1 [a+ to te+].

In each figure, the same reference numerals represent the same or equivalent parts, l is the substrate, 2 is the source, train, 3 is the low concentration diffusion layer, 4 is the insulating film, 5 is the gate electrode, and 6 is the electrode/wiring. .

Figure 1 fal is a 4'i/i structure in which the gate, source, and drain diffusion regions are formed in a self-aligned manner, represented by a polycrystalline S] gate, and (1)) is an M-1/i structure. This is a structure in which the gate I, the source, and the drain overlap with each other with an insulating film interposed therebetween. fcl has a double diffusion structure, [dl
□ has an offset cable structure, and both of them are made of a transistor which increases the withstand voltage of the source and drain.

TEL has a structure in which the gate electrode is drawn out to the drain, and has recently been proposed for the purpose of increasing the breakdown voltage.

Most of these elements with conventional structures are
The source and drain portions have a relatively low breakdown voltage, making them difficult to use in devices that use large voltages. Furthermore, those with a structure that increases the withstand voltage have the disadvantage that they are unsuitable for high integration.

The first object of the present invention is to solve the disadvantages mentioned in -1-1, to be suitable for high integration, and to have a source and a train with high durability.
An object of the present invention is to provide an IS type semiconductor device. Another object of the present invention is to use the semiconductor device as an MNO8 element to realize a byte-erasable nonvolatile memory.

FIG. 2 is a schematic cross-sectional view showing the main structure of the semiconductor device of the present invention developed to achieve the objective 171. The semiconductor device of the present invention is basically a structure in which the above-described conventional element is made more efficient and has a higher durability, and is also suitable for higher integration. In the figure, 11 is a substrate, 12 is a source having a conductivity type opposite to that of the substrate, a train diffusion layer, and 3 is a source.

A diffusion layer having the same conductivity type as the drain diffusion layer and having an impurity concentration equal to or lower than that, 14 an insulating film, 15 a gate electrode, ]6
is an insulating film (first insulating film). In this structure 1,
The channel part (or layer 1:3 of the expansion layer 11) and this relatively thin insulating film 16 are formed in self-alignment, and the gate electrode 15 and the source and train diffusion layers 12 are formed in a self-aligned manner.
is formed by self-alignment. By adopting such a structure, electric field concentration at the two ends of the train or source diffusion layer is dispersed to two locations, and a high withstand voltage is achieved.
It has an elementary r-structure suitable for high integration. This is particularly effective in devices such as MNO8 type memory devices in which a high voltage is applied to the 1.sup. line (or source).

Hereinafter, the present invention will be explained in detail with reference to Examples.

In order to simplify the explanation, the structure of each part constituting the semiconductor device of the present invention, the dimensions of the conductive type 5, etc. will be defined and explained, but the present invention is not limited thereto.

FIG. 3 is an explanatory diagram of the manufacturing process of the semiconductor device of the present invention,
[a+~+e) shows the cross-sectional structure in the main process, f
e] is a semiconductor device completed by this manufacturing process. Note that ge) is a plan view of +e), and a cross section along the AHA line in the figure is shown as te+. Order of diagrams [a) to t
This will be explained in correspondence with c+.

f2+1: p-type Si substrate] 1, -1: 5i02 film 17 and about 10 with a thickness of about 10 nm (1') at t
Form 5i3Nll ntb 18 of 0 nm.

(1)) E) - By lithography, S+; (N4 film (oxidation (7)? Suff) 18 is left L/T, using the 513N4 film 18 as a mask, Pl-
A diffusion layer (also referred to as an n-layer or first diffusion layer) 13 is formed by implanting ions into the surface of the Si substrate 1j by an ion implantation method. The dose at this time is l x JO''~] x
It was about 1015 cm-2.

(C) Exposure to an oxidizing atmosphere to form a 5i layer with a thickness of about 5Q nm on the n layer 3-1 formed by ion implantation.
02 film 19 is formed. After this, the Si3N4 film 18 and the 8102 film 17 underneath it are removed. However, at this time, one thick 5i02 film or the formed part has a certain thickness of 5i02 film.
The surface mi of the Si substrate 1j is exposed only in the region where the 102 film 19 remains and the Si3N4 film 18 was formed. after that,
5i02 film 2 with a thickness of about 2 nm that allows charge to tunnel t+J
0, a Si3N4 film 21 with a thickness of about 30 nm (7), and a polycrystalline S1 film 22 with a thickness of about 300 nm are successively deposited. In this step, the insulating film (5i02 film 20, Si3N4 film 21) deposited on the exposed part of the surface of the Si substrate 1j
is called the first insulating film, and there is one S]02 film and the insulating film deposited on the first insulating film (5i02 film 20, S+3N4 film 21
) will be referred to as the second insulating film.

fd) The polycrystalline S1 film 22 deposited in the above step,
A predetermined position overlapping with the first layer 13 is left, and the other parts are removed. At this time, the second insulating film present in the removed portion is also removed so that the surface of the Si substrate 1j in the removed portion is exposed. Thereafter, using the remaining polycrystalline Si film 22 as a mask, PL ions are implanted into the exposed surface of the S] substrate 11 by ion implantation to form a diffusion layer (also called a resistance layer or a second diffusion layer) 12. .

The amount of 1·-z of this 11〒 was 1×10 16 cm −2 . It should be noted that the polycrystalline S1 film 22 left with -1- becomes the gate electrode 15 when the semiconductor device is completed.

After depositing the fCIIJ glass film (insulating film) 23, a hole for contact is formed through processes such as annealing, and the M electrode/wiring 24 is not provided.

Below-1-71-: According to the steps, the semiconductor device of the present invention (M
NO8 element) is completed. In addition, in the manufacturing method described in item 1, by changing some of the steps, various semiconductor devices having slightly different structures can be obtained. For example, icl
By approximately 1", an additional approximately 5 nm is added to the Si3N4 film 21".
(D 5i02 film is formed, 5i02-Si3N4
-5i02 (D 3-layer 'l'' -1- Insulating film structure, it is possible to obtain a semiconductor device with reliability in the direction of -1- layer.Furthermore, the 5i02 film 19 is formed in the fcl process. After that, the Si3N4 film 18 and the 5i02 film 17 may be used as the first insulating film without removing them.If this method is used, there is no need to deposit the Si3N4 film 21 again, that is, the second insulating film is Either the 5i02 film 19 should be used, or the 5102 film 19 should be made 1-thick.Furthermore, to simplify the process, the thickness should be approximately 50 nm.
The first insulating film (channel-1- insulating film) and the second insulating film (n-layer] 3 J2 insulating film) are formed identically by omitting the entire step of forming the 19-m Si○2 film 19. Even in this case, results were obtained that satisfied the specified characteristics.

FIG. 4 is a circuit diagram of a nonvolatile memory using the semiconductor device of the present invention. M made by the method shown in the above example
NOS element 40 and switch MO connected in series to it
S trans raster (hereinafter simply abbreviated as IVIO8T).

), a single rewritable non-volatile memory cell is made up of two old elements. The gate 101 of the MO8T4] is connected to the output of the X decoke 42, the gate 102 of the MNO3 element 40 is connected to the output of the write circuit 43,
The other terminal 103 is 71 inch MO8l transistor 4
Sense amplifier 45 and data human power circuit 401 through 4
Otherwise, the other end (source or train) 104 of the MNO8 element 40 is connected to the output of the write fXll +1 circuit 47. Note that the MNO8 element and 108T are formed in a common well at 1 byte X n (17; l li ). An erase circuit 48 is connected to the well.

1. Writing of the MNOS element 40] River 1)-2
1 non-selection.

Alternatively, the potential relationship for each erasing mode is shown graphically in FIG. In the diagram, V■・ is the program voltage,
■-■Ha high level signal, L means low level signal.

By constructing +hv as shown in FIG. 4, a non-volatile memory capable of erasing one byte can be realized.

As explained above, according to the present invention, the withstand voltage of the train or source can be improved, so the element can be made finer and
Moreover, it is possible to use a relatively high voltage. Therefore, it is especially effective in semiconductor devices such as non-volatile memories that require application of a higher voltage than in normal operation. Particularly when using the hide erase or internal boost method, a slight flake town is a problem, but with the present invention,
Since this can be stopped by Ii+1, a programmable nonvolatile memory having the above-mentioned low performance can be realized.

Further, in the present invention, the thin portions of the gate insulating film and the n layer, and the gate and the n4 layer are self-aligned, and are effective for high integration. It should be noted that as a structure similar to the semiconductor 1D device of the present invention, is there a known 3-game 1-structure using M gates? It will be possible to achieve twice as high integration and approximately 15 times as high voltage resistance.

[Brief explanation of the drawing]

FIG. 1 is a structural explanatory diagram of a conventional MIS type semiconductor device, and FIG. 2 is a schematic cross-sectional view showing the main structure of a semiconductor device of the present invention. FIG. In the diagram explaining the manufacturing process of a semiconductor device, ta+ to f (1 indicates the cross-sectional structure in the main process, te+ is a cross-sectional view of the completed semiconductor device, and the crest is the 1' side view. A circuit configuration diagram of a non-volatile memory using the semiconductor device of the invention, FIG. 5 is a chart showing the potential relationship in each mode of the non-volatile memory of FIG. 4. ]・Substrate 2・Source, train 3
Low concentration diffusion layer 4 Insulating film 5 Kate electrode 6 Electrode Wiring 11 Substrate 12 Source, train diffusion layer (01 layer or second diffusion layer) 13 Diffusion layer (n layer or first diffusion layer) 1/l-insulating film 15, gate electrode 16...insulating film (first
(insulating film) 17.5i02 film 18- Si3N4 film (oxidation mask) 10.S]02
Film 20...5102 film 21/Si3N4 film
22・Polycrystalline Si film 2:3・Phosphorus glass film (
Insulating film) 24... Electrode/wiring 40... MNO3 element 4
1...Switch MOS transistor (MO8T)/17
・Junnosuke Nakamura, Patent Attorney, Circuit Agent]

Claims (1)

[Scope of Claims] (1) At least a first insulating film and a second insulating film disposed adjacent to the first insulating film are provided between the gate electrode and the substrate;
a first diffusion layer of conductivity type opposite to that of the substrate formed on the surface of the substrate under the second insulating film, and a first diffusion layer under the first insulating film; 1. A semiconductor device comprising: a second diffusion layer formed adjacent to the first diffusion layer and having a conductivity type opposite to that of the substrate on the surface of the substrate opposite to the channel. +2) The first insulating film forming region and the first diffusion layer in I-, the gate electrode and the second diffusion layer in -1- are formed in a self-aligned manner. 1. Semiconductor device described in Section 1. t3+ 1- first insulating film or second insulating film, 2
3. The semiconductor device according to claim 1 or 2, which comprises a plurality of insulating films of seven or more layers. (4) The first insulating film and the second insulating film described in 1- above are composed of an insulating film of two or more IV several layers, and at least one insulating film among the few layers is Claim 1 or 2 consists of an equal insulator formed.
1. Semiconductor device described in Section 1. (Claim 514) The first insulating film is composed of a small number of layers, and the thickness of the insulating film located on the substrate side of the first insulating film has a value that allows tunneling of charges. Section 2, 3rd
Item i1i! 2. Semiconductor device. (6) J:, first insulating film and second insulating film, 4Z
quality. The semiconductor device according to claim 1, wherein the semiconductor device is formed of an insulating film having substantially the same thickness. (7) Forming a layer to serve as an oxidation mask in the region of the substrate 11 where the first insulating film is to be formed, and using the mask to form a layer on the region of the substrate 11 where the second insulating film is to be formed. A step of forming a first diffusion layer having a conductivity type opposite to that of the plate, a step of forming an oxide film on the first diffusion layer -1- using a mask described in -I-, and a step of removing the mask to form a removed portion. = L length to expose the surface of the substrate; L length to deposit an insulating film on the substrate including the exposed portion to form a first insulating film and a second insulating film; Step 11 of forming a gate electrode at a predetermined position of the second insulating film 1-, removing an unnecessary portion of the second insulating film using the gate electrode as a mask to expose the substrate surface, and forming a gate electrode on the exposed substrate portion. A method for manufacturing a semiconductor device characterized by forming a second diffusion layer of conductivity type opposite to that of the substrate. (8) First oxidation forming a part of the first insulating film on the substrate. forming a film in a predetermined region of the second oxide film;
a step of forming a nitride film forming a part of an insulating film; a step of forming a first diffusion layer of a conductivity type opposite to that of the substrate in the substrate using the nitride film as a mask; a second insulating film adjacent to the first insulating film;
a step of forming an oxide film of the first oxide film; Step 1 of forming a gate electrode at a predetermined position on the second insulating film, step 2 of removing unnecessary portions of the second insulating force using the gate electrode as a mask, and step 2 of forming the gate electrode at a predetermined position on the second insulating film. A method for manufacturing a semiconductor device, comprising the step of forming a second diffusion layer of a conductivity type opposite to that of the substrate on the substrate as a mask. (9) A first insulating film consisting of at least a plurality of layers; A first diffusion layer having a second insulating film adjacent thereto between the gate electrode and the substrate, and having a conductivity type opposite to that of the substrate formed on the surface of the substrate under at least the second insulating crotch. , and a second diffusion layer having a conductivity type opposite to that of the substrate, which is formed adjacent to the first diffusion layer on the surface of the substrate opposite to the channel under the first insulating film with the first diffusion layer in between. M configured with a diffusion layer of
Using the NO8 element in a nonvolatile memory cell, -11 M
1. A semiconductor device comprising a memory device configured by connecting a peripheral circuit that applies a high voltage for inhibiting writing to the source or drain of an NO8 element.