JPS5955034A - Formation of interelement isolating film - Google Patents

Formation of interelement isolating film

Info

Publication number
JPS5955034A
JPS5955034A JP16574182A JP16574182A JPS5955034A JP S5955034 A JPS5955034 A JP S5955034A JP 16574182 A JP16574182 A JP 16574182A JP 16574182 A JP16574182 A JP 16574182A JP S5955034 A JPS5955034 A JP S5955034A
Authority
JP
Japan
Prior art keywords
substrate
film
films
silicon
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16574182A
Other languages
Japanese (ja)
Inventor
Yoshimi Shiotani
喜美 塩谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16574182A priority Critical patent/JPS5955034A/en
Publication of JPS5955034A publication Critical patent/JPS5955034A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To enable to form the interelement isolating SiO2 film with a small area by a method wherein after a resist film and the protruding oxide films of silicon epitaxial layers formed on a silicon substrate are etched, while silicon dioxide films remaining on the epitaxial layers are removed. CONSTITUTION:The photo resist film 15 is applyingly formed on the substrate, and the upper part of the surface of the substrate is made to be the flat condition by burying the gaps between the Si layers 13 grown in the convex type on the SiO2 films 12. After then the substrate is installed in a reaction tube, mixed gas of carbon tetrafluoride gas and O2 gas is introduced in the reaction tube, a high-frequency voltage is applied between an electrode and a substrate installation base in the reaction tube, and the photo resist film 15 on the surface of the substrate and the SiO2 films 14 protruding locally on the interelement isolating SiO2 films 12 are etched at the same time by plasma to be removed. The SiO2 films 14 remaining on the epitaxial layers 13 are etched to be removed by the mixed liquid of hydrofluoric acid and ammonium fluoride, and the surface of the Si substrate demarcated by the interelement isolating SiO2 films 12 having the flat surface and the small area is obtained.

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発明はIC,LSI等の半導体装置製造の際、 に用
いられる素子間分離膜の形成方法の改良に関する本ので
ある。             □(ハ)技術の背景 工01LSI等の半導体装置を形成する際、シリコン(
Sl)のような半導体基板に所定パターンの土酸化シリ
□コン(S1O2)膜を形成し、該5102膜で画定さ
れた領域内にトランジヌタ等の半導体素子を形成して半
導体装置を形成している。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention is a book related to an improvement in a method for forming an isolation film between elements used in manufacturing semiconductor devices such as ICs and LSIs. □(c) Technology background 01 When forming semiconductor devices such as LSI, silicon (
A semiconductor device is formed by forming a silicon oxide (S1O2) film in a predetermined pattern on a semiconductor substrate such as 5102 film, and forming semiconductor elements such as transistors within the area defined by the 5102 film. .

ところ寸このような素子間分離用のS’x0.1膜は出
来るだけ面□積を小さくして形成し、1枚の81基板上
にできるだけ多数の半導体素子を高密度に形成すること
が望ましい。        ゛(Q)  従来技術と
問題点   □       ・従来このような素子間
分離用のSin、膜の形成方法としては、第1図に示す
ように表面が(tOa)面の81単結晶基板lに所定パ
ターンのホトレジスト膜2を形成し、該ホトレジスト膜
2をマスクトシ七力缶イカリ(FCOll()のエツチ
ング液を用いてエツチングする。こめようにすればV字
状の溝8が形成され、この7字溝8の傾斜面4が(Il
l)面となるように異方性エツチングされる。この上、
、  ・うにして形成された7字溝を有する81基板表
面を02ガスを含んだH2,Oガスの雰囲気内で加熱し
て7字溝内およびSi基板表面にS:lO,膜を形成し
てから、1字溝内を除いてSj、基板表面に付着してい
るSiO2膜を選択的にエツチングして除去する。
It is desirable to form such a S'x0.1 film for isolation between elements with a surface area as small as possible, and to form as many semiconductor elements as possible on one 81 substrate at high density. .゛(Q) Conventional technology and problems □ ・Conventionally, as a method for forming such a Si film for isolation between elements, as shown in Fig. A patterned photoresist film 2 is formed, and the photoresist film 2 is etched using an etching solution of FCOll (FCOll) using a mask. The inclined surface 4 of the groove 8 is (Il
l) Anisotropically etched to form a surface. On top of this,
・Heat the surface of the 81 substrate with the 7-shaped grooves formed in this way in an atmosphere of H2, O gas containing 02 gas to form a S:lO, film inside the 7-shaped grooves and on the Si substrate surface. After that, the SiO2 film adhering to Sj and the substrate surface is selectively etched and removed except for the inside of the single-shaped groove.

そしてこのような7字溝の5in2膜で画定されたSi
基板表面へ半導体素子形成用不純物を導入して工C,L
SI等の半導体装置を製造するようにしていた。
And the Si defined by the 5in2 film with 7-shaped grooves like this
Processes C and L by introducing impurities for semiconductor element formation into the substrate surface.
The company was manufacturing semiconductor devices such as SI.

しかし上述した7字状の素子間分離用5102膜を81
基板上に形成したのでは、該7字状の5in2膜がSj
−基板の表面に到達するにつれて面積が拡大する傾向を
生じ、そのため素子間分離用5j−02膜のSi基板表
面における面積が増大して、1枚のSi基板に半導体素
子を多数集積化して形成できない欠点を生じている。
However, the above-mentioned 7-shaped 5102 film for isolation between elements is
When formed on a substrate, the 7-shaped 5in2 film is Sj
- The area tends to expand as it reaches the surface of the substrate, so the area of the 5j-02 film for element isolation on the Si substrate surface increases, making it difficult to integrate a large number of semiconductor elements on one Si substrate. This has resulted in the disadvantage that it cannot be done.

(cl)発明の目的 本発明は上述した欠点を除去し、工C!、LSI等の半
導体装置製造の際の工程に用いる素子間分離用5−10
.膜を小さい面積で形成し得るようにした新規な素子間
分離用Si、O,膜の形成方法の提供を目的とするもの
である。
(cl) OBJECT OF THE INVENTION The present invention eliminates the above-mentioned drawbacks and provides C! , 5-10 for isolation between elements used in the process of manufacturing semiconductor devices such as LSI
.. The object of the present invention is to provide a novel method for forming a Si, O, and film for isolation between elements, which allows the film to be formed in a small area.

(e)  発明の構成 かかる目的を達成するだめの本発明の素子間分離用Si
、O,膜の形成方法はシリコン基板上に所定パターンの
絶縁膜を形成し、更に該基板上にシリコンエピタキシャ
ル層を形成して前記絶縁膜の間を埋めるようにし次に該
エピタキシャル層表面を酸化後、前記所定パターンの絶
縁膜上に形成され突出シているシリコンエピタキシャル
層が埋まる厚さに該基板上にレジスト膜を形成し、次い
で前記1/シスト膜および突出しているシリコンエピタ
キシャル層’層の酸化物膜を干ツチングした後更にエピ
タキシャル層上に残留している二酸化シリコン膜を除去
することを特徴とするものである。
(e) Structure of the Invention Si for device isolation of the present invention to achieve the above object
, O, film formation method is to form an insulating film in a predetermined pattern on a silicon substrate, further form a silicon epitaxial layer on the substrate to fill in the gaps between the insulating films, and then oxidize the surface of the epitaxial layer. After that, a resist film is formed on the substrate to a thickness that buries the protruding silicon epitaxial layer formed on the insulating film of the predetermined pattern. This method is characterized in that after drying the oxide film, the silicon dioxide film remaining on the epitaxial layer is further removed.

(f′)発明の実施例 以下図面を用いて本発明の一実施例につき詳細に説明す
る。第2図に示すようにまずN型の81基板ll上にシ
ラン(SiH,)ガスと酸素(02)ガスと用いたケミ
カル、ペーパー、デポジション(OVD)法によりある
いは該基板の熱酸化法によってSin、膜を形成後、該
基板上に所定パターンのホトレジスト膜を形成し、該ホ
トレジスト膜をマスクとしてプラズマエツチング法等に
よシ所定パターンの5j−02膜12を形成する。
(f') Embodiment of the Invention An embodiment of the invention will be described below in detail with reference to the drawings. As shown in Fig. 2, first, a chemical paper deposition (OVD) method using silane (SiH) gas and oxygen (02) gas or a thermal oxidation method of the substrate was performed on an N-type 81 substrate ll. After forming the Sin film, a photoresist film with a predetermined pattern is formed on the substrate, and a 5j-02 film 12 with a predetermined pattern is formed by plasma etching or the like using the photoresist film as a mask.

次いで該基板を反応管中に挿入し該反応管中へ四塩化硅
素(Sice4)と水素CHg)との混合ガスを導入し
、該反応管を加熱してS:1c74の水素還元によって
、第3図に示すように単結晶のシリコンエピタキシャル
層13を前述した5102膜の間へ埋めるようにして形
成する。この時前述の8102膜12の上へもSiエピ
タキシャμ層が成長し、5in2膜上がSi層で凸形形
状を呈するようになる。
Next, the substrate was inserted into a reaction tube, a mixed gas of silicon tetrachloride (Sice4) and hydrogen (CHg) was introduced into the reaction tube, and the reaction tube was heated to reduce S:1c74 with hydrogen. As shown in the figure, a single crystal silicon epitaxial layer 13 is formed so as to be buried between the 5102 films described above. At this time, the Si epitaxial μ layer also grows on the 8102 film 12 described above, and the Si layer forms a convex shape on the 5in2 film.

次に該基板表面を熱酸化してSi、02膜14を全面に
形成する。この5102膜14は後の工程でホトレジス
ト膜をエツチングする際に81工ピタキシヤル層表面を
損傷しないように保護する保護膜としての働きを有する
Next, the surface of the substrate is thermally oxidized to form a Si,O2 film 14 on the entire surface. This 5102 film 14 functions as a protective film to protect the surface of the 81-layer pitaxial layer from damage when etching the photoresist film in a later step.

15を塗布形成し、前述の8102膜12上に凸形に成
長している81層13の間を埋めるようにして基板表面
上をなだらかに平坦な状態にする。
15 is applied to fill the spaces between the 81 layers 13 which have grown in a convex shape on the 8102 film 12 described above, so that the surface of the substrate is gently flattened.

その後読基板を反応管中の基板設置台に設置し四弗化炭
素(CF4)ガスが95容量%、Oi!ガスが5容量%
の混合ガスを反応管中へ導入し、反応管内の電極と基板
設置台間に出力1.2 KW 、周波数13.56MH
zの高周波電圧を印加して該基板表面のホトレジスト膜
15と素子間分離用8102膜12上に局部的に突出し
ている5102膜14を同時にプラズマエツチングして
除去する。ここで上述したOF、4ガスと02ガスの混
合ガスを用いることでホトレジスト膜12と突出したS
in、膜14とがほぼ同じ速度でエツチングされて除去
される。このようにして形成された状態を第5図に示す
Thereafter, the reading substrate was placed on the substrate mounting stand in the reaction tube, and carbon tetrafluoride (CF4) gas was added at 95% by volume, Oi! Gas is 5% by volume
Introduced a mixed gas into the reaction tube, and connected it between the electrode in the reaction tube and the substrate installation stand with an output of 1.2 KW and a frequency of 13.56 MH.
By applying a high frequency voltage of z, the photoresist film 15 on the surface of the substrate and the 5102 film 14 locally protruding on the 8102 film 12 for element isolation are simultaneously removed by plasma etching. Here, by using the above-mentioned mixed gas of OF, 4 gas and 02 gas, the photoresist film 12 and the protruding S
In, film 14 is etched and removed at approximately the same rate. The state formed in this manner is shown in FIG.

図示するように素子間分離用のSin、膜12上で突出
して形成されていたsxo、、 # 14も除去されて
平坦な状態となる。。
As shown in the figure, the Si for element isolation and the sxo, #14 that were formed protrudingly on the film 12 are also removed, resulting in a flat state. .

更に該エピタキシャル層18上に残留しているモ=ウム
(NH4F)の混合液にてエツチングして除去すること
で、第6図のように表面が平坦で小さい面積の素子間分
離用5102膜12で画定された81基板表面が得られ
、このSing膜12で画定された領域内へ半導体素子
形成用不純物を導入することで高密度に集積化された工
C,LSI等の半導体装置が形成できる。
Furthermore, by etching and removing the remaining epitaxial layer 18 with a mixed solution of molybdenum (NH4F), a 5102 film 12 for isolation between elements with a flat surface and a small area is formed as shown in FIG. By introducing impurities for semiconductor element formation into the region defined by this Sing film 12, highly integrated semiconductor devices such as C, LSI, etc. can be formed. .

(至)発明の効果 以上述べたように本発明の方法によれば81基板に微少
な面積で素子間分離用5in2膜が形成できるので、該
基板に形成される半導体装置の集積度が向上し、また基
板表面が平坦に形成されるので、半導体素子形成後、該
素子間を接続する配線が断線したりする恐れがなくなり
高信頼度の半導体装置が得られる利点を有する。
(To) Effects of the Invention As described above, according to the method of the present invention, a 5in2 film for isolation between elements can be formed on an 81 substrate in a minute area, so the degree of integration of semiconductor devices formed on the substrate is improved. Moreover, since the substrate surface is formed flat, there is no fear that the wiring connecting between the semiconductor elements will be disconnected after the semiconductor elements are formed, and a highly reliable semiconductor device can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の半導体装置の製造方法を示す断面図、第
2図より第6図までは本発明の半導体装置の製造方法の
一実施例を示す断面図である。 図においてl、11は81基板、2.■5はホトレジヌ
ト膜、8は7字溝、4はV字溝側面、12゜14は51
02膜、18はSiエピタキシャル層を示す。 第1図 第2図 第3図 第4図 第5図 4 第6図
FIG. 1 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device, and FIGS. 2 through 6 are cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device according to the present invention. In the figure, 1 and 11 are 81 substrates, 2. ■5 is photoresinut film, 8 is 7-shaped groove, 4 is V-shaped groove side, 12°14 is 51
02 film, 18 indicates a Si epitaxial layer. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 4 Figure 6

Claims (1)

【特許請求の範囲】[Claims] シリコン基板上に所定パターンの絶縁膜を形成し、更に
該基板上にシリコンエピタキシャル層を形成して前記絶
縁膜の間を埋めるようにし次に該エピタキシャル層表面
を酸化後、前記所定パターンの絶縁膜上に形成され突出
しているシリコンエピタキシャル層が埋まる厚さに該基
板上にレジスト膜を形成し、次いで前記レジスト膜およ
び突出しているシリコンエピタキシャル層の酸化物膜を
エツチングした後更にエピタキシャル層上に残留してい
る二酸化シリコン膜を除去することを特徴とする素子間
分離膜の形成方法。
An insulating film with a predetermined pattern is formed on a silicon substrate, and a silicon epitaxial layer is further formed on the substrate to fill in the gaps between the insulating films.Then, after oxidizing the surface of the epitaxial layer, the insulating film with a predetermined pattern is formed on the silicon substrate. A resist film is formed on the substrate to a thickness that buries the protruding silicon epitaxial layer formed thereon, and then, after etching the resist film and the protruding oxide film of the silicon epitaxial layer, a resist film remains on the epitaxial layer. 1. A method for forming an isolation film between elements, characterized by removing a silicon dioxide film that is
JP16574182A 1982-09-22 1982-09-22 Formation of interelement isolating film Pending JPS5955034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16574182A JPS5955034A (en) 1982-09-22 1982-09-22 Formation of interelement isolating film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16574182A JPS5955034A (en) 1982-09-22 1982-09-22 Formation of interelement isolating film

Publications (1)

Publication Number Publication Date
JPS5955034A true JPS5955034A (en) 1984-03-29

Family

ID=15818189

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16574182A Pending JPS5955034A (en) 1982-09-22 1982-09-22 Formation of interelement isolating film

Country Status (1)

Country Link
JP (1) JPS5955034A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5541715A (en) * 1978-09-19 1980-03-24 Oki Electric Ind Co Ltd Production of semiconductor device
JPS5768049A (en) * 1980-10-15 1982-04-26 Fujitsu Ltd Semiconductor device and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5541715A (en) * 1978-09-19 1980-03-24 Oki Electric Ind Co Ltd Production of semiconductor device
JPS5768049A (en) * 1980-10-15 1982-04-26 Fujitsu Ltd Semiconductor device and manufacture thereof

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