JPS5953950A - Fault relieving method of inter-processor communication equipment - Google Patents

Fault relieving method of inter-processor communication equipment

Info

Publication number
JPS5953950A
JPS5953950A JP57163866A JP16386682A JPS5953950A JP S5953950 A JPS5953950 A JP S5953950A JP 57163866 A JP57163866 A JP 57163866A JP 16386682 A JP16386682 A JP 16386682A JP S5953950 A JPS5953950 A JP S5953950A
Authority
JP
Japan
Prior art keywords
inter
processor communication
communication equipment
communication device
fault
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57163866A
Other languages
Japanese (ja)
Inventor
Koshu Yoshizaki
吉崎 皇秋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57163866A priority Critical patent/JPS5953950A/en
Publication of JPS5953950A publication Critical patent/JPS5953950A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To eliminate a state that a stand-by system does not rise, and to improve performance, by constituting so that a processor communication equipment which takes the leadership initializes an inter-processor communication equipment of other system, when a fault is generated in the inter-processor communication equipment of other system. CONSTITUTION:When a fault is generated in a sub-system processor 6, a fault display FF/14 of a sub-system transmits fault information to a software by a data bus 18 of a CPU 1 of an active system, through a system control device 5 and a gate 12. As a result, the software detects its fault information, and issues an initializing prescribed instruction to an inter-processor communication equipment of its own system. When the self system is the ACT system, its signal is transmitted to the sub-system, and the inter-processor communication equipment of the sub-system is initialized.

Description

【発明の詳細な説明】 本発明は、中央処理装置が2重化ネれ、他系のプロセッ
サ間通信装置の障害検出時、他系のプロセッサ間通信装
置を初期設定することによシ、プロセッサ間通信装置の
障害を救済する方式に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention has a dual central processing unit, and when a failure is detected in the inter-processor communication device of the other system, the processor The present invention relates to a method for relieving failures in intercommunication equipment.

従来、プロセッサ間通信装置に障害が発生した場合、他
系のシステム、コントローラを介して障害発生のステエ
イ々スを検出し、それぞれの中央制御装置がプロセッサ
間通信装置を初期設定することによりプロセッサ間通信
装置の障害を救済していた。
Conventionally, when a failure occurs in an inter-processor communication device, the failure is detected via other systems and controllers, and each central control device initializes the inter-processor communication device to resolve the problem. They were assisting with communication equipment failures.

本方式の欠点は、プロセッサ間通信装置の初期設定を各
基が独立に行うため、同期のとれた運用ができないこと
である。
The drawback of this method is that synchronized operation is not possible because each unit performs the initial settings of the interprocessor communication device independently.

本発明の目的は、従来技術の欠点、即ちプロセッサ間通
信装置の初期設定を両系で非同期にやるのではなく、主
導権を持つプロセッサ間通信装置が他系のプロセッサ間
通信装置を同期化させようとするものである。
The purpose of the present invention is to overcome the shortcomings of the prior art, that is, instead of performing the initial settings of the inter-processor communication devices asynchronously in both systems, the inter-processor communication device having the initiative synchronizes the inter-processor communication devices of other systems. This is what we are trying to do.

本発明は、上記の目的を他系のプロセッサ間通信装置に
障害が発生し、初期設定信号が送出されたことを検出す
る手段と、該信号をソフトウェアに連絡する手段と、他
系のプロセッサ間通信装機を初期設定する手段を設ける
ことによシ実現しようとするものである。
The present invention aims to achieve the above-mentioned purpose by providing a means for detecting that an initial setting signal is sent when a failure occurs in a communication device between processors of another system, a means for communicating the signal to software, and a means for communicating between processors of another system. This is attempted to be achieved by providing a means for initializing the communication equipment.

以下、本発明の一実施例を図により説明する。Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

1はACT系の中央制御装置である。2けACT系のシ
ステム制御装置である。6はACT系のプロセッサ間通
信装置である。4,5.6はSBY系の上記各装置に対
応する。
1 is a central control device of the ACT system. This is a 2-digit ACT system control device. 6 is an ACT-based interprocessor communication device. 4, 5.6 correspond to each of the above-mentioned devices of the SBY system.

7は中央処理装置1のアドレス線であり、8はデータ線
である。
7 is an address line of the central processing unit 1, and 8 is a data line.

9は他系システム制御装置へ自系プロセッサ間通信装置
の障害表示F/F 14の状態を伝える信号線である。
Reference numeral 9 denotes a signal line for transmitting the status of the fault display F/F 14 of the inter-processor communication device of the own system to the system control device of the other system.

12は他糸プロセッサ間通信装置の障害を中央制御装置
1が読み出すゲートである。
Reference numeral 12 denotes a gate through which the central control unit 1 reads failures in the communication device between processors of other threads.

15はソフトウェアのプロセッサ間通信装置のアドレス
、デコーダである。ゲート16けACT系のときプロセ
ッサ間通信装置を初期設定するものである。17はSB
Y系時、他系よりのプロセッサ間通信装置の初期設定命
令を受けつけるゲートである。
15 is an address and decoder of a software interprocessor communication device. This is used to initialize the inter-processor communication device in the case of a 16-gate ACT system. 17 is SB
In the Y system, this is a gate that receives an initial setting command for the interprocessor communication device from another system.

SBY糸プロセッサ間通信装置6に障害が発生した場合
、SBY系の障害表示F/F 14がシステム制御装置
5を経由してゲート12を介してACT系の中央制御装
置1のデータ、バス18によシ、その障害情報がソフト
ウェアに伝えられる。
When a failure occurs in the SBY thread processor communication device 6, the SBY system failure display F/F 14 transmits data to the ACT system central control unit 1 and bus 18 via the system control unit 5 and the gate 12. Okay, that failure information is passed on to the software.

ソフトウェアはその障害情報を検出することにより、自
系プロセッサ間通信装置に初期設定命令を発行する。自
系がACT系の場合、その信号をSBY系に伝え、SB
’Y系のプロセッサ間通信装置も初期設定が可能になる
By detecting the fault information, the software issues an initialization command to its own interprocessor communication device. If the own system is an ACT system, the signal is transmitted to the SBY system, and the SB
'Y system interprocessor communication device can also be initialized.

本発明によれば、プロセッサ間通信装置の初期設定を両
系で同期化して初期設定することにより、プロセッサ間
通信装置の障害でスタンド、パイ系が立ち上らないとい
う欠点がなくなり性能の向上に効果を奏する。
According to the present invention, by synchronizing and initializing the initial settings of the inter-processor communication device in both systems, the disadvantage that the stand and pie systems cannot be started due to a failure in the inter-processor communication device is eliminated, and performance is improved. be effective.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の一実施例を説明するための通信装置の回路
図である。 1・・・中央制御装置、 2・・・システム制#11装
置、6・・・プロセッサ間通信装置、 7・・・アドレス線、   8・・・データ線、12・
・・ゲート、15・・・アドレス、テコータ、17・・
・ゲート。
The figure is a circuit diagram of a communication device for explaining one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Central control unit, 2... System system #11 device, 6... Inter-processor communication device, 7... Address line, 8... Data line, 12...
...Gate, 15...Address, Tekota, 17...
·Gate.

Claims (1)

【特許請求の範囲】[Claims] 1、 中央処理装置が2重化され、各基にあるプロセッ
サ間通信装置によシ接続されている場合、他系プロセッ
サ間通信装置で障害が発生したことを検出する手段と、
該信号をソフトウェアに連絡する手段と、他系のプロセ
ッサ間通信装置をソフトウェアのコマンドによシ初期設
定する手段とを設けたことを特徴とするプロセッサ間通
信装置の障害救済方法。
1. When the central processing unit is duplicated and connected to an inter-processor communication device in each base, means for detecting that a failure has occurred in the inter-processor communication device of another system;
A fault recovery method for an inter-processor communication device, comprising means for communicating the signal to software, and means for initializing an inter-processor communication device of another system according to a command from the software.
JP57163866A 1982-09-22 1982-09-22 Fault relieving method of inter-processor communication equipment Pending JPS5953950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57163866A JPS5953950A (en) 1982-09-22 1982-09-22 Fault relieving method of inter-processor communication equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57163866A JPS5953950A (en) 1982-09-22 1982-09-22 Fault relieving method of inter-processor communication equipment

Publications (1)

Publication Number Publication Date
JPS5953950A true JPS5953950A (en) 1984-03-28

Family

ID=15782253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57163866A Pending JPS5953950A (en) 1982-09-22 1982-09-22 Fault relieving method of inter-processor communication equipment

Country Status (1)

Country Link
JP (1) JPS5953950A (en)

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