JPS5953513B2 - Electronic clock with zero return - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a seconds return device in an electronic timepiece equipped with a hand movement display device.

Conventionally, as a method of correcting errors in seconds in electronic watches equipped with a hand movement display device, an auxiliary counter that is synchronized with the second hand of the hand movement display device and a return to zero switch are provided, and this return to zero switch is used as a standard for time signals, etc. A so-called second-return method, in which errors in seconds are corrected by adjusting the time, is commonly used.

To explain the second zero return method used in the present invention with reference to FIG. 1, 1 is a reference oscillation circuit equipped with a crystal oscillator, and 2 is an IHz clock signal obtained by dividing and waveform-shaping the oscillation signal of the reference oscillation circuit 1. A frequency dividing circuit 3 generates φ1 and a fast forward signal φ2 of 32 Hz, and 3 is a signal switching circuit, which is composed of AND gates 4 and 5 and an OR gate 6.

7 is a motor drive circuit, 8 is a pulse motor that is an electromagnetic converter, and 9 is a hand movement display device driven by the pulse motor 8 via a clock train (not shown), including an hour hand 9a, a minute hand 9b, and a second hand 9C. has.

The above series of configurations constitutes a well-known hand movement display type electronic timepiece.

Next, the configuration of the seconds return device will be explained.

Reference numeral 11 denotes an auxiliary counter driven in synchronization with the second hand 9C of the hand movement display device 9, which has a sexagesimal configuration and has input terminal Ill, output terminal Q1□, reset terminal R□1, and condition terminal C. has.

12 is a correction control circuit, and this correction circuit 12 includes a reference counter 13, a coincidence detection circuit 14, and a delay/advance judgment circuit 15.
, an RS type flip-flop (hereinafter abbreviated as R8-FF) 16, and an AND gate 17. Furthermore, the lag/lead determination circuit 15 is composed of two AND gates 18, 19, and an inverter 20. .

21 and 22 are zero return switches and reset switches that are linked to external operation members, 23 and 24 are waveform shaping circuits for pulsing the operation signals of the respective switches, 25 and 26 are AND gates, and 27 is an AND gate. It is an inverter.

Next, the operation of the electronic timepiece with the above configuration will be explained.

In the normal state, the correction control circuit 12 has R3 and FF16.
is in the reset state, and the two AND gates 18 and 19 constituting the lag/lead judgment circuit 15 connected to its output terminal Q are both in the OFF state, so that its judgment output terminals Qd and Qs is kept at logic "0" and unmodified.

As a result, the AND gate 5 connected to the delay determination terminal Qd is turned off, and the AND gate 5 connected to the advance determination terminal Qs is turned off.
When the ND gate 26 is in the OFF state and the advance judgment terminal Qs
AND gate 4 connected through inverter 27 from
and 25 are in the ON state.

Therefore, the output signal from the frequency dividing circuit 2 is ORed by selecting only the lHz clock signal φ□ by the signal switching circuit 3.
Motor drive circuit 7 via gate 6 and AND gate 4
The time is displayed on the hand movement display device 9 by driving the pulse motor 8 in 1 second steps.

Furthermore, the clock signal φ1 which has passed through the OR gate 6 passes through the AND gate 25 which is in the ON state and is supplied to the input terminal ■1□ of the auxiliary counter 11.

Therefore, when the reset switch 22 is operated once when the second hand 9C of the hand movement display device 90 is at the zero second position, a reset signal outputted from the waveform shaping circuit 24 according to this operation is supplied to the reset terminal R1□, thereby providing assistance. The contents of the counter 11 are reset to zero, and thereafter it is driven in synchronization with the second hand 9C by the clock signal φ1 supplied to the input terminal 11□.

Furthermore, the auxiliary counter 11 outputs the counted contents to the output terminal Q.
1□ to the coincidence detection circuit 14, and the condition terminal C has a logic 90" level when the count content is between 0 and 29, and a logic 90" level between 30 and 5.
During the period 9, a condition signal of logic "1" level is generated.

The above is the normal clock operation.Next, the zero correction operation will be explained.

That is, when it becomes necessary to adjust the time, when the user issues a correction command to the correction control circuit 12 by operating the zero return switch 21, the correction control circuit 12 operates in response to the correction signal and should stop the clock signal. (if the clock is running forward)
, determine whether the clock signal should be turned into a fast-forward signal (if the clock is delayed), or whether to leave the clock signal as it is and nit seconds or less (if the clock is out of order), and control each element. This is to correct the clock's inaccuracy.

Now, let's think about corrective actions when the clock is behind.

When the user recognizes that the clock is behind and operates the zero switch 21 at the same time as the time signal or bulletin, this operation causes a correction signal generated from the waveform shaping circuit 23 to reset the frequency dividing circuit 2 and the reference counter 13. slightly delayed,
Set R3 and FF16.

Now, as an example, if the delay of the clock is 5 seconds, the second hand 9C of the hand movement display device 9 indicates 55 seconds, the content of the auxiliary counter 11 is 55 seconds, and the output terminal Q1□ has an output value of 55 seconds. However, a condition signal of logic "1" level is outputted to the condition terminal C, respectively.

Therefore, R8-F set by the correction signal
AND gate 17 connected to output terminal Q of F16
is in the ON state, and furthermore, in the delay/advance judgment circuit 15, the delay judgment terminal Qd becomes 1" and the lead judgment terminal Qs becomes 0", so the AND gate 5 connected to the judgment terminal Qd is inverted to the ON state, and the signal switching circuit 3 to fast forward mode.

As a result, the fast forward signal φ2 that has passed through the AND gate 5 and the OR gate 6 is transferred to the AND gate 4 and the motor drive circuit 7.
At the same time, the pulse motor 8 is fast-forwarded via AND
The auxiliary counter 11 is fast-forwarded through the gate 25 and returns to zero.

This return to zero operation is performed at the output terminal Q of the auxiliary counter 11.
1□ and the value of the output terminal Q□3 of the reference counter 13 match, the match signal generated by the match detection circuit 14 is A.
The signal passes through the ND gate 17 to reset the R8-FF16, and the output terminal Q of the R8-FF returns the lag/advance determining circuit 15 to the non-repaired state, thereby ending the process.

In the series of delay correction operations described above, the delay of the hand movement display device 9 and the auxiliary counter 11 is corrected by fast forwarding using the reference counter 13 reset by the correction signal as a comparison standard. The second hand 9C returns to the 0 second position, and the zero return switch 21
Normal clock operation is resumed by the clock signal φ1, which is generated again one second after the frequency dividing circuit 2 is reset by the operation signal.

Next, the advance correction operation when the clock is ahead by 5 seconds will be explained.

Similarly to the delay correction operation described above, when the zero return switch 21 is operated at the same time as the time signal or bulletin, the second hand 9C indicates 5 seconds and the content of the auxiliary counter 11 also indicates 5 seconds.
Since the output value 5 is output to the output terminal Q1 and the condition signal of logic "0" level is output to the condition terminal C, the frequency dividing circuit 2 and the reference counter 13 are reset and then set by the correction signal. In response to the output Q of the R8-FF16, only the lead determination terminal Qs of the lag/advance determination circuit 15 is set to logic 51''.

Therefore, the AND gate 26 directly connected to the judgment terminal Qs is turned ON, and the AND gate 26 connected directly to the judgment terminal
The ND gates 4 and 25 are turned off, and the signal switching circuit 3
Switch to signal blocking state.

As a result, the clock signal φ1 that has passed through the OR gate 6 is AN
At the same time, the supply to the motor drive circuit 7 and the auxiliary counter 11 is blocked by the D gates 4 and 25, respectively.
Input terminal 11 of reference counter 13 through D gate 26
3 and counted.

In this advance correction operation, when the values of the output terminal Qll of the auxiliary counter 11 and the output terminal Q13 of the reference counter 13 match, a match signal generated from the match detection circuit 14 passes through the AND gate 17 and the R3-FF16 is reset, and the lag/advance determining circuit 15 returns to the non-correction state by the output terminal Q of the R3-FF 16, thereby ending the process.

In the above series of advance correction operations, the auxiliary counter 11
is used as a comparison standard, and the reference counter 13 reset by the correction signal counts the number of clock signals to be blocked, thereby correcting the progress of the hand movement display device 9 and the auxiliary counter 11. As a result, the hand movement display device 9 The second hand 9C stops for 5 seconds and then returns to normal watch operation.

If the clock error is less than 1 second, when the return-to-zero switch 21 is operated, the contents of the second hand 9C and the auxiliary counter 11 are both 0 seconds, so the correction signal is used to change the frequency divider circuit 2 and the reference counter. After resetting 13, R3-
At the same time that the FF 16 is set, a coincidence signal is outputted from the coincidence detection circuit 14 to reset the R8-FF 16, so that a return to zero within a second is performed as a result.

As mentioned above, the seconds return/zero device of a hand movement display type electronic watch requires two switches: a reset switch to reset the auxiliary counter and a zero return switch. Conventionally, this reset switch drives the hand movement display device. The structure is such that the auxiliary counter is reset every minute, or the structure is closed in conjunction with an external operating member such as a crown, so that the user can control the movement of the hands. There is a method in which the auxiliary counter is reset by operating the external operation member while looking at the display device and when the second hand is at the 0 second position, but the former method is less functional. However, the structure is complicated and there are problems with reliability because the switch must be closed many times.In the latter case, multiple external operating members are required, and operating members with other functions are required. Although it is possible to consider a method in which both are used, this method has the disadvantage that the operation for returning to zero is complicated and difficult to understand.

An object of the present invention is to provide a zero return device for an electronic timepiece that solves the above-mentioned drawbacks, and the gist of the present invention for achieving the above-mentioned object is to provide a reference oscillation circuit, a frequency dividing circuit, an electromagnetic converter, It has a hand movement display device driven by the electromagnetic converter, and further includes an auxiliary counter that synchronizes with the hand movement display device, a correction control circuit that adjusts the time according to the state of the auxiliary counter, and a correction command to the correction control circuit. The electronic timepiece is equipped with a return-to-zero switch that provides a second return-to-zero correction, and is characterized in that the return-to-zero switch also serves as a reset switch for an auxiliary counter.

The present invention will be explained in detail below with reference to the drawings.

FIG. 2 is a block diagram of an electronic timepiece with a zero return device according to the present invention, and the same numbers as in FIG. 1 indicate the same elements.

That is, the configuration of this embodiment omits the reset switch 22 in FIG. 1, and instead includes an operation signal switching circuit 30 for switching the operation signal of the zero return switch 21, and this operation signal switching circuit. 30 is provided with a timer circuit 35 for automatically returning it.

The operation signal switching circuit 30 includes an R3-FF 31 for storing correction operations and two AND gates 32 . ．． It is composed of 33, and 3
6 is an OR gate, and 37 is a waveform shaping circuit.

Further, the timer circuit 35 is composed of three or four flip-flops connected in series and one AND gate whose respective output terminals are input. It counts the periodic carry signals and generates a return signal at the output terminal Q after a certain period of time.

Next, the operation of this embodiment in the above configuration will be explained.

The clock mechanism composed of the reference oscillation circuit 1 and the hand movement display device 9 operates in the same way as in the case of FIG.
On the other hand, each element constituting the seconds return device is maintained in an unmodified state, and the operation signal switching circuit 30 is connected to the R8-FF31
Since it is in the reset state, only the AND gate 32 connected to its output terminal Q is turned on and maintained in the reset operation state.

In state 3, when the user operates the zero return switch 21 once when the second hand 9C of the hand movement display device 9 is at the zero second position, the signal output from the waveform shaping circuit 23 according to this operation changes to the operation signal switch. AND gate 3 configuring circuit 30
2 becomes a reset signal, which resets the auxiliary counter 11 and the timer circuit 35, and sets R8-FF 31 at a slightly delayed timing.

As a result, A connected to the output terminal circuit of R8-FF31
Only the ND gate 33 is turned on and the state is switched to the zero return operation state.

Furthermore, when the user operates the zero return switch 21 at the same time as the time signal or bulletin in this return operation state, the signal that can be output from the waveform shaping circuit 23 by this operation is output from the AND gate 33 that constitutes the operation signal switching circuit 30. By passing through, it becomes a correction signal, which resets the frequency divider circuit 2 and the reference counter 13, and also sets R8-FF16 to perform a zero return operation in the same manner as explained in FIG.

Then, at the end of the return-to-zero operation, the coincidence signal that resets R5-FF16 resets R8-FF 31 via OR gate 36 and waveform shaping circuit 37, thereby returning operation signal switching circuit 30 to the reset operation state.

Further, the operation signal switching circuit 30, which is switched to the zero return operation state by the first operation of the zero return switch 21, switches the operation signal switching circuit 30 to the zero return operation state if the zero return operation is not performed thereafter.
After a certain period of time, the output signal No. 5 returns to the reset operation state.

Therefore, the return to zero correction operation in the electronic timepiece is performed at a timing when the second hand 9C of the hand movement display device 9 is at the zero second position within a certain period of time before the time signal or bulletin that the user wants to correct. This is done by operating the return to zero switch 21 and then operating the return to zero switch 21 at the same time as the time signal or bulletin.

As described above, according to the present invention, a switch is provided that is linked to the only external operating member for performing zero return correction, and the first operation of this switch resets the auxiliary counter and simultaneously sets the zero return operation state. However, since the zero return correction is performed only when the switch is operated in the set zero return operation state, there is no need to provide a reset switch and its operating mechanism, and the reset switch is linked to the only external operating member. A zero return device can be configured by adding a zero return switch and some circuit elements, and
Since setting of the zero return operation state by the zero return switch and resetting of the auxiliary counter are performed simultaneously, accurate return to zero correction can be performed at all times.

Furthermore, even if the external operation member for returning to zero is operated by mistake when carrying the watch normally, the timer circuit will cancel the return to zero state after a certain period of time, which prevents time-related information from being destroyed due to incorrect operation. It has many effects such as:

Furthermore, in the embodiment of the present invention shown in FIG. During the period in which the second hand is in operation, the second hand 9C is
By adding an operation display such as simple intermittent hand movement in seconds steps, it is possible to provide an electronic timepiece with a zero return device that is easier for the user to use.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an electronic timepiece with a seconds return device, and FIG. 2 is a block diagram of an electronic timepiece with a seconds return device according to the present invention. 1...Reference oscillation circuit, 3...Signal switching circuit, 8...Pulse motor, 9...Hand movement display device, 11... Auxiliary counter, 12...
... Correction control circuit, 15 ... Delay/advance judgment circuit, 21 ... Return to zero switch, 30 ...
・Operation signal switching circuit.

Claims (1)

[Claims] 1. A correction control circuit that includes a reference oscillation circuit, a frequency dividing circuit, an electromagnetic converter, and a hand movement display device driven by the electromagnetic converter, and further adjusts the time according to the state of an auxiliary counter that is synchronized with the hand movement display device; and a correction operation storage means for storing a correction operation state by using an operation signal of the zero return switch as a switching signal in an electronic timepiece that includes a zero return switch that gives a correction command to the correction control circuit and performs second return zero correction. an operation signal switching circuit comprising: a switching gate controlled by the correction operation storage means for selectively supplying the operation signal to a reset terminal of the auxiliary counter and the correction control circuit; By providing a timer circuit for resetting the correction operation storage means after a certain period of time, the auxiliary counter is reset by the first operation of the zero return switch, and the second return to zero correction is performed by the second operation, and the correction operation is performed. An electronic clock with a zero return function, which is characterized by having an automatic return function from a state.