JPS6152957B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece having a plurality of switches, and particularly to a switch input control method.

In general, electronic watches obtain the time by counting the reference frequency of a crystal oscillator, etc., and display this using an electro-optical display device such as a liquid crystal or a light emitting diode. When performing this using a plurality of switches, an input control circuit for the switches is provided.

According to the conventional input control circuit, the normal display (hour and minute display) mode, month and day display mode, stopwatch mode, and
When a mode such as time correction mode is selected and the time is to be corrected, select the time correction mode using the mode changeover switch, select the element to be corrected using the selection switch, and then use the correction switch to select the time correction mode. A correction is made. To carry out the correction, a signal that advances by one step is output every time the correction switch is closed, and if the correction switch is kept closed for a certain period of time, a continuous step signal is output and the correction is performed. Furthermore, if there is no switch input for a certain period of time after all switches are opened, the mode automatically returns to the normal display mode. In order to carry out such an operation, the switch input control circuit has a large number of elements and becomes very complicated.

The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide an electronic timepiece in which the number of components of a switch input control circuit is significantly reduced. The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention,
1 is a mode control circuit, 2 is a switch input circuit, 3
is a frequency divider circuit, 4 is a reset circuit, 5 is an AND gate which is the first gate, and 6 is the second gate.
AND gate and 7 are OR gates which are prohibited gates.

The mode control circuit 1 is composed of a counter, a decoder, etc., and outputs mode control signals S ₁ to Sn corresponding to the number of openings and closings of the mode changeover switch SW ₁ , and outputs mode control signals S 1 to Sn corresponding to the number of openings and closings of the mode changeover switch SW 1, and selects hour/minute display mode, month/day display mode, and stopwatch mode. , and controls each circuit, such as a display circuit, in order to implement functions such as time adjustment mode. Further, when the mode control circuit 1 selects the time correction mode, the mode control circuit 1 selects a correction element by opening and closing the correction element selection switch _SW2 . On the other hand, switch
SW ₃ is a switch that executes corrections in the correction mode, and these mode changeover switches
The signals of SW ₁ , modification element selection switch SW ₂ and modification switch SW ₃ are applied to switch input circuit 2 . The switch input circuit 2 includes D type flip-flops 8, 9, 10 and AND gates 11, 12, 1.
3, consisting of a NOR gate 14 and an OR gate 15, and a D-type flip-flop 8, 9, 1
0 and AND gates 11, 12, NOR gate 14
forms a differential circuit controlled by clock pulse _OP1 . The outputs a, b, d of AND gates 11, 12 and NOR gate 14 are the corresponding switches.
Outputs a pulse when SW ₁ , SW ₂ , and SW ₃ are opened,
The output d of the AND gate 13 is a pulse when the switch _SW3 is closed. These outputs a, b,
c and d are applied to the reset terminal R of the frequency divider circuit 3 via the OR gate 15. The frequency divider circuit 3 has a plurality of flip-flops with reset terminals connected in cascade, and the input clock pulse _CP2 is applied via the inhibit gate 7.
By counting _CP2 , the closing time of switch _SW3 and the predetermined time after all switches _SW1 , _SW2 and _SW3 are opened are obtained. These times can be set to desired times by selecting the divided output of each stage. The AND gate 5 is applied with the divided outputs φ ₁ and φ ₂ that set the closing time of the switch SW ₃ , the signal M output from the mode control circuit 1 in the time correction mode, and the signal of the correction switch SW ₃ . , the output of AND gate 5 is applied to OR gate 7 and AND gate 6 to which clock pulse CP ₂ used as a correction pulse is applied. On the other hand, the frequency division output _φ3 is a switch
This signal determines the time since all of SW ₁ , SW ₂ and SW ₃ are opened, and this output φ ₃ is applied to the reset circuit 4 . The reset circuit 4 consists of an AND gate 16 to which the inverted signals of the switches SW ₁ , SW ₂ , SW ₃ and the output φ ₃ are applied, and a clock pulse CP _{1 .}
A D-type flip-flop 17 controlled by
AND gate 18, which differentiates the divided output _φ3 generated when all switches are open,
The mode control circuit 1 is reset by the pulse output from the output h of the AND gate 18, and returned to the normal display mode (hour and minute display mode).

Next, the operation will be explained with reference to timing charts shown in FIGS. 2 and 3.

First, the mode changeover switch _SW1 is opened and closed to put the mode control circuit 1 into the time correction mode. At this time, when switch SW ₁ is opened, switch input circuit 2 is opened.
A signal with the same pulse width as clock pulse CP ₁ is output from AND gate 11 output a, and OR gate 15
The frequency divider circuit 3 is reset via. The reset frequency divider circuit 3 starts counting the clock pulses _CP2 from the beginning, but before the predetermined time elapses and the frequency division output _φ3 is output, the selection switch _SW2 is opened and closed to select the correction element. do. When opening switch SW ₂ , AND gate 12 of switch input circuit 2
A differential pulse is output from the output b of the OR gate 15, and the output e of the OR gate 15 resets the frequency divider circuit 3, which is in the middle of counting, to an initial state. When the correction switch SW ₃ is closed within a predetermined time after the frequency divider circuit 3 starts counting again, a differential pulse is output from the output c of the AND gate 13 of the switch input circuit 2 at the time of closing, and the frequency divider circuit 3 starts counting again. It will be reset and counting will start from the beginning. Further, the differential pulse of the output c is transmitted from the output g of the OR gate 20 to the switch SW as a one-step correction signal via the AND gate 19 which is in a conductive state depending on the signal M output from the mode control circuit 1 in the correction mode. Applied to the modification element selected in _{step 2} .

If the correction switch SW ₃ remains closed, the frequency divider circuit 3 continues to count clock pulses CP ₂ ;
The time determined by the divided outputs φ ₁ and φ ₂ (Fig. 2
When the time indicated by _T1 has elapsed, the output f of the AND gate 5, which is enabled to conduct due to the signal M from the mode control circuit 1, goes to the "1" level. Based on this output f, the OR gate 7 cuts off the clock pulse _CP2 , and the frequency divider circuit 3 stops counting. Further, depending on the output f, the AND gate 6 makes the clock pulse _CP2 conductive, and the clock pulse is output from the output g of the OR gate 20.
CP ₂ is applied as a continuous step correction signal to the selected correction element to effect automatic feed correction.

Next, consider a case where all the switches are open, for example after correction is executed with correction switch SW ₃ in the time correction mode.

As mentioned above, close the correction switch SW ₃ , execute the correction, and when the desired correction value is reached, the correction switch
Open SW ₃ . At this time, switch input circuit 2
A differential pulse is output from the output d of the NOR gate 14, and is sent to the frequency divider circuit 3 via the OR gate 15.
is reset. Until the frequency dividing circuit 3 is reset, the clock pulse CP ₂ is cut off by the output f of the AND gate 5 and counting is stopped, or the counting is in the middle and the predetermined time T ₁ is not reached. be. When the frequency divider circuit 3 is reset, the output f of the AND gate 5 becomes "0" and the clock pulse _CP2 is applied to the frequency divider circuit 3 via the OR gate 7 to start counting. The fixed time, that is, the time until the divided output _φ3 is output, is shown in Figure 3.
Although it is indicated by T ₂ , T ₂ is set longer than the time T ₁ determined by the divided outputs φ ₁ and φ ₂ ,
The divided outputs φ ₁ and φ ₂ are output before the fixed time T ₂ elapses, but since the signal of the correction switch SW ₃ is applied to the AND gate 5 and the correction switch SW ₃ is open, The AND gate 5 is blocked and the output f does not block the clock pulse CP ₂ in the OR gate 7. Therefore, the frequency dividing circuit 3 continues counting and outputs the frequency divided output _φ3 for the time _T2 after being reset. The frequency-divided output _φ3 is applied to the AND gate 16 of the reset circuit 4, which is in a conductive state due to the inverted signals of the switches _SW1 , _SW2 , and _SW3 , and is controlled by the clock pulse _CP1 via the AND gate 16. It is differentiated by a D-type flip-flop 17 and an AND gate 18.
The differential output h of the AND gate 18 is applied to the reset terminal R of the mode control circuit 1, and the internal counter is reset to automatically return to the normal display mode.

In this way, the frequency divider circuit 3 has the function of detecting the closing time of the correction switch SW ₃ , and automatically displays the normal display if there is no other switch input for a certain period of time after all switches are opened. It also has the function of returning to the mode, so there is no need to provide a plurality of frequency dividing circuits 3, and the number of components can be reduced significantly.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are timing charts for explaining the operation of the embodiment shown in FIG. DESCRIPTION OF SYMBOLS 1... Mode control circuit, 2... Switch input circuit, 3... Frequency division circuit, 4... Reset circuit, 5...
...First gate, 6...Second gate, 7...Prohibition gate.

Claims (1)

[Claims] 1 It has a plurality of switches, a control circuit that selects a mode by one of the switches and controls each circuit, and a frequency divider circuit that counts a predetermined frequency and obtains the elapsed time, and has a function to reset the frequency divider circuit. A signal generated by opening/closing a switch related to correction among the plurality of switches and a signal generated when another switch is opened are applied to the terminal, and the first output of the frequency dividing circuit and the signal generated in the correction mode are output. A predetermined frequency applied to the frequency dividing circuit is controlled and corrected by an inhibit gate depending on the output of a first gate to which a signal from the control circuit indicating the closing of the switch related to the correction is applied. The frequency dividing circuit is controlled by controlling the second gate to which the signal is applied and further applying a second output having a longer period than the first output of the frequency dividing circuit to the reset terminal of the control circuit. ,
When a switch related to the correction is operated in the correction mode, it is detected that the operation is continued, a correction signal is sent from the second gate, and when all operations of the switch are completed. An electronic timepiece characterized in that the electronic timepiece detects that a predetermined time period has elapsed since the end of the operation and resets the control circuit.