JPS5952471U - 2-stage peak hold circuit - Google Patents
2-stage peak hold circuitInfo
- Publication number
- JPS5952471U JPS5952471U JP14634882U JP14634882U JPS5952471U JP S5952471 U JPS5952471 U JP S5952471U JP 14634882 U JP14634882 U JP 14634882U JP 14634882 U JP14634882 U JP 14634882U JP S5952471 U JPS5952471 U JP S5952471U
- Authority
- JP
- Japan
- Prior art keywords
- hold circuit
- peak hold
- stage peak
- peak
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Measurement Of Current Or Voltage (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のピークホールド回路の一例を示す構成図
。第２図は本考案によるピークホールド回路の一実施例
を示す構成図、第３図は第２図における第１のピークホ
ールド回路の他の実施例である。
２：第１のピークホールド回路、２ａ：トランジスタ、
２ｂ：負荷抵抗、２Ｃ：コンデンサ、２ｄ：抵抗、３：
第２のピークホールド回路、４：被ピークホールド信号
波形、５：第１のピークホールド回路の出力信号波形。FIG. 1 is a configuration diagram showing an example of a conventional peak hold circuit. FIG. 2 is a block diagram showing one embodiment of the peak hold circuit according to the present invention, and FIG. 3 is another embodiment of the first peak hold circuit in FIG. 2. 2: first peak hold circuit, 2a: transistor,
2b: Load resistance, 2C: Capacitor, 2d: Resistance, 3:
2nd peak hold circuit, 4: peak held signal waveform, 5: output signal waveform of the first peak hold circuit.
Claims (1)
路において、入力インピータンスが高くかつ出力インピ
ーダンスの低いエミッタホロア回路と、該エミッタホロ
ア回路の出力とアース間に接続したコンデンサとで構成
する第１のピークホールド回路及び該第１のピークホー
ルド回路の出力を入力にして信号のピーク値を検波し直
流電圧に変換する第２のピークホールド回路からなるこ
とを特徴とする２段ピークホールド回路。In a peak hold circuit that converts the peak value of a signal into a DC voltage, a first peak hold circuit is composed of an emitter follower circuit with high input impedance and low output impedance, and a capacitor connected between the output of the emitter follower circuit and ground. A two-stage peak hold circuit comprising a second peak hold circuit that receives the output of the first peak hold circuit, detects the peak value of a signal, and converts it into a DC voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14634882U JPS5952471U (en) | 1982-09-29 | 1982-09-29 | 2-stage peak hold circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14634882U JPS5952471U (en) | 1982-09-29 | 1982-09-29 | 2-stage peak hold circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5952471U true JPS5952471U (en) | 1984-04-06 |
Family
ID=30325779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14634882U Pending JPS5952471U (en) | 1982-09-29 | 1982-09-29 | 2-stage peak hold circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5952471U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2023080374A (en) * | 2019-10-23 | 2023-06-08 | 株式会社東芝 | Ringing detection circuit and power converter |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5128942B2 (en) * | 1972-12-20 | 1976-08-23 |
-
1982
- 1982-09-29 JP JP14634882U patent/JPS5952471U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5128942B2 (en) * | 1972-12-20 | 1976-08-23 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2023080374A (en) * | 2019-10-23 | 2023-06-08 | 株式会社東芝 | Ringing detection circuit and power converter |
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