JPS5951785B2 - Asynchronous reversible counter - Google Patents

Description

[Detailed description of the invention] In this invention, flip-flops are connected in cascade, and counting is performed by applying a counting input pulse only to the first stage of the flip-flops, making it possible to perform both addition and subtraction counting. This invention relates to an asynchronous reversible counter.

Conventional reversible counters have been limited to synchronous types for reasons described later.

In the synchronous reversible counter, for example, as shown in FIG. 1, flip-flops FF1 to FF4 are arranged in series, and a first gate G1 and a second gate G2 are respectively arranged between these adjacent flip-flops.

Each of the first gates G1 receives the Q outputs of all the flip-flops in the previous stage, and the second gate G2 receives the outputs of all the flip-flops in the previous stage.

Further, a rear count pulse is applied from a terminal 11 to each gate G1, and a down count pulse is applied from a terminal 12 to each second gate G2.

Between each flip-flop, the outputs of the first gate G1 and the second gate G2 are applied to the trigger terminal of the subsequent flip-flop through an OR gate G3.

An up-count pulse is applied to the trigger terminal of the first-stage flip-flop FF1 through an OR gate G3.

The figure shows the case where a preset counter is used, and the preset data input terminals D1 to D4 are connected to gates 64 to G, respectively.
7, the set side of flip-flops FF1 to FF4 and their inverted versions are connected to the reset side, respectively.

The gates 64 to G7 are controlled to open and close by a control signal from the terminal 13 to preset the states of the data terminals D to D4 to the flip-flops FF1 to FF4. I can say that.

111. is supplied to each of the flip-flop terminals T1 to T4, and each vehicle power I+ + '/ is supplied to each of the flip-flop terminals T1 to T4. -A is obtained at terminal 15 as a carry output from the middle of the bath.

Further, each flip-flop is performed, and the output thereof is obtained at the terminal 17 as a carry down output.

In this way, in the conventional synchronous reversible counter, the terminal 1
When an up-count pulse is applied to the flip-flop 1, this pulse is also applied to other flip-flops according to the opening/closing states of the first stage flip-flop lower F□ and the first gate G1 to perform up-counting.

When a down pulse is applied to the terminal 12, it is simultaneously applied to the trigger terminal of the flip-flops FF1 to FF4 to perform a down count depending on the open/closed state of the gate G2.

By the way, when this reversible counter is given a narrow input pulse near the resolution of F1 to FF4 under the flip flow rough, some will operate and others will not.

For example, when an input pulse is extracted by a gate, the width of the input pulse may be narrowed at both ends of the gate.

If only one such pulse is input, for example, if the states FF1 to FF4 of the flip-flops are 1111, they should all be 0, but due to variations in the operation of the flip-flops, they may become 0111 or 0011. etc., resulting in completely random counts.

In this case, if the flip-flops FF1 to FF4 are configured as one semiconductor integrated circuit as a one-digit counting section, it is also possible to make the resolutions of the flip-flops FF1 to FF4 the same.

However, when such counters are connected in cascade to count multiple digits, there is a risk that the resolution between the digits will vary, leading to erroneous counting.

Therefore, in the past, in order to prevent such narrow pulses from being given, consideration has been given to using a pulse separator to prevent pulses near the resolution from being given as counting pulses.

In an asynchronous counter, for example, as shown in the case of an up-counter in FIG. 2, the pulse from the input terminal 11 is applied only to the trigger terminal of the lower flip-flop F1 in the first stage, and each flip-flop FF1 to FF4 is connected to the previous stage. Q outputs are directly supplied to the trigger terminal T in sequence.

Therefore, if a pulse near the resolution of the flip-flop is given to the input terminal 11, the first stage flip-flop FF
1 is whether it operates or not, and only whether one pulse is counted or not, so the counted value will not be greatly deviated.

As shown in FIG. 3, the asynchronous down counter has flip-flops connected in series in such a way that the Q output of the previous flip-flop is directly applied to the trigger input of the next subsequent flip-flop.

In this case as well, when the width of the input pulse becomes narrow, the miscount is only 1 and does not deviate significantly.

By the way, if these asynchronous up counters and down counters are simply combined, the result will be as shown in FIG. 4, for example.

The first gate G1 and the second gate G1 are connected between adjacent flip-flops.
A gate G2 is arranged, the Q output of the flip-flop in the previous stage is inputted to the first gate G1, the Q output is inputted to the second gate G2, and the outputs of these gates G1 and G2 are input to the flip-flop in the next subsequent stage through the OR gate G3. to the trigger input T of the trigger.

According to the up/down switching control signal from the terminal 18, when it is at a high level, each first gate (G1) is opened, and when it is at a low level, each of the second gates (G2) is opened, thereby causing an up count and a down count, respectively. make it work.

With the configuration shown in FIG. 4, there is no problem if it is used only for up-counting or just down-counting.

However, when switching to up-count run 1 and down-counting from that count value, the outputs of the first gate) G A case may arise in which an effective trigger pulse is applied to the trigger terminal T.

Therefore, the counter shown in FIG. 4 cannot be used as a reversible counter.

From this point of view, conventionally only synchronous counters have been used as reversible counters.

The object of this invention is to provide an asynchronous method in which only one counting error occurs even when the width of the input pulse approaches the resolution of the flip-flop, and to switch between up-counting and down-counting during the counting operation. Another object of the present invention is to provide an asynchronous reversible counter that does not cause erroneous counting.

According to this invention, flip-flops are arranged in series,
A first gate and a second gate are respectively arranged between these adjacent gates.

If it is in one logic state, the first gate is opened and the Q of the previous flip-flop is
The output is given to the flip-flop in the subsequent stage, and the switching signal is applied to the flip-flop in the previous stage in other logic states.
The Q output of the door block is applied to the trigger input of the subsequent flip-flop, and a counting pulse is applied only to the first-stage flip-flop to form an up/down counter.

Furthermore, a register capable of storing and holding the contents of each flip-flop is provided, and the contents of each flip-flop are transferred to the register immediately before the up-down switching signal is switched, and after the up-down switching is performed. The contents transferred to the registers are returned to the respective flip-flops again.

In this way, malfunctions are prevented from occurring during up/down switching.

For example, as shown in FIG. 5, an asynchronous counter 21 is provided which counts the tarok signal at terminal 11.

This counter 21 performs up-counting or down-counting in response to an up-down switching signal from the terminal 18.

This switching signal 18 is also supplied to the control circuit 22, and before the switching signal 18 is generated, the contents of the reversible counter 21 are transferred to the register 23 through the control circuit 22, and after the switching by the switching signal is completed, the contents of the reversible counter 21 are transferred to the control circuit 22 again. through register 2
The contents of 3 are returned to the counter 21.

For example, in FIG. 6, parts corresponding to those in FIG. 4 are shown with the same reference numerals.

In this example, the counting flip-flops are trigger type flip-flops FF1 to FF1 with preset terminals.
FF4 is provided.

Gates G1, G between each adjacent flip-flop
2 are provided respectively, and an Otegenite G3 is further provided.

When the switching signal from terminal 18 is high level, gate G1
is opened and applied to the trigger terminal T of the subsequent flip-flop through the preceding flip-flop.

Further, when the switching signal from the terminal 18 is at a low level, the gate G2 is opened through the inverter 24, and the Q output of the flip-flop at the front stage is applied to the trigger terminal T of the flip-flop at the rear stage through the gates G2 and G3.

Terminal 1 is the trigger terminal of the first stage flip-flop FF.
A counting human pulse is given from 1.

In this way, the reversible counter 21 is configured.

A shift register is provided as a register 23 that temporarily stores the contents of the flip-flops FF1 to FF4 of this counter 21, and the contents of this shift register 23 can be set to the flip-flops FF1 to FF4, that is, can be preset. This is the case.

The shift register 23 includes each flip-flop FF1 to FF.
4, corresponding to 4 D-type flip-flops lower F5 to FF
8, which are connected in series.

The data terminal of the first stage flip-flop FF5 is connected to the input terminal 25, from which the data to be preset is input.

A shift pulse is also applied from the terminal 26 to the clock terminals of the flip-flops FF5 to FF8.

In the control circuit section 22, the pump flop FF1
~ Each Q output of FF4 passes through gates 27 to 30, and further passes through inverters 31 to 34 to preset terminals PS of F5 to FF8 under the flip flow rough of register 23.
given to.

These gates 27 to 30 are controlled to open or close by a control signal from a terminal 35.

Further, a signal from a terminal 36 is applied to timing signals 27-30 for transferring data.

Also, Fritsub syrup FF5 to FF8 each Q output is gate 3
7 to 40 and further to preset terminals PS of flip-flops FF1 to FF4 through inverters 41 to 44.

A store signal from a terminal 36 is also applied as timing to the gates 37 to 40, and a control signal from a terminal 35 is inverted and applied to the gates 37-40.

Furthermore, the counter column NOR signal is applied from the terminal 46 through the OR gate 47 and further through the inverter 48 to the reset terminal R of each of the flip-flops FF1 to FF4.

A reset signal from the terminal 49 is supplied to the register 47, and is also supplied to the reset terminals R of the flip-flops FF5 to FF8 of the register through an inverter 1.

For example, the reset pulse shown in FIG. 7A is generated at four terminals, which causes flip-flops FF1 to FF4 and F
F5 to FF8 are all reset.

Thereafter, as shown in FIG. 7B, a counting pulse is applied from the terminal 11, which is applied only for the period of the gate signal, for example, and is a so-called gated pulse.

At this time, for example, if the switching signal at the terminal 18 is at a high level as shown in FIG.

Depending on the normal counting operation state, the control signal from the terminal 35 is at a high level as shown in Figure 7.

If the next gated pulse from terminal 11 is to be used as a down-count, a store signal is applied to terminal 36 as shown in FIG. Level of Ma・
It is said that

Therefore, it is applied to flip-flops FF5 to FF8 through flip-flop 0, respectively, and its high level is set to a high level in the corresponding ones of flip-flops FF5 to FF8, respectively.

After the time t1, the switching signal at the terminal 18 is set to a low level as shown in FIG. , and a clear signal is applied to the terminal 46 as shown in FIG. 7F, so that the flip-flop F
F□ to FF4' are reset.

Further, after time t3, while the control signal at terminal 35 is at a low level, the store signal is again applied to terminal 36 as shown in FIG.

In the closed state, the gates 37 to 40 are opened, and the states of the lower flip flow roughs F5 to FF8 are the same, and the flip 70 knobs FF1 to FF are opened again through these gates.
Returned to 4.

After time t4, the control signal goes high.

Furthermore, after time t5, a count input is applied to the terminal 11 again, and a down count is performed from the count value at the previous up count operation.

In this way, before the up/down switching signal is switched, the counted value is saved in the register 23, and after the switching, the counted value is saved again? Since the counter is turned back, there is no possibility of erroneous counting due to up/down switching, and a reversible counter is constructed in an asynchronous manner.

To preset the date to this counter, use terminal 2.
After inputting the data to be preset from 5 into the shift register 23, the control signal at the terminal 350 is set to low level and the store signal is applied to the terminal 36 to transfer the contents of the flip-flops FF5 to FF8 to the flip-flops FF, -FF.
You can move it to 4.

It goes without saying that store signal control signals, clear signals, etc. can be easily created based on input signals, switching signals, etc.

Further, in the above description, the register 23 is required, but for example, the count value of a counter is often displayed, and in that case, a register is required, and the register can also be used.

Therefore, the configuration is not particularly complicated.

Furthermore, when the data is transferred to the register 23, processing such as adding the data transferred to the register 23 with other data can be performed and the data can be returned to the counter 21 again.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional synchronous reversible counter.
Figure 2 is a route map showing an asynchronous up counter, Figure 3 is a route map showing an asynchronous down counter, and Figure 4 is a route map showing an asynchronous down counter.
FIG. 5 is a block diagram showing the principle of the asynchronous reversible counter according to the present invention, and FIG. 6 is a logic circuit diagram showing an example of the asynchronous reversible counter according to the present invention. , FIG. 7 is a waveform diagram for explaining the operation. 21: Reversible counter, 22: Control circuit, 23: Register,
18 Near-sub-down switching signal input terminal, 35: Control signal input terminal, 36: Store signal input terminal, 46: Count clear signal input terminal.

Claims (1)

[Scope of Claims] 1. Flip-flops are arranged in series, and a first gate and a second gate are provided between adjacent flip-flops, and when one of the logic states of an up-down switching signal is applied, the first gate is switched on. 1- is opened and the Q output of the previous flip-flop is given to the trigger input of the subsequent flip-flop, and in other logic states, the Q output of the previous flip-flop is
The output is given to the trigger input of the subsequent flip-flop through the second gate, the counting pulse is given only to the trigger input of the first stage flip-flop, a register is provided that can store the contents of the flip-flop, and the up-down A change in the switching signal (at time E). Before that, the contents of each of the above flip-flops are transferred to the above registers, and then after the change of the switching signal, the contents of the above registers are returned to the flip-flops respectively, and the above contents are transferred to the above flip-flops. A control circuit for presetting is provided,
After the above preset: 1 of the above first stage flip-flop
~An asynchronous reversible counter that provides a counting pulse to the trigger input.