KR910001070B1 - Ring-counter circuit of three gata type - Google Patents

Abstract

The circuit uses 3 gates at every one-stage of the ring counter to form a flip-flop (FF) circuit. The FF circuit for one stage of the ring counter is formed by applying the outputs of a gate (G1) to a gate (G2); and a the gate (G2) one to the gate (G1). Another FF circuit is formed by appliing the outputs of G2 to a gate (G3) and the gate (G3) one to the G2. The data input terminal (IS), data output terminal (OR), data output terminal (OS), data input terminal (IR), output terminal of counter (Q), and input terminal of a counter (CK) are connected to the NAND or NOR gate so that the ring counter is comprised.

Description

3-gate ring counter circuit

1 is a conventional ring counter circuit diagram constructed using D-FF.

2 is an actual circuit diagram of the D-FF used in FIG. 1 (SN 7474).

3 is a block diagram of a ternary ring counter circuit of the present invention shown in blocks.

4 is a circuit diagram of the ternary ring counter of the present invention in which the second block of FIG. 3 is replaced with the actual circuit of the basic circuit of the present invention.

5 is a ternary ring counter circuit diagram of the present invention in which the second block of FIG. 3 is replaced with the actual circuit of the basic circuit of the present invention in which the connection diagram J of FIG. 7 is added.

6 is a basic circuit diagram of the present invention.

7 is a basic circuit diagram of the present invention in which a connecting line J is added.

8 is a self-starting binary ring counter circuit constructed using the basic circuit of the present invention.

9 is an application circuit diagram of the present invention in which one input NAND gate is added to the basic circuit of the present invention, in which connection line J is added, and the reset input and output terminals IR and OR are removed.

FIG. 10 is an application circuit diagram of the present invention in which one input NAND gate is added to the basic circuit of the present invention to remove reset input and output terminals IR and OR.

FIG. 11 is an application circuit diagram of the present invention in which a SW input terminal is provided after adding one NAND gate to the basic circuit of the present invention, in which connection line J is added. (When SW input is "0" (OPEN). Does normal ring counter operation, but when SW input is “1” (ON), it decreases the counter count of ring counter circuit once.)

FIG. 12 is an application circuit diagram of the present invention in which a SW input terminal is provided after adding one NAND gate and one buffer gate to the basic circuit of the present invention in which connection line J is added. If <OPEN> is set, normal ring counter operation is performed, but when SW input is "0", the counter count of ring counter circuit is reduced by one time.)

* Explanation of symbols for main parts of the drawings

CK: Clock pulse input terminal CLR: Clear input terminal

D: Input terminal of D-FF Q.Q: Output terminal of D-FF

QA-QC: Output terminal of conventional ring counter circuit

G1-G5: NAND gate used in the drawing

J: Connection line connecting the output of G3 to the input of G1.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to ring counter circuits, and more particularly to circuits capable of reducing the number of gates required in a ring counter circuit configuration to one half of the prior art. In the conventional method, when the ring counter circuit is constructed, a shift register (a register used to serially input parallel data) is used to rotate unique data "1" or "0". Since it is composed of -FF or JK FF (see Fig. 1), six gates were required for each stage of the ring counter circuit. (See Fig. 2). A three-gate ring counter configured by using the basic circuit of the present invention, showing the basic circuit of the present invention (which consists of three gates), which is a special FF circuit that can constitute a ring counter circuit with only three gates. By presenting the circuit, the circuit which improves the IC directivity and economics is presented.

The principle of the present invention will be described according to the accompanying drawings.

3 is a block diagram of the ternary ring counter circuit of the present invention shown in blocks, and the role and operation of each input / output terminal in the ring counter operation are as follows.

Q1: output terminal of 1 ring counter stage, Q2: output terminal of 2 ring counter stage, Q3: output terminal of 3 ring counter stage, OS: set data output terminal, IS: set data input terminal, OR: reset Data output terminal for IR, IR: Data input terminal for reset, Set: Operation of selecting one output terminal among the output terminals of a plurality of ring counters, Data: Bit "0" or Bit "1".

(1) If one more clock pulse is input to CK terminal while Q1 is set (Q1 is selected), set data comes out from OS1 (set data output terminal 1), and the set data is IS2 ( As input to the set data input terminal 2), Q2 is set (Q2 is selected) and reset data is output from OR2 (reset data output terminal 2). The reset data is IR1 ( It is input to the reset data input terminal 1, and the ring counter operation of the first stage is performed to reset Q1.

(2) If one more clock pulse is input to CK terminal while Q2 is set (selected), set data comes out from OS2 and Q3 is set (selected) because the set data is input to IS3. At the same time, the reset data comes out from OR3. When the reset data is input to IR2, Q2 is reset, and the second 1st ring counter operation is performed.

(3) If one more clock pulse is input to CK terminal while Q3 is set (selected), set data comes out from OS3, and the set data is input to IS1, so Q1 is set (Q1 is selected). At the same time, the reset data comes out from OR1, and the reset data is input to IR3, which resets Q3 so that the third ring stage operation is completed. This is done.

4 shows the operation principle of the ternary ring counter circuit of the present invention in which the second block of FIG. 3 is replaced with the actual circuit of the basic circuit of the present invention. (Since the circuit consists of NAND gates, the output of the selected terminal will be bit "0", and the counter will operate with a positive edge, which is made at the moment CK goes from "0" to "1".)

(1) Operation when "0" is set in Q1 (Q1 is selected) and CK is changed from "0" to "1": Set data "0" comes out in OS1 at the moment when CK becomes "1". The set data "0" causes G2 and G3 to be OPEN (the output of the gate becomes "1") via IS2, and the input "1" of G2 and the input of IR2 (Q3 is set (selected)). Since "1" is turned on, "1" turns on G1 (the output of the gate becomes "0"), and "0" is set in Q2 (Q2 is selected). By inputting data "0" into IR1 through OR2 to reset Q1, the first stage of counter counter operation is performed. The output "0" of OS1 which set Q2 above is for the period of CK is "1". G2 and G3 are kept open (otherwise, G1 opens G2 and G2 turns on G3, so that the set data "0" is output from OS2 immediately after Q2 is set. Haircut Because.)

(2) Operation when "0" is set (selected) in Q2 and CK changes from "1" to "0": The output of OS1 that kept "0" while CK is "1", As soon as CK is changed to "0", the output of OS1 is changed from "0" to "1" and input to IS2 so that G2 and G3 can perform FF operation (but strictly speaking, G2 and G3 are Full FF operation is allowed only for period of "1".)

(3) Operation when "0" is set (selected) in Q2 and CK changes from "0" to "1": CK changes to "1" and is input to G3 so that G2 and G3 operate FF. Since output "0" of G1 ("0" set in Q2) has opened G2, output of G2 is set to "1" and output of G1 is set to "0" so that CK is " FF is maintained for a period of 1 ", and the output of this G3 is" 0 "input to IS3 through OS2 as the set data, and the reset data output from OR3 at the same time that Q3 is set (Q3 is selected). As "0" is input to IR2, OPEN G1 is reset and Q2 is reset so that ring counter operation of 2nd step 1 is done. At this time, output "1" of OPEN G1 is input to G2, but already G2 and G3 Does not change the output of G2 and G3 because FF operation, CK keeps G3 as "0" for the period of "1" and inputs SI3 bit "0" through OS2. This makes it possible to prevent a malfunction (oscillation) in which the set data "0" is output from OS3 immediately after Q3 is set.

(4) Operation when "0" is set (selected) in Q3 and CK is changed from "1" to "0": When CK input becomes "0", G3 is open and the output of this G3 is When the connected G2 input is changed from "0" to "1", G1 and G2 operate FF. At this time, since the reset data "0" has already opened G1 via IR2, the output of G1 The output of "1" G2 is set to "0" so that FF operation is performed. (Although the output of OR3 is changed to "1" and input to G1 through IR2, the output of FF consisting of G1 and G2 is not changed.) And output "1" of OPEN G3 is input to IS3 through OS2. .

(5) Operation when "0" is set (selected) in Q3 and CK is changed from "0" to "1": CK is changed to "1" and input to G3, but output "0" of G2 is already G3. G3 is not turned on because it is input to. On the other hand, when CK changes to "1", the set data "0" is output from OS3 and input to IS1, while Q1 is set (Q1 is selected) and reset data "0" is output from OR1 and Q3 is reset. The third counter ring operation is performed.

(6) Operation when "0" is set in Q1 and CK is changed from "1" to "0": The output of OS3 that kept "0" is changed to "1" when CK is changed to "0". It is input to IS1.

5 is a ternary ring counter circuit of the present invention in which the second block of FIG. 3 is replaced with the actual circuit of the basic circuit of the present invention with the connection line J of FIG. Omitted to the role of the connection line J which is the difference between FIG. 4 (using the basic circuit of the present invention without the connecting line J added) and FIG. 5 (using the basic circuit of the present invention with the connecting line J added). Description only. The difference in operation with and without connection line J is in the process of resetting Q2.

First, in FIG. 4, when "0" is set (Q2 is selected) in Q2 and CK changes from "0" to "1", G3 is turned on, and the output "0" is set to OS2 as the set data. Q3 is set (selected) via IS3 and the reset data "0" is input to IR2 through OR3, and Q2 is reset. However, in FIG. 5, when "0" is set (selected) in Q2 and CK changes from "0" to "1", G3 is turned on and the output "0" of the G3 is directly connected via the connecting line J. Q2 is reset by opening G1. That is, in FIG. 4 circuit without connection line J, Q2 is reset after Q3 is set, and in FIG. 5 circuit with connection line J, Q2 is first reset before Q3 is set. have. (This operational feature would make the FIG. 5 circuit advantageously not duplicated and output in the encode operation.) FIG. 6 is named by the present applicant as the basic circuit of the present invention. Is divided into G2 and G3, the output of G2 is input to G3 and the output of G3 is input to G3 to form FF, the output of G2 is input to G1 and the output of G1 is input to G2 and another FF. The other input of G1 becomes input terminal IR, the output of G1 becomes output terminal Q and OR, the output of G3 becomes output terminal OS, and another input of G3 is input terminal CK. The operation is as follows.

First, the set data "0" is input to the IS, so that Q is set (selected) to "0", the reset data "0" is output from the OR, and the front end is reset. When the value is changed from 0 "to" 1 ", the set data" 0 "is output from the OS and the rear end is set, and the reset data" 0 "output from the rear end is input to the IR and Q is reset to" 1 ". In principle, it serves as a basic circuit of the present invention. (In addition, the basic circuit of the invention of FIG. 6 using the NOR gate is operated in the same principle. However, the input and output operate as the logic in which "0" and "1" are reversed in the above description. 7 is named by the present applicant as the basic circuit of the present invention, in which the connecting line J is added, and in the configuration form, J is connected to the basic circuit of the present invention and the output of G3 is inputted to G2. The basic operation is the same as that of Fig. 6, and only the operation of the connection J will be described as follows. When Q is set (selected) to "0", CK goes from "0" to "1" and G3 is turned on, and the output "0" of the G3 directly opens G1 to reset Q. The same operation is added to the operation of the basic circuit of the present invention of FIG. 6, and serves as the basic circuit of the present invention with the addition of the connection line J. (And this FIG. The basic circuit of the invention can also be configured as a NOR gate, of course, where the inputs and outputs also act as the logic in which " 0 " and " 1 " are reversed in the preceding description. As the self-starting binary ring counter circuit, the basic operation has been described above, and thus the role of G4 and G5 will be briefly described.

G4 is an AND gate to make CK "0" during clear operation to simplify the configuration of the CLR circuit. G5 is Q1 when Q1-Q4 detects "1" and CK changes from "0" to "1". It is to set (select) "0" to enable the self start ring counter operation.

9 is an application circuit of the present invention in which an input / output terminal IR and OR for reset are removed by adding one NAND (or NOR) gate to the basic circuit of the present invention in which connection line J is added. In the basic circuit of the present invention in which connection line J is added, the gate G6 (the two input terminals of G6 are connected to the input terminal IS and the output terminal of G1, respectively, and the output terminal of G6 is used as the IR input terminal. Is connected to the input terminal of G1.) The input / output terminals IR and OR for reset are removed, and the basic operation is the operation of the basic circuit of the present invention in which connection line J is added. (1) what constitutes this circuit at the expense of one more gate to obtain, (2) what can this circuit be included in the present invention, and (3) The role of the added gate G6 will be described.

(1) Although the basic circuit of the present invention is reduced to 1/2 of the conventional circuit in the number of gates in FIG. If you block the, it becomes more complicated. This may require a circuit that eliminates the input and output terminals IR and OR for reset, and will use this circuit at the expense of one more gate to obtain such a circuit. The effect that number becomes 2/3 of the conventional remains.)

(2) The following two things can be mentioned as a margin that this circuit can be included in the present invention.

First, the basic operation principle of IS, OS, CK, and Q in the basic circuit of FIG. 9 is not different from the present invention.

Secondly, in the basic circuit of FIG. 9, the connection line J, which is the characteristic of the basic circuit of FIG. 7, resets Q directly (see FIG. 7 and FIG. 5). Can be eliminated, so that the basic circuit of FIG. 9 can be constructed. That is, FIG. 9 can be regarded as an application circuit of the basic circuit of the present invention in which the connection line J of FIG. 7 is added (since one more gate is required).

(3) When there is no G6 in Fig. 9, the output of G3 becomes "0" (the output of G3 when Q changes from the set state to the reset state) and the output of G1 and G2 becomes "1" and then G3 The output of is changed to '1' again (the output of G3 when CK is changed from "1" to 0 after Q is reset) and it is input to G1 and G2 and G1 and G2 start FF operation at the same time. It is unpredictable, and normal ring counter operation is not performed.

In FIG. 9, the role of G6 is to input the output "1" of G1 when the output of G3 becomes "0", and input the output "0" back to G1 so that the output of G1 is "1". Set), so that even if the output of G3 changes to "1", the normal ring counter operation is performed.

On the other hand, as the set data "0" enters the IS, the output of G2 goes from "0" to "1" and the G6 and G2 start FF operation simultaneously, thus preventing the output of G6 and G2 from becoming unstable. One input terminal of G6 is connected to the IS to open the G6 (the output becomes "1").

FIG. 10 is an application circuit of the present invention in which a reset input / output terminal IR and OR are removed by adding one NAND (or NOR) gate to the basic circuit of the present invention. In the basic circuit of the invention, after the gate G7 (the three input terminals of G7 are connected to the output terminals of the input terminals CK, IS and gate G2, respectively, the output terminal is connected to the input terminal of G1 used as the IR input terminal), The input and output terminals IR and OR for the reset are removed. Since the basic operation is the same as the basic circuit operation of FIG. 6 of the present invention, the role of the added gate G7 will be omitted. If there is no G7 in FIG. 10, even if the output of G3 is changed to "0", G1 remains as "0" (set) and normal ring counter operation is not performed. After setting, CK changes from "0" to "1" and G7 outputs "1" of CK and input "1" of CK and G7 detects "0" (for reset) It is to make normal ring counter operation by inputting data).

Before describing FIG. 11, the role of the newly added input terminal SW in FIG. 11 and FIG. 12 will be described. 3 is a configuration diagram of a ternary ring counter circuit of the present invention, in which a switch (turn on or turn off a contact point on or off) a signal is installed at a second input terminal IS2 and a second output terminal OS2. Think about it. When the switch is in the open state, the ring counter circuit of FIG. 3 performs normal counter operation. However, when the switch is in the ON state, the set data "0" input to IS2 is directly input to IS3 by the switch circuit. The third block is set (selected) so that the ternary counter circuit performs a binary counter operation. (Hereinafter, this function is referred to as "counter exclusion switch function.") Likewise, the SW (SWITCH abbreviation) input terminal in FIG. 11 and FIG.

FIG. 11 shows the counter circuit switch function by adding an input terminal SW by adding one NAND gate to the basic circuit of the present invention in which connection line J is added to FIG. In the application circuit of the present invention with the function of reducing the function at once, the basic operation is the same as the basic circuit operation of the present invention in which the connection line J is added. do. In FIG. 11, when the input of the input terminal SW is in the state of " 0 " &lt; OPEN &gt;, G8 is opened, so that G8 does not operate at all and the ring counter circuit performs normal counter operation. However, when "1" (counter exclusion switch function ON) is input to the input terminal SW, G8 operates in the following order so that the number of counters can be reduced by one time than the normal counter number.

(1) When "0" is set (selected) in Q and CK is "0": G2 output terminal and input terminal "1" at input terminal SW are input to G8, but " Since 0 "is input, G8 does not cause any action.

(2) Operation when "0" is set (selected) in Q and CK changes from "0" to "1" state: Set data "0" comes out of OS when CK becomes "1" The next stage Q is set (selected). Then, the reset data "0" is inputted to G1 through IS to reset the Q at the next stage OR terminal. At this time, the output "1" of G1 and the output "1" of G2 OPEN by G3 and "1" of SW terminal are input to G8 and G8 is ON (output "0"), and the output of G8 " 0 "forcibly opens G3 and the output of OS is changed from" 0 "to" 1 "and is input to the next stage IS. Then, the next stage Q is reset again and the set data" 0 "is output from the next stage OS. As the second next stage Q is set, the next stage counter circuit is excluded from the counter operation, and the number of counters is reduced by one time. (The above description is for a circuit without the connecting line J. By the time reset data "0" is input to G1 via IR, G8 is already ON and it is time to open G3 (except the next stage from the counter).)

FIG. 12 is an application circuit of the present invention having a function of reducing the number of counters once from the normal counter by installing an input terminal SW by adding one NAND gate and one buffer gate to FIG. Since the basic operation is the same as that of the circuit of FIG. 7, the description thereof will be omitted and only the added gates G9 and G10 and the input terminal SW will be described. In Fig. 12, when the input of the input terminal SW is "1", G1 is not open, so the ring counter circuit operates normally. (When G3 is ON, G10 is opened by G3. And G2 output "1" is detected and the set data "0" is output to the OS. However, when "0" (counter switch ON) is input to the input terminal SW, G1 is forced to open. 1 ")," 0 "cannot be set in Q, and Q is not set (selected) even if the set data" 0 "enters the IS, and the main counter circuit is removed from the counter operation. Will be reduced. At this time, the role of G10 detects that the output of G2 is "1" when the set data "0" is input to the IS, and outputs "0" (set data) to the OS to follow the set data "0". Only to pass on. At this time, the role of G9 delays the output of G2 and inputs it to G10. When the main stage Q is set (when the input of SW is "1"), G2 delays the output by the delay time of G1 and inputs it to G10. This is to prevent the malfunction that G10 is ON.

There is another application method to the present invention, such that the counter output terminal Q connected to the output terminal of G1 can be obtained from the output terminal of G3. In this case, the set data output terminal OS and the counter output terminal Q can be used together, so that the circuit can be simplified, and the length of the set (selection) time can be changed to the CK (+) width as needed. As described above, since the basic circuit is composed of three gates, the number of gates can be reduced to one half of the conventional circuit, thereby realizing a circuit having high integration and economic efficiency.

Claims (5)

In the basic circuit that constitutes the first stage of the ring counter circuit, the output of G1 is input to G2 and the output of G2 is input to G1 to configure FF, the output of G2 is input to G3, and the output of G3 is input to G2. In the circuit that constitutes another FF, the set (selection) data input terminal IS connected to the input terminals G2 and G3, the reset data output terminal OR connected to the output terminal G1, and the The set data output terminal OS connected to the output terminal, the reset data input terminal IR connected to the input terminal of G1, the output terminal Q of the counter connected to the output terminal of G1, and the input terminal of G3. Even if the input terminal CK of the counter is NAND or NOR (various FFs composed of NAND gates are configured with NOR gates, they operate on the same principle with only the logic level of I / O changed. Because it becomes a gate.) It is made by using a gate, and is the basic of the ring counter basic circuit (Fig. 6 is a connection connected in the internal circuit of the basic circuit without conversion in the basic role of IS, OS, OR, IR, Q, CK in the basic circuit of the present invention. Also included is a basic circuit of a ring counter that is modified by adding a line and an input / output terminal connected to an external circuit of the basic circuit. The configuration according to claim 1, wherein a connection line J for connecting the output terminal of G3 and the input terminal of G1, which allows the main terminal Q to be reset first before the rear stage Q is set, is added by using a NAND or NOR gate. The basic role of the IS, OS, OR, IR, Q, CK in the basic circuit of the present invention in which the connection line J is added is not changed, but the internal circuit of the basic circuit does not change. Also included are ring counter circuits in which modifications are made by adding a connection line to be connected and an input / output terminal connected to the basic circuit. The reset mouth according to claim 1, wherein at least one gate or switch element (e.g., an all-optical diode) is added or inserted (cutting and inserting a circuit) in the configuration of claim 1, as in the example of FIG. A circuit characterized in that the application circuit of the present invention removes the output terminal IR and OR. 3. The application circuit of the present invention according to claim 2, wherein the input / output terminals IR and OR for reset are removed after adding or inserting one or more gates or switching elements to the configuration of claim 2, as in the example of FIG. A circuit characterized in that. The method according to claim 1 or 2 or 3 or 4, as in the example of the gates added in FIGS. 9, 10, 11, 12. A circuit comprising the application circuit of the present invention in which another function is added by inserting or adding one or more gates or switching elements to the configuration of claim 3 or 4. (The application circuit of FIG. 9 or FIG. 10 is shown in FIG. It can be obtained by adding G8 or G9 and G10 to the circuit of FIG. Or FIG. 10. <In the application circuit of FIG. 6 or 7 or 9 or 10, an application circuit having a gate or switching element inserted therein By cutting off between G2 connected to input terminal IS and G3 connected to G2, and adding AND gate or switching element there, application circuit with counter exclusion switch function can be obtained.

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