JPS5834654A - Logical integration circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit, by constituting a logical integration circuit for detecting a call and an end, which outputs a ''significant'' state, by use of an exclusive logical gate, when logical ''1'' or ''0'' has been continued exceeding a prescribed time. CONSTITUTION:When an octal counter CNT counts 8 clock pulses CK continuously, it generates an overflow pulse OVF, but when an input signal from a terminal IN and a signal of an output OUT of a flip-flop FF2 are on the same logical level, an output of an exclusive logical gate EOR becomes logical ''0'', and logical ''0'' is supplied to a terminal CE and R of the octal counter CNT, therefore, said counter CNT continuously holds its counting value at ''0''. In case when input pulse length applied to the input terminal IN is a call or end signal which continues exceeding an 8 piece portion of the clock pulse CK, however, the flip-flop FF2 is set (or reset) by the output OVF of the counter CNT, and to the terminal OUT, a significant pulse of logical ''1'' is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic integrator circuit that outputs 1 or 0 when logic 1s and 0s continue for N times, and attempts to reduce the number of elements used.

A logic integration circuit is used to cope with the instability of binary data during a transition period, or to remove all noise mixed in during transmission on the receiving side. For example, in a PCM telephone switching system, not only pulse code modulated voice signals are transmitted on the communication path, but also call origination and call termination signals are transmitted.
These are monitored by the switch's scanning mechanism, and a logic 1 causes a call to be sent.
A logical 0 is considered to be the end of the episode. At this time, the logic may temporarily become OK due to noise, etc., but if you respond immediately, the call will be judged to be over and the call path will be cut off. Therefore, if a logic 1 or 0 continues for a certain period of time, and the signal obtained by sampling in the scanning system is 1 or 0 consecutively for a predetermined number of times, then a call is initiated or terminated, the above-mentioned inconvenience occurs. can be avoided, and the logical integration circuit is effective for such applications. An example is shown in FIG. In the figure, SR is an N-bit, serial-in, balan-out shift register, and input (NR
Z signal) INf: Sequentially sampled and captured. A!
is an AND circuit with N inputs, and outputs ax'lrH only when the contents of register 7)1/8R are all at H (high) level.
Make it. Aya is also an N-input AND circuit, but since it has an inverter at the input end, the output becomes H only when the contents of the shift register SR are all at L (low) level. FF
Ike set reset.

And circuit A with 7 lips and 70 tubes! output a1 of
When becomes H, set il, %Q output 0UTtHK. On the other hand, AND circuit A! When the output signal becomes H, it is reset and the output OU'l is LIC'd. FIG. 2 is a signal waveform diagram of each part with N=8, and shows how the output OUT is inverted to that level only when the input IN maintains the same level for 8 consecutive bits. In other words, the input IN is 3
Part PI where only bits and bits are high or only one bit is low
The portion PI etc. where K has fallen are removed.

However, in the circuit shown in Fig. 1, in order to have an integration time for N cycles, a shift register SR of N bits is required, and two N inputs (As +
Since Am is required, the number of elements is large, and the circuit configuration at the element level becomes complicated.

The present invention improves this point and reduces the overall number of components by sharing circuits having the same type of logic integration function. The logic integration circuit of the present invention includes an N-ary counter that counts black and white pulses, and a flip-flop that inverts an output signal every time it receives an overflow pulse from the counter.
The counter is reset by an input signal and a distributed output, and the mismatched output of the circuit is inputted to the counter as the clock signal and the clock signal. This will be explained below with reference to the illustrated embodiment. Explain in detail.

FIG. 3 shows an embodiment of the present invention, in which EOR is an exclusive OR circuit, CNT is an N-ary counter, and FF is a J-type 7
It's a lip flop. This flip-flop, FIFI
, the overflow pulse Ov from the counter CNT in the previous stage
F is the output Q' each time it is applied to the coupler terminal cp.
ft: Invert. This output Q is the output signal OUT, which, together with the input signal IN, becomes the dual power of the exclusive OR circuit FOR. Every time the count value of the N-ary counter CNT reaches N, an overflow pulse OVF is generated. For example, N=
If it is 8, the counter CNT is composed of a binary counter of 3 bits and
When counting, an overflow pulse OVF is generated (see FIG. 4, the same applies hereinafter). However, the counter CNT
is capable of counting clocks and CKs only while the count enable terminal CE is receiving H input, and returns the count value to 0 if the count reset terminal R reaches Hv level during counting. This counter is controlled by the exclusive OR circuit EOR, and during the period when the input IN and output OUT match, the reset terminal RIH (the output level of EOR is L
This is inverted at the stage before terminal R), and the count value is kept at 0. Conversely, when the input IN and output OUT do not match, the EOR output (cg large input becomes H) and the counter CNT starts counting.Then, when the count value N=8, a full overflow pulse OvF is generated.As a result, the flip-flop, , is inverted, the output OUT becomes the same level as the input IN, the IOR output becomes L, and the counter C
NT is reset.

According to this logic integrator circuit, at the same time as shown in FIG. 2, at the input IN, the counter C is
Pulse O because the NT count value only rises to ``3'' and it is dangerous.
VF does not occur. Also, the part P where only 1 bit and G fall to L
2, the count value of the counter CNT is reset only when it becomes "1", and even if N=8, in the case of Fig. 1, it is 8.
While a bit shift register SR is required, a 3-bit counter CNT is sufficient in this example. Also, the gates in Figure 1 are eight-man powered gates A and A! In this example, only one FJOR is required for a two-person game). As described above, the logic integration circuit of the present invention may require a small number of constituent elements, but this tendency becomes more noticeable as the N value increases. For example, if N=50, the shift register S in Figure 1
Although R requires 50 bits, 6 bits is sufficient for the counter of the present invention (can cover up to N=64).

One of the reasons for the simplicity of the circuit of FIG. 5 compared to the circuit of FIG. 1 is the use of FOR gates. In other words, in Figure 1, the case where logic 1 continues and the case where logic 0 continues are game) AI F
Although they are detected separately by AI, in FIG. 3 they are detected using a logic that is a different state from the current state, so the detection means can be shared for logics 1 and 0.

Since a counter is used as a substitute for the M9 shift V register,
The number of elements can be reduced from °N to n bits, where 2n=N.

Note that the flip-flop and FF may be of D type, and in this case, the output is inverted and the overflow pulse of the counter CNT is input to the input circuit by crossing and turning (although this is actually nothing but a J-KFF).

As described above, according to the present invention, it is possible to reduce the number of constituent elements of a logic integration circuit, and this invention is effective to a large extent when the integration time (N value) is large.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional shift V register type logic integration circuit, Fig. 2 is a signal waveform diagram of each part thereof, Fig. 3 is a circuit diagram showing an embodiment of the present invention, and Fig. 4 is a circuit diagram of each part thereof. It is a signal waveform diagram. In the figure, CNT is an N-ary counter, FF is a J-type flip-flop, and EOR is an exclusive OR circuit. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi Figure 1 R Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] An N-ary counter that counts all black and white pulses, a flip-flop that inverts the output signal every time it receives an overflow pulse from the counter, and an exclusive OR circuit that uses two people to process the input signal and the output signal from the flip-flop. and the matching output of the circuit resets the color, and the mismatching output of the circuit is inputted to the counter as the black and white counters, among the input signals. A logical integrator circuit whose output is 1 when N 1's or 0's continue and 0 otherwise.