JPS5950529A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5950529A JPS5950529A JP16200582A JP16200582A JPS5950529A JP S5950529 A JPS5950529 A JP S5950529A JP 16200582 A JP16200582 A JP 16200582A JP 16200582 A JP16200582 A JP 16200582A JP S5950529 A JPS5950529 A JP S5950529A
- Authority
- JP
- Japan
- Prior art keywords
- film
- etching
- resist
- semiconductor wafer
- resist film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000001020 plasma etching Methods 0.000 claims abstract description 7
- 235000012431 wafers Nutrition 0.000 abstract description 23
- 238000000059 patterning Methods 0.000 abstract 1
- 238000005520 cutting process Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 206010011732 Cyst Diseases 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は半導体装置の製造方法に係り、特に半導体ウェ
ーハ上に被膜を形成し、該被膜上にレジスト膜を設けて
パターン形成を行うウェーハ処理工程の該パターン！の
小領域のみのレジスト膜をエツチング除去する方法の改
善に関する。Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular to wafer processing in which a film is formed on a semiconductor wafer and a resist film is provided on the film to form a pattern. The pattern of the process! The present invention relates to an improvement in a method for etching away a resist film from only a small area.
（ｂ） 技術の背景
集積回路半導体素子の高密度、高速度化が急速に進展し
ている中で、微細パターン形成に対する制御性はその重
要度を非常に増しつつある。(b) Background of the Technology As the density and speed of integrated circuit semiconductor devices are rapidly increasing, the controllability of fine pattern formation is becoming extremely important.
（ｅ） 従来技術と問題点
そのため製造単位、即ちあるロットをパターン形成のエ
ツチングをする際には 先行テスト（パイロット〕を該
ロット（本体）円から数枚の半導体ウェーハを選び母体
の処理条件をイ１（ＫＨ−ａ−ることか通常行われてい
るつと記ウエーハエツチング工程においては、拡散工程
、フォトプロセス工程等の各ロフト間の微少な変動に対
処才るｔコめに該ロット本体のエツチング処理に先か（
〕て、パイロットにより適切と思われる条件で、半導体
ウェー／Ｓ上に被膜を形成し、該被膜上に形成されたレ
ジスト°パターン膜をマスクとして該被膜を選択的にエ
ツチングし、次いで前記レジストマスクＭを全曲剥離し
て半導体ウェーハのエツチング後の状態、即ちパターン
の切れ具合、パターン幅等を測定又は観察し、ロフト本
体のエツチング後件の微調整を行なっている。(e) Conventional technology and problems Therefore, when etching a manufacturing unit, that is, a certain lot, to form a pattern, a preliminary test (pilot) is carried out by selecting several semiconductor wafers from the lot (main body) circle and checking the processing conditions of the base material. A1 (KH-a) In the wafer etching process that is usually performed, it is necessary to deal with minute variations between lofts such as the diffusion process and the photo process process. Before the etching process (
] A film is formed on the semiconductor wafer/S under conditions deemed appropriate by a pilot, and the film is selectively etched using the resist pattern film formed on the film as a mask, and then the resist mask is etched. M is completely peeled off and the state of the semiconductor wafer after etching is measured or observed, ie, the degree of pattern cutting, pattern width, etc., and fine adjustments are made to the etching condition of the loft body.
しかしながらパイロットは１回だけで最適条件を設定出
来るとは限らず複数回を要する場合もあり、この各層ご
とにパイロットを設けたのでは微調整の行われた最適条
件でエツチングされるロット本体のウェーハ枚数が著し
く減少する。又Ｍ、Ｏ８（７）ＥＰＲＯＭに用いられる
セルフ・アライメント構造のエツチングを行った場合に
おいては一層目のエツチングパイロットは完全に不良と
なり歩留低下の原因となる。そこで前記レジストパター
ン膜の所要部分を選択的に除去する方法としてイオンビ
ームエツチング（１，Ｂ、Ｅ）を用いる方法が考えられ
るが、１ｉｌＥは一度に使えるビームが一本で複数ケ所
をエツチングする場合には時間がかかり又下地との選択
比、損傷などの間、同点が発生する。However, it is not always possible to set the optimum conditions by piloting only once, and it may be necessary to set the pilot several times.If pilots are provided for each layer, the wafers of the lot body will be etched under the finely adjusted optimum conditions. The number of sheets decreases significantly. Furthermore, when etching the self-alignment structure used in the M, O8(7) EPROM, the etching pilot in the first layer becomes completely defective, causing a decrease in yield. Therefore, a method using ion beam etching (1, B, E) can be considered as a method of selectively removing the required portions of the resist pattern film, but 1ILE is a method in which only one beam can be used at a time to etch multiple locations. It takes time and ties occur due to selectivity with the substrate, damage, etc.
（ｄ） 発明の目的
本発明の目的はかかる問題点を解消して能率及び製造歩
留の向上、かつ高信頼性の製品を製造することのできる
半導体装置の製造方法の提供にある。(d) Object of the Invention An object of the present invention is to provide a method of manufacturing a semiconductor device that can solve the above problems, improve efficiency and manufacturing yield, and manufacture highly reliable products.
（ｅ） 発明の構成
即ち本発明は半導体ウェーハ上に被膜を形成し該被膜上
にレジスト膜をパターニング形成し該レジスト膜をマス
クとして該被膜を選択的にエツチングした後、該１／シ
スト膜にプラズマエッチングガスを噴射して該レジスト
膜を選択的に除去する工程が含まれでなることを特徴と
している。(e) Structure of the invention That is, the present invention forms a film on a semiconductor wafer, patterns a resist film on the film, selectively etches the film using the resist film as a mask, and then etches the 1/cyst film. The method is characterized in that it includes a step of selectively removing the resist film by spraying plasma etching gas.
（ｆ） 発明の実施例
以下本発明の笑施例について第１図及び第２図に示す本
発明の一実施例の工程要部断面図を用いて詳細に説明す
る。なお前回と同等部分については同一符号を付しでい
る。(f) Embodiments of the Invention Hereinafter, embodiments of the present invention will be described in detail using sectional views of main steps of an embodiment of the present invention shown in FIGS. 1 and 2. Note that parts that are the same as the previous version are given the same reference numerals.
第１図において半導体ウェーハ１．」二に被膜２を形成
し、該被膜２上に所定厚のレジスト膜を全曲に被覆し通
常のフォトプロセスによってパターンニングを行い、所
望のレジストパターン膜３を形成し、次いで上記レジス
トパターン膜３を具備してなる半導体ウェーハ本体より
、パイロット用１として半導体ウェーハ１を所定数選び
、適切と思われる条件で半導体ウェーハ１上の被１１※
１２七に形成されたレジストパターン膜３をマスクとし
て該被膜２をエツチングする。次いで第２図に示すヨ・
）ニ該被膜２上の所定箇所の小領域４のみのレジストパ
ターンｌｌＮ３を後述するプラズマ処理装置によって除
去し、該被膜２のエツチング後の状態、即ちパターンの
切れ具合、パターン幅Ｊ・等を測定又は観察し、例えば
エツチングが不足の場合には同一ウェーハをＦ［エツチ
ングして前記小領域４の横の所定個所を上述した方法を
繰返して最適条件を決定する。このようにすれば新しい
半導体ウェーハを消耗することなく又パイロット半導体
ウェーハ１上の全ブーツブが不良になることなく最適条
件の設定が可能となる１、第３図は本発明の一実施例に
用いるプラズマ処理装置１０の模式的断面図を示してい
る。同図において先ずパイロット用としてエツチングさ
れた半導体ウェーハ１１を処理室１２内の載置台１３上
に固定し、モーター１４及びセンサー１５によって所定
位置にセットする。In FIG. 1, a semiconductor wafer 1. ``Secondly, a film 2 is formed, a resist film of a predetermined thickness is coated on the entire surface of the film 2, and patterned by a normal photo process to form a desired resist pattern film 3; Select a predetermined number of semiconductor wafers 1 as pilot 1 from a semiconductor wafer body comprising a
The film 2 is etched using the resist pattern film 3 formed at 127 as a mask. Next, as shown in Figure 2,
) D. Remove the resist pattern LLN3 of only a small region 4 at a predetermined location on the film 2 using a plasma processing device to be described later, and measure the state of the film 2 after etching, that is, the degree of cutting of the pattern, the pattern width J, etc. Alternatively, if the etching is insufficient, the same wafer is subjected to F[etching, and the above-described method is repeated at a predetermined location beside the small region 4 to determine the optimum conditions. In this way, it is possible to set the optimum conditions without wasting new semiconductor wafers or without all bootstubs on the pilot semiconductor wafer 1 becoming defective. 1 and 3 are used in one embodiment of the present invention. A schematic cross-sectional view of a plasma processing apparatus 10 is shown. In the figure, first, a pilot etched semiconductor wafer 11 is fixed on a mounting table 13 in a processing chamber 12 and set at a predetermined position by a motor 14 and a sensor 15.
次いで処理室１２の上部開口部の所定位置（こ遮蔽板１
６をセットする。該遮蔽板１６には予め前記半導体ウェ
ーハ１１上に形成された被膜上のレジストパターン膜を
除去すべき小領域に対応する開口径約２ Ｑ ｌｔ ｍ
のノズル１７が設けられ“Ｃいる。Next, the shielding plate 1 is placed at a predetermined position in the upper opening of the processing chamber 12.
Set 6. The shielding plate 16 has an opening diameter of about 2 Q lt m corresponding to a small area from which a resist pattern film on a film previously formed on the semiconductor wafer 11 is to be removed.
A nozzle 17 is provided.
次いで排気１」１８より真空排気しガス導入管１９より
０．＋ＣＩ’”４（２０％ンの混合ガスを導入してプラ
ズマ発生室２０の輿望反を約１．０１’＋ｌ ｒ ｒ
、処理室１２は約１０ ”、Ｉ’ｏｒｒ になるよ
うに調が（くする。Next, the vacuum is evacuated from the exhaust 1" 18, and the gas is evacuated from the gas introduction pipe 19. +CI'''4 (by introducing 20% of the mixed gas, the pressure of the plasma generation chamber 20 is approximately 1.01'+l r r
, the processing chamber 12 is tuned to about 10'', I'orr.
の混合ガスに作用してプラズマを発生し、該プラズマエ
ツチングガスがノズル１７を介してヒーム状に形成され
直進し、ラジカルを主体としｊこエツチングガスによっ
て半導体ウェーハ１１−にの所１７．！の小領域のレジ
ストパターン膜のみを除去する、。The plasma etching gas acts on the mixed gas of 17 to generate plasma, and the plasma etching gas is formed into a heam shape and travels straight through the nozzle 17, and the etching gas, which mainly consists of radicals, is applied to the semiconductor wafer 11- at 17. ! Only a small area of the resist pattern film is removed.
該エツチング除去方法は物理的エツチングを主体とした
イオンエツチングに比ベラジカルを主体とした化学的エ
ツチングに、Ｌる１こめ半導体ウエ−ノ＼１１の損傷が
ｌｃ＜かつ選択比を人き（とれる長所を有している。This etching removal method has the advantage that damage to the semiconductor wafer is less than lc and the selectivity is higher than that of chemical etching, which is mainly based on radicals, compared to ion etching, which is mainly based on physical etching. have.
（ｇ） 発明の詳細
な説明しｔこように本発明によればメミ圧を利用し、所
定のノズルを通じてヒーム状に絞ったラジカルを主体と
したプラズマエツチングガスを噴射してｌＣるプラズマ
処理装置によつ−Ｃ所望の小頭域のレジストパター ン
膜のみを一度にエツチング除去するが可能となり、又ロ
ット本体の半導体ウェーハを著しく減することなく能率
向上、歩留向上の大きな効果があり、かつラジカルを主
体とした化学的プラズマエツチングによつ−Ｃ１Ｆ地の
損傷選択比の改善による信頼性の向上にも効果がある。(g) Detailed explanation of the invention As described above, according to the present invention, a plasma processing apparatus performs LC by injecting a plasma etching gas mainly composed of radicals squeezed into a heel shape through a predetermined nozzle using Memi pressure. It is possible to remove only the resist pattern film in the desired small head area by etching at one time, and it has the great effect of improving efficiency and yield without significantly reducing the number of semiconductor wafers in the lot body. Furthermore, chemical plasma etching mainly consisting of radicals is effective in improving reliability by improving the damage selectivity of the -C1F substrate.
第１図および第２図は本発明の一実施例の工程要部断面
図、第３図は本発明の一実施例に用いるプラズマ処理装
置の模式的断面図である。
図において１．１１は半導体ウェーハ ２は被膜、３は
レジストパターン膜、４は小領域、１７はノズルを示す
。
第１図
□１
第３図
−＋
第３図
、２
１
３
２
１FIGS. 1 and 2 are sectional views of essential parts of a process according to an embodiment of the present invention, and FIG. 3 is a schematic sectional view of a plasma processing apparatus used in an embodiment of the present invention. In the figure, 1.11 is a semiconductor wafer, 2 is a coating, 3 is a resist pattern film, 4 is a small region, and 17 is a nozzle. Figure 1□1 Figure 3-+ Figure 3, 2 1 3 2 1
Claims (1)
膜をパターニング形成し、該レジスト膜をマスクとして
該被膜を選択的にエツチングしｔこ後、該レジスト膜に
プラズマエツチングガスを噴射して該レズスト膜を選択
的に除去する工程が含まれてなることを特徴とする半導
体装置の製造方法。A film is formed on a semiconductor wafer, a resist film is patterned on the film, the film is selectively etched using the resist film as a mask, and then a plasma etching gas is injected onto the resist film to remove the etching. A method for manufacturing a semiconductor device, comprising a step of selectively removing a resist film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16200582A JPS5950529A (en) | 1982-09-16 | 1982-09-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16200582A JPS5950529A (en) | 1982-09-16 | 1982-09-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5950529A true JPS5950529A (en) | 1984-03-23 |
Family
ID=15746226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16200582A Pending JPS5950529A (en) | 1982-09-16 | 1982-09-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5950529A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62274727A (en) * | 1986-05-23 | 1987-11-28 | Hitachi Tokyo Electron Co Ltd | Processsor |
-
1982
- 1982-09-16 JP JP16200582A patent/JPS5950529A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62274727A (en) * | 1986-05-23 | 1987-11-28 | Hitachi Tokyo Electron Co Ltd | Processsor |
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