CN113451123A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN113451123A CN113451123A CN202010211167.8A CN202010211167A CN113451123A CN 113451123 A CN113451123 A CN 113451123A CN 202010211167 A CN202010211167 A CN 202010211167A CN 113451123 A CN113451123 A CN 113451123A
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises a central area and a crystal edge area surrounding the central area; forming a target graphic layer on a substrate, wherein the target graphic layer positioned in a central area is a device target graphic layer, and the target graphic layer positioned in a crystal edge area is a pseudo target graphic layer; doping ions in the pseudo target pattern layer to form a doped pattern layer, wherein the etching difficulty of the doped pattern layer is smaller than that of the target pattern layer of the device; and removing the doping pattern layer. In the embodiment of the invention, ions are doped in the pseudo target pattern layer in the crystal edge area to form a doped pattern layer, and the etching difficulty of the doped pattern layer is less than that of the device target pattern layer; therefore, in the process of removing the doped pattern layer, the damage of the target pattern layer of the device is small, and the uniformity of the electrical performance of the semiconductor structure is improved.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In today's large scale integrated circuit fabrication, plasma dry etching is the basic process for pattern transfer. Are commonly used to form the desired pattern in a semiconductor device layer, such as etching of a top metal layer. In etching, a mask pattern is usually formed on a metal layer to be etched by photolithography (photolithography), which is a process for removing a specific portion of a thin film on a wafer surface through a series of production steps, to protect the metal pattern to be remained. After that, a film with a micro-pattern structure is left on the wafer surface. Through the photolithography process, what remains on the wafer is ultimately the feature pattern portion.
The standard process method for forming the mask pattern by photoetching comprises the following steps: firstly, forming a photoresist pattern layer on a metal layer; then Soft Baking (Soft Baking) is carried out for the purpose of removing the solvent, enhancing the adhesiveness, releasing the stress in the photoresist film and preventing the photoresist from contaminating the equipment; removing Edge photoresist, wherein the photoresist is accumulated on the front surface and the back surface of the Edge of the silicon wafer after the photoresist is coated, the photoresist on the Edge is generally not uniformly spin-coated, a good pattern cannot be obtained, and stripping (Peeling) is easy to occur to influence the patterns of other parts, so the photoresist needs to be removed; or, using a Wafer Edge Exposure (WEE), after completing the Exposure of the pattern, exposing the Edge of the silicon Wafer with laser to remove the Edge photoresist.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the uniformity of the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a central area and a crystal edge area surrounding the central area; forming a target graphic layer on the substrate, wherein the target graphic layer positioned in the central area is a device target graphic layer, and the target graphic layer positioned in the crystal edge area is a pseudo target graphic layer; doping ions in the pseudo target pattern layer to form a doped pattern layer, wherein the etching difficulty of the doped pattern layer is smaller than that of the device target pattern layer; and removing the doping pattern layer.
Optionally, ions are doped in the pseudo target pattern layer by using a crystal edge plasma process or a ribbon ion beam implantation process to form the doped pattern layer.
Optionally, doping ions in the pseudo target pattern layer by using a crystal edge plasma process; the technological parameters of the crystal edge plasma process comprise: the reaction gas includes one or more of Ar, H2, N2 and He, the chamber pressure is 500mtorr to 2000mtorr, the source power is 100W to 1000W, the bias power is 15W to 200W, and the process time is 10 seconds to 300 seconds.
Optionally, doping ions in the pseudo target pattern layer by using a ribbon ion beam implantation process; the technological parameters of the ribbon ion beam implantation technology comprise: the dopant ions include one or more of Ar, H, B, P, and As, with a dopant amount of 1E13 atoms per square centimeter to 1E15 atoms per square centimeter, and an implant energy of 10kev to 200 kev.
Optionally, the method for forming the semiconductor structure further includes: forming a target pattern layer on the substrate, and forming a shielding layer covering the central region and exposing the crystal edge region before doping ions in the pseudo-target pattern layer; the method for forming the semiconductor structure further comprises the following steps: and removing the shielding layer after removing the doping pattern layer.
Optionally, in the step of providing the substrate, a direction from the center of the central region to the edge region is taken as a radial direction, and a dimension of the edge region in the radial direction is less than 2 mm.
Optionally, in the process of removing the doping pattern layer, an etching selection ratio of the doping pattern layer to the device target pattern layer is greater than 3, and an etching selection ratio of the doping pattern layer to the substrate is greater than 3.
Optionally, the step of forming a target pattern layer on the substrate includes: forming a target material layer on the substrate; forming a photoresist material layer on the target material layer; carrying out patterning treatment on the photoresist material layer to form a photoresist layer; and etching the target material layer by taking the photoresist layer as a mask, wherein the residual target material layer is taken as the target pattern layer.
Optionally, the step of forming the photoresist layer further includes: and carrying out photoresist edge repairing treatment on the photoresist material layer.
Optionally, the doped pattern layer is removed by a wet etching process.
Optionally, the etching solution used in the wet etching process includes: a mixed solution of hydrofluoric acid, nitric acid and acetic acid, or a diluted hydrofluoric acid solution.
Optionally, the doping pattern layer is removed by using a remote plasma etching process.
Optionally, the target graphics layer includes: one or both of silicon oxide and silicon nitride.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate comprising a central region and a bead region surrounding the central region; a device target graphics layer located in the central region of the substrate; and the doped pattern layer is positioned in the crystal edge area of the substrate, doped ions are arranged in the doped pattern layer, and the etching difficulty of the doped pattern layer is smaller than that of the target pattern layer of the device.
Optionally, the doping ions include one or more of Ar, H, B, P, and As; alternatively, the dopant ions comprise one or more of Ar, H, N and He.
Optionally, the doping concentration of the dopant ions in the doping pattern layer is 1E18 atoms per cubic centimeter to 1E20 atoms per cubic centimeter.
Optionally, a direction from the center of the central region to the edge region is taken as a radial direction, and a dimension of the edge region in the radial direction is less than 2 mm.
Optionally, an etching selection ratio of the doping pattern layer to the device target pattern layer is greater than 3, and an etching selection ratio of the doping pattern layer to the substrate is greater than 3.
Optionally, the material of the device target pattern layer includes: one or both of silicon oxide and silicon nitride.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming a semiconductor structure provided by the embodiment of the present invention, the substrate includes a central area and a crystal edge area surrounding the central area, the target pattern layer located in the central area is a device target pattern layer, the target pattern layer located in the crystal edge area is a dummy target pattern layer, and the step of forming the target pattern layer on the substrate generally includes forming a target material layer on the substrate, forming a photoresist layer on the target material layer, and etching the target material layer with the photoresist layer as a mask to form the target pattern layer, where the photoresist layer is generally formed by a spin coating process, and the formation quality of the photoresist layer in the crystal edge area is generally poor, which correspondingly results in poor formation quality of the dummy target pattern layer. In the embodiment of the invention, ions are doped in the pseudo target pattern layer in the crystal edge area to form a doped pattern layer, and the etching difficulty of the doped pattern layer is less than that of the device target pattern layer; therefore, in the process of removing the doped pattern layer, the damage of the target pattern layer of the device is small, and the uniformity of the electrical performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 7 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The semiconductor structure formed at present still has a problem of poor performance. The reason for the poor performance is analyzed in combination with a method for forming a semiconductor structure.
Fig. 1 to 6 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure.
As shown in fig. 1 and 2, fig. 2 is a cross-sectional view at aa of fig. 1, providing a base including a central region I and a bead region II surrounding the central region I (only the bead region II on one side of the central region I is illustrated in fig. 1), the base including an initial substrate 1 and a core material layer 2 on the initial substrate 1; a mask layer 3 is formed on the core material layer 2, wherein the mask layer 3 includes an organic material layer 31, an anti-reflective coating 32 on the organic material layer 31, and a photoresist layer 33 on the anti-reflective coating 32.
As shown in fig. 3 and 4, fig. 4 is a cross-sectional view at bb of fig. 3, and the photoresist layer 33 in the Edge region II is removed by using a photoresist Edge repair process (EBR).
As shown in fig. 5, the core material layer 2 is etched using the mask layer 3 as a mask to form a core layer 4.
As shown in fig. 6, a side wall material layer (not shown) is formed on the core layer 4 and the substrate exposed from the core layer 4; removing the side wall material layers on the top surface of the core layer 4 and the surface of the substrate 1, and taking the rest side wall material layers positioned on the side wall of the core layer 4 as side wall layers 5; after the formation of the side wall layers 5, the core layer 4 is removed.
The formation of the photoresist layer 33 generally includes: a photoresist material layer (not shown) is formed on the anti-reflective coating 32 by a spin coating process, and is exposed and developed to form a photoresist layer 33. In the process of forming the photoresist material layer by using the spin coating process, the redundant photoresist is pushed to the edge zone II by centrifugal force, most of the redundant photoresist is thrown away from the substrate, and a part of the redundant photoresist remains in the edge zone II, so that the photoresist in the edge zone II is rapidly solidified to form a bump (as shown in A in FIG. 1) due to the high relative speed of the airflow of the edge zone II. In the process of removing the bump by using the photoresist edge repairing process, back sputtering may occur, and a back sputtering body (as shown in fig. 3B) is formed in a partial region of the photoresist layer 33, and in the process of etching the core material layer 2 by using the mask layer 3 as a mask to form the core layer 4, the volume of the core layer 4 in the dashed-line frame formed by using the back sputtering body as a mask is too large, which accordingly causes a deviation between the position of the finally formed sidewall layer 5 in the dashed-line frame in fig. 5 and a preset position, resulting in poor formation of the finally formed semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a central area and a crystal edge area surrounding the central area; forming a target graphic layer on the substrate, wherein the target graphic layer positioned in the central area is a device target graphic layer, and the target graphic layer positioned in the crystal edge area is a pseudo target graphic layer; doping ions in the pseudo target pattern layer to form a doped pattern layer, wherein the etching difficulty of the doped pattern layer is smaller than that of the device target pattern layer; and removing the doping pattern layer.
In the method for forming a semiconductor structure provided by the embodiment of the present invention, the substrate includes a central area and a crystal edge area surrounding the central area, the target pattern layer located in the central area is a device target pattern layer, the target pattern layer located in the crystal edge area is a dummy target pattern layer, and the step of forming the target pattern layer on the substrate generally includes forming a target material layer on the substrate, forming a photoresist layer on the target material layer, and etching the target material layer with the photoresist layer as a mask to form the target pattern layer, where the photoresist layer is generally formed by a spin coating process, and the formation quality of the photoresist layer in the crystal edge area is generally poor, which correspondingly results in poor formation quality of the dummy target pattern layer. In the embodiment of the invention, ions are doped in the pseudo target pattern layer in the crystal edge area to form a doped pattern layer, and the etching difficulty of the doped pattern layer is less than that of the device target pattern layer; therefore, in the process of removing the doped pattern layer, the damage of the target pattern layer of the device is small, and the uniformity of the electrical performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 7 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
As shown in fig. 7, fig. 7 includes fig. 7(a) and 7(b), and fig. 7(b) is a cross-sectional view along EE in fig. 7(a), and provides a substrate 100, wherein the substrate 100 includes a central region I and a bead region II surrounding the central region I.
The substrate 100 is ready for subsequent formation of the bottom pattern.
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the central region I is used for preparing a subsequent formation of a device target pattern layer, and the edge region II is used for preparing a formation of a pseudo target pattern layer.
In the step of providing the substrate 100, a direction from the center of the central region I to the edge region II is taken as a radial direction, and a dimension of the edge region II in the radial direction is not required to be too large. If the size of the edge region II in the radial direction is too large, the ratio of the edge region II to the central region I is too large, and the effective region of the substrate for forming the semiconductor device is too small, which is not favorable for improving the yield of the semiconductor structure. In this embodiment, the size of the edge zone II in the radial direction is less than 2 mm.
Referring to fig. 8 to 10, a target pattern layer 101 (as shown in fig. 10) is formed on the substrate 100, the target pattern layer 101 located in the central region I is a device target pattern layer 1011, and the target pattern layer 101 located in the edge region II is a pseudo target pattern layer 1012.
The device target patterned layer 1011 is prepared for subsequent etching of the substrate 100; the pseudo target graphics layer 1012 is removed in a subsequent process.
The material of the target patterned layer 101 is different from that of the substrate 100, and in the corresponding subsequent step of etching the substrate 100 by using the device target patterned layer 1011 as a mask, the substrate 100 and the device target patterned layer 1011 have a larger etching selectivity.
Specifically, the material of the target pattern layer 101 includes: one or both of silicon oxide and silicon nitride. In this embodiment, the material of the target pattern layer 101 includes silicon nitride. The silicon nitride is a dielectric material with a common process and low cost, and has high process compatibility, thereby being beneficial to reducing the process difficulty and the process cost for forming the target pattern layer 101.
The step of forming the target patterned layer 101 on the substrate 100 includes: as shown in fig. 8, a target material layer 102 is formed on the substrate 100; forming a photoresist material layer 104 (not shown) on the target material layer 102; as shown in fig. 9, the photoresist material layer 104 is patterned to form a photoresist layer 103; as shown in fig. 10, the target material layer 102 is etched by using the photoresist layer 103 as a mask, and the remaining target material layer 102 is used as the target patterning layer 101.
In this embodiment, the target material layer 102 is etched by using the photoresist layer 103 as a mask and using a dry etching process, and the remaining target material layer 102 is used as the target patterning layer 101. The dry etching process has anisotropic etching characteristics and better etching profile controllability, is favorable for enabling the appearance of the target pattern layer 101 to meet the process requirements, and can take the top of the substrate 100 as an etching stop position in the etching process, thereby being favorable for reducing the damage to other film layer structures. In addition, the dry etching process can etch each film layer in the same etching equipment by replacing etching gas, thereby simplifying the process steps.
It should be noted that the photoresist material layer 104 is usually formed by a spin coating process, and during the process of forming the photoresist material layer 104, the excess photoresist material layer 104 is pushed to the edge of the edge zone II by a centrifugal force, most of the excess photoresist material layer is thrown off the substrate, and a part of the excess photoresist material layer remains in the edge zone II, and due to the relatively high speed of the gas flow in the edge zone II, the photoresist material layer 104 in the edge zone II is rapidly solidified to form a raised edge (as shown in E in fig. 8). Under the action of surface tension, a small amount of the photoresist material layer 104 flows to the back surface of the wafer even along the edge, and the back surface of the wafer is contaminated, and the photoresist material layer 104 is easy to peel off to affect the patterns of other parts or cause contamination.
It should be noted that an organic material layer 106 and a bottom anti-reflective coating 105 on the organic material layer 106 are further formed between the target material layer 102 and the photoresist material layer 104. In the process of etching the target material layer 102 by using the photoresist layer 103 as a mask, the organic material layer 106 and the bottom anti-reflection coating 105 are also etched.
In other embodiments, the step of forming a target patterned layer on the substrate further includes: and carrying out photoresist Edge repairing (EBR) on the photoresist material layer.
The photoresist edge repairing process utilizes a Propylene Glycol Methyl Ether Acetate (PGMEA) or Ethylene Glycol Methyl Ether Acetate (EGMEA) edge removing solvent to spray a small amount of photoresist material in the crystal edge area II, so that the photoresist material layer in the crystal edge area II can be removed.
Referring to fig. 11, ions are doped in the pseudo target patterned layer 1012 to form a doped patterned layer 107, and the etching difficulty of the doped patterned layer 107 is less than that of the device target patterned layer 1011.
The step of forming the target patterned layer 101 on the substrate 100 generally includes forming a target material layer 102 on the substrate 100, forming a photoresist layer 103 on the target material layer 102, and etching the target material layer 102 by using the photoresist layer 103 as a mask to form the target patterned layer 101, wherein the photoresist layer 103 is generally formed by a spin coating process, and the formation quality of the photoresist layer 103 in the edge region II is generally poor, which correspondingly results in poor formation quality of the dummy target patterned layer 1012. In the embodiment of the present invention, ions are doped in the pseudo target pattern layer 1012 in the edge region II to form a doped pattern layer 101, and the difficulty of etching the doped pattern layer 101 is less than that of etching the device target pattern layer 1011; therefore, in the process of removing the doping pattern layer 101, the damage of the device target pattern layer 1011 is small, and the uniformity of the electrical property of the semiconductor structure is improved.
In this embodiment, ions are doped in the pseudo target pattern layer 1012 by using a level plasma process (level plasma), so as to form the doped pattern layer 107. The edge plasma process is capable of doping ions into the dummy target pattern layer 1012 while not doping ions into the device target pattern layer 1011 in the central region I. The ions doped into the dummy target pattern layer 1012 can reduce the bond energy between atoms in the dummy target pattern layer 1012, so that the bond energy between atoms in the formed doped pattern layer 107 is smaller than the bond energy between atoms in the device target pattern layer 1011, and the doped pattern layer 107 and the device target pattern layer 1011 have a larger etching selectivity ratio in the subsequent process of removing the doped pattern layer 107.
The technological parameters of the crystal edge plasma process comprise: the reaction gas comprises Ar and H2、N2And He. The reaction gas is plasmatized by a Source power.
In this embodiment, the target pattern layer 101 is made of silicon nitride, and correspondingly, the reaction gas includes H2. The hydrogen ions are doped in the doping pattern layer 107, so that the bond energy between atoms in the doping pattern layer 107 can be lowered.
It should be noted that, during the edge plasma process, the chamber pressure should not be too high or too low. If the chamber pressure is too high, the speed of the ionized ions is easy to be low, and the ionized ions are not easy to be doped into the bottom of the pseudo target pattern layer 1012, so that the forming quality of the doped pattern layer 107 is poor, the bottom of the doped pattern layer 107 is difficult to be removed in the subsequent process of removing the doped pattern layer 107, and accordingly, in the subsequent process of etching the substrate 100 by using the device target pattern layer 1011 as a mask, the residual doped pattern layer 107 in the crystal edge region II can be used as a mask to etch the substrate 100 to form a disordered crystal edge pattern, which is not beneficial to improving the uniformity of the semiconductor structure performance. If the chamber pressure is too low, the speed of the plasma-formed ions is too high, and the top of the dummy target pattern layer 1012 is easily damaged in the process of doping the plasma-formed ions into the dummy target pattern layer 1012, so that the thickness of the dummy target pattern layer 1012 is reduced; in addition, if the chamber pressure is too low, the process controllability and the reaction rate uniformity of the doping process of the dummy target pattern layer 1012 are small, which results in poor formation quality of the doped pattern layer 107 and is not favorable for improving the electrical performance of the semiconductor structure. In this embodiment, during the edge plasma process, the chamber pressure is 500mtorr to 2000 mtorr.
It should be noted that, in the process of the edge plasma process, the source power should not be too small or too large. If the source power is too low in the process of the edge plasma process, the plasma density is easily reduced, so that the rate of doping ions into the pseudo target pattern layer 1012 is too slow, which is not beneficial to improving the formation rate of the doping pattern layer 107; if the source power of the plasma treatment is too high during the edge plasma process, the plasma density is too high, and the doping uniformity of the pseudo-target pattern layer 1012 is poor, resulting in poor formation quality of the doped pattern layer 107. Therefore, in the embodiment, the source power is 100W to 1000W during the edge plasma process.
It should be noted that, in the process of the edge plasma process, the bias power should not be too large or too small. If the bias power is too large in the process of the edge plasma process, the speed of the plasma-formed ions is too high, and the top of the pseudo target pattern layer 1012 is easily damaged in the process of doping the plasma-formed ions into the pseudo target pattern layer 1012, so that the thickness of the pseudo target pattern layer 1012 is reduced; in addition, the bias power is too high, and the process controllability and the reaction rate uniformity of the doping process of the dummy target pattern layer 1012 are small, so that the formation quality of the doped pattern layer 107 is poor, and the improvement of the electrical performance of the semiconductor structure is not facilitated. If the bias power is too small in the process of the crystal edge plasma process, the speed of the ionized ions is easy to be smaller, and the ionized ions are not easy to be doped into the bottom of the pseudo target pattern layer 1012, so that the forming quality of the doped pattern layer 107 is poor, the bottom of the doped pattern layer 107 is difficult to be removed in the subsequent process of removing the doped pattern layer 107, and accordingly, in the subsequent process of etching the substrate 100 by taking the device target pattern layer 1011 as a mask, the residual doped pattern layer 107 in the crystal edge region II can be used as a mask to etch the substrate 100 to form a disordered crystal edge pattern, which is not beneficial to improving the uniformity of the structural performance of the semiconductor. For this reason, in the present embodiment, the bias power is 15W to 200W.
It should be noted that the processing time of the edge plasma process should not be too long or too short. If the process time of the edge plasma process is too long, the efficiency of the semiconductor structure is low. If the process time of the crystal edge plasma process is too short, the ion content in the doping pattern layer 107 is small, the etching selection between the doping pattern layer 107 and the device target pattern layer 1011 is small in the subsequent process of removing the doping pattern layer 107, the doping pattern layer 107 is prone to remain in the subsequent process of removing the doping pattern layer, and in the subsequent process of etching the substrate 100 by taking the device target pattern layer 1011 as a mask, the substrate 100 is etched by taking the remaining doping pattern layer 107 as a mask, so that a disordered pattern is formed in the crystal edge region II, and the uniformity of the semiconductor structure performance is not improved. In this embodiment, the process time of the edge plasma process is 10 seconds to 300 seconds.
In other embodiments, the dummy target pattern layer may be formed by doping ions in the dummy target pattern layer using a ribbon ion beam implantation process (ribbon beam implantation process). The ribbon ion beam implantation process has a good process window, and can be used for injecting ions into the pseudo target pattern layer in the crystal edge area II in a targeted mode.
The technological parameters of the ribbon ion beam implantation technology comprise: the dopant ions include one or more of Ar, H, B, P, and As.
It should be noted that, during the ribbon ion beam implantation process, the doping amount of the doping ions in the doping pattern layer should not be too high or too low. If the doping amount of the doping ions in the doping pattern layer is too high, the process time required by the corresponding ribbon ion beam implantation process is too long, and the efficiency of the semiconductor structure is low. If the doping amount of the doping ions in the doping pattern layer is too low, the ion content in the doping pattern layer is small, the etching selection between the doping pattern layer and the device target pattern layer is small in the subsequent process of removing the doping pattern layer, the doping pattern layer is easy to remain, and in the subsequent process of etching the substrate by taking the device target pattern layer as a mask, the remaining doping pattern layer is taken as the mask etching substrate to form disordered patterns in a crystal edge area II, so that the uniformity of the structure performance of the semiconductor is not favorably improved. In other embodiments, the ribbon ion beam implantation process dopes ions at a dose of 1E13 atoms per square centimeter to 1E15 atoms per square centimeter.
It should be noted that the implantation energy should not be too large or too small during the ribbon ion beam implantation process. If the implantation energy is too large in the process of the ribbon ion beam implantation process, the doping ions easily penetrate through the pseudo target pattern layer to enter the substrate, correspondingly, the doping amount of the doping ions in the formed doping pattern layer is small, in the subsequent process of removing the doping pattern layer, the etching selection between the doping pattern layer and the device target pattern layer is small, the doping pattern layer is easy to remain, in the subsequent process of etching the substrate by taking the device target pattern layer as a mask, the substrate is etched by taking the remaining doping pattern layer as the mask, and disordered patterns are formed in the crystal edge area II, so that the uniformity of the structure performance of the semiconductor is not improved. If the implantation energy is too small in the process of the ribbon-shaped ion beam implantation process, doped ions are only formed on the surface of the doped pattern layer, the etching selection between the doped pattern layer and the device target pattern layer is small in the subsequent process of removing the doped pattern layer, the doped pattern layer is easy to remain, and in the subsequent process of etching the substrate by taking the device target pattern layer as a mask, the remaining doped pattern layer is taken as the mask to etch the substrate, so that disordered patterns are formed in the crystal edge area II, and the uniformity of the structural performance of the semiconductor is not improved. In this embodiment, the implantation energy is 10kev to 200kev during the ribbon ion beam implantation process.
In other embodiments, the method for forming a semiconductor structure further includes: after the target pattern layer is formed on the substrate, before ions are doped in the pseudo target pattern layer, a shielding layer (not shown in the figure) covering the central area I and exposing the crystal edge area II is formed, and the shielding layer covers the device target pattern layer of the central area I and exposes the pseudo target pattern layer of the crystal edge area II.
In the process of doping ions in the pseudo target graphic layer in the crystal edge area II, the shielding layer can protect the device target graphic layer from being doped with the ions.
In this embodiment, the material of the shielding layer includes organic materials, such as: BARC (bottom-antireflective coating) material, ODL (organic dielectric layer) material, photoresist, DARC (dielectric-antireflective coating) material, DUO (Deep UV Light Absorbing Oxide) material, or APF (Advanced Patterning Film) material.
The method for forming the semiconductor structure further comprises the following steps: and removing the shielding layer after removing the doping pattern layer.
In this embodiment, the material of the shielding layer is an organic material, and the shielding layer is removed by an ashing process.
Referring to fig. 12, the doping pattern layer 107 is removed.
The etching difficulty of the doping pattern layer 107 is smaller than that of the device target pattern layer 1011; therefore, in the process of removing the doping pattern layer 107, the damage of the device target pattern layer 1011 is small, and in the subsequent process of etching the substrate 100 by using the device target pattern layer 1011 as a mask, the formation of a pattern in the crystal edge region II can be prevented, so that the effect of forming a semiconductor structure only in the central region I is realized, and the uniformity of the performance of the finally formed semiconductor structure is high.
In this embodiment, the doping pattern layer 107 is removed by a wet etching process. The wet etching process is isotropic etching, has high etching rate, and is simple to operate and low in process cost.
Specifically, the wet etching process comprises the following steps: a level WET etching process (bottom WET) and a global WET etching process (whole wafer WET).
In this embodiment, the material of the doping pattern layer 107 is silicon nitride doped with H ions. The etching solution adopted in the wet etching process comprises the following steps: dilute hydrofluoric acid solution (DHF). In other embodiments, the etching solution used in the wet etching process may further include a mixed solution (HNA) formed by hydrofluoric acid, nitric acid, and acetic acid.
It should be noted that, in the process of removing the doping pattern layer 107, the etching selectivity ratio of the doping pattern layer 107 to the device target pattern layer 1011 is greater than 3, and the etching selectivity ratio of the doping pattern layer 107 to the substrate 100 is greater than 3. So that less damage is done to the device target patterned layer 1011 and substrate 100 during the removal of the dopant pattern layer 107.
In other embodiments, a Remote Plasma etching process (Remote Plasma) may be further used to remove the doping pattern layer. The remote plasma etching process is a process of forming plasma outside the crystal edge region II by using a plasma source, and then introducing the plasma into the crystal edge region II through air flow, an electric field, a magnetic field and the like to etch the doped pattern layer. In the remote plasma etching process, the distance between the ionization region and the etching reaction region of the plasma is far, which is beneficial to obtaining better space uniformity, or more suitable ion and neutral component proportion and different free radical proportion are obtained, thereby being beneficial to improving the etching effect of the plasma etching process.
Referring to fig. 13, after removing the doping pattern layer 107, the substrate 100 is etched by using the device target pattern layer 1011 as a mask, so as to form a substrate 109 and a bottom pattern 110 on the substrate 109.
In this embodiment, the substrate 100 is etched by a dry etching process using the device target patterned layer 1011 as a mask. The dry etching process has anisotropic etching characteristics and good etching profile controllability, is favorable for enabling the morphology of the bottom pattern 110 to meet process requirements, and is favorable for accurately controlling the removal thickness of the substrate 100 by adopting the dry etching process.
Correspondingly, referring to fig. 11, an embodiment of the invention further provides a semiconductor structure.
The semiconductor structure includes: a substrate 100, wherein the substrate 100 includes a central region I and a bead region II surrounding the central region I (only the bead region II on one side of the central region I is illustrated in fig. 11); a device target patterning layer 1011 located in the central region I of the substrate 100; the doping pattern layer 107 is located in the edge region II of the substrate 100, the doping pattern layer 107 has doping ions therein, and the etching difficulty of the doping pattern layer 107 is smaller than that of the device target pattern layer 1011.
In the semiconductor structure provided by the embodiment of the invention, ions are doped in the doping pattern layer 107 in the crystal edge region II, and the etching difficulty of the doping pattern layer 107 is less than that of the device target pattern layer 1011; in the subsequent process of removing the doping pattern layer 107, the damage of the device target pattern layer 1011 is small, and in the subsequent process of etching the substrate 100 by taking the device target pattern layer 1011 as a mask, the formation of a pattern in the crystal edge region II can be prevented, so that the effect of forming a semiconductor structure only in the central region I is realized, and the finally formed semiconductor structure has high performance uniformity.
The substrate 100 is ready for subsequent formation of the bottom pattern.
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
Note that, taking the direction from the center of the center region I to the edge region II as the radial direction, the dimension of the edge region II in the radial direction is not necessarily too large. If the size of the edge region II in the radial direction is too large, the ratio of the edge region II to the central region I is too large, and the effective region of the substrate for forming the semiconductor device is too small, which is not favorable for improving the yield of the semiconductor structure. In this embodiment, the size of the edge zone II in the radial direction is less than 2 mm.
The device target pattern layer 1011 is prepared for subsequent etching of the substrate to form a bottom pattern.
The material of the device target patterned layer 1011 is different from the material of the substrate 100. In the subsequent step of etching the substrate 100 by using the device target patterned layer 1011 as a mask, the substrate 100 and the device target patterned layer 1011 have a larger etching selectivity.
Specifically, the material of the device target pattern layer 1011 includes: one or both of silicon oxide and silicon nitride. In this embodiment, the material of the device target pattern layer 1011 includes silicon nitride. The silicon nitride is a dielectric material which is commonly used in the process and has low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the device target graphic layer 1011.
The doping pattern layer 107 is removed in the subsequent process, and no pattern is formed in the substrate 100 in the crystal edge region II in the subsequent process of etching the substrate 100 by the device target pattern layer 1011.
In this embodiment, the etching selectivity of the doping pattern layer 107 to the device target pattern layer 1011 is greater than 3, and the etching selectivity of the doping pattern layer 107 to the substrate 100 is greater than 3. During the process of removing the doping pattern layer 107, the device target pattern layer 1011 and the substrate 100 are less damaged.
In this embodiment, the dopant ions include one or more of Ar, H, N, and He.
Ions in the doping pattern layer 107 can reduce the bond energy between atoms in the doping pattern layer 107, so that the bond energy between the atoms in the formed doping pattern layer 107 is smaller than the bond energy between atoms in the device target pattern layer 1011, and in the subsequent process of removing the doping pattern layer 107, the doping pattern layer 107 and the device target pattern layer 1011 have a larger etching selection ratio.
In other embodiments, the dopant ions may further include one or more of Ar, H, B, P, and As.
It should be noted that the doping concentration of the dopant ions in the doping pattern layer 107 should not be too high or too low. If the doping concentration of the dopant ions in the doped pattern layer 107 is too high, the corresponding process time required for forming the doped pattern layer 107 is too long, resulting in a low efficiency of the semiconductor structure. If the doping concentration of the doping ions in the doping pattern layer 107 is too low, the ion content in the doping pattern layer 107 is small, in the subsequent process of removing the doping pattern layer 107, the etching selection between the doping pattern layer 107 and the device target pattern layer 1011 is small, the doping pattern layer 107 is prone to remain, in the subsequent process of etching the substrate 100 by taking the device target pattern layer 1011 as a mask, the substrate 100 is etched by taking the remaining doping pattern layer 107 as a mask, and a disordered pattern is formed in the crystal edge region II, which is not beneficial to improving the uniformity of the semiconductor structure performance. In the present embodiment, the doping concentration of the dopant ions is 1E18 atoms per cubic centimeter to 1E20 atoms per cubic centimeter.
The semiconductor structure of this embodiment may be formed by the formation method described in the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a central area and a crystal edge area surrounding the central area;
forming a target graphic layer on the substrate, wherein the target graphic layer positioned in the central area is a device target graphic layer, and the target graphic layer positioned in the crystal edge area is a pseudo target graphic layer;
doping ions in the pseudo target pattern layer to form a doped pattern layer, wherein the etching difficulty of the doped pattern layer is smaller than that of the device target pattern layer;
and removing the doping pattern layer.
2. The method of claim 1, wherein the dummy target pattern layer is formed by doping ions in the dummy target pattern layer using a wafer edge plasma process or a ribbon ion beam implantation process.
3. The method of claim 1, wherein the dummy target pattern layer is doped with ions using a wafer edge plasma process;
the technological parameters of the crystal edge plasma process comprise: the reaction gas comprises Ar and H2、N2And He, a chamber pressure of 500 to 2000mtorr, a source power of 100 to 1000W, a bias power of 15 to 200W, and a process time of 10 to 300 seconds.
4. The method of claim 1, wherein the dummy target pattern layer is doped with ions using a ribbon ion beam implantation process;
the technological parameters of the ribbon ion beam implantation technology comprise: the dopant ions include one or more of Ar, H, B, P, and As, with a dopant amount of 1E13 atoms per square centimeter to 1E15 atoms per square centimeter, and an implant energy of 10kev to 200 kev.
5. The method of forming a semiconductor structure of claim 1, further comprising: forming a target pattern layer on the substrate, and forming a shielding layer covering the central region and exposing the crystal edge region before doping ions in the pseudo-target pattern layer;
the method for forming the semiconductor structure further comprises the following steps: and removing the shielding layer after removing the doping pattern layer.
6. The method of claim 1, wherein the step of providing the substrate is performed with a radial direction from a center of the central region to the edge region, and a dimension of the edge region in the radial direction is less than 2 mm.
7. The method for forming a semiconductor structure according to claim 1, wherein during the removing of the doping pattern layer, an etching selectivity ratio of the doping pattern layer to a device target pattern layer is greater than 3, and an etching selectivity ratio of the doping pattern layer to a substrate is greater than 3.
8. The method of forming a semiconductor structure of claim 1, wherein the step of forming a target pattern layer on the substrate comprises: forming a target material layer on the substrate;
forming a photoresist material layer on the target material layer;
carrying out patterning treatment on the photoresist material layer to form a photoresist layer;
and etching the target material layer by taking the photoresist layer as a mask, wherein the residual target material layer is taken as the target pattern layer.
9. The method of forming a semiconductor structure of claim 8, wherein the step of forming the photoresist layer further comprises: and carrying out photoresist edge repairing treatment on the photoresist material layer.
10. The method of forming a semiconductor structure of claim 1, wherein the doped pattern layer is removed using a wet etch process.
11. The method for forming a semiconductor structure according to claim 10, wherein the etching solution used in the wet etching process comprises: a mixed solution of hydrofluoric acid, nitric acid and acetic acid, or a diluted hydrofluoric acid solution.
12. The method of claim 1, wherein the dopant pattern layer is removed using a remote plasma etch process.
13. The method of forming a semiconductor structure of claim 1, wherein the material of the target pattern layer comprises: one or both of silicon oxide and silicon nitride.
14. A semiconductor structure, comprising
A substrate comprising a central region and a bead region surrounding the central region;
a device target graphics layer located in the central region of the substrate;
and the doped pattern layer is positioned in the crystal edge area of the substrate, doped ions are arranged in the doped pattern layer, and the etching difficulty of the doped pattern layer is smaller than that of the target pattern layer of the device.
15. The semiconductor structure of claim 14, wherein the dopant ions comprise one or more of Ar, H, B, P, and As;
or,
the dopant ions include one or more of Ar, H, N, and He.
16. The semiconductor structure of claim 14, wherein a doping concentration of dopant ions in the doping pattern layer is from 1E18 atoms per cubic centimeter to 1E20 atoms per cubic centimeter.
17. The semiconductor structure of claim 14, wherein a dimension of the edge region in a radial direction is less than 2 mm, taking a direction from a center of the center region toward the edge region as a radial direction.
18. The semiconductor structure of claim 14, wherein the etch selectivity of the doping pattern layer to the device target pattern layer is greater than 3, and the etch selectivity of the doping pattern layer to the substrate is greater than 3.
19. The semiconductor structure of claim 14, wherein the material of the device target pattern layer comprises: one or both of silicon oxide and silicon nitride.
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