JPS59501287A - Digital clocking and detection system for digital storage systems - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] name of invention Digital clocking and detection system for digital storage systems Background of the invention The present invention provides data storage systems for digital data storage systems such as tape drives. specifically improved digital data clocking and detection. Regarding the tracking and detection system.

Stored digital data is stored on a device such as a magnetic tape or disk system. When regenerated from the data storage 7 stem, the frequency and frequency of the conversion in the regenerated signal It is necessary to determine both the phase and phase. In magnetic tape storage, data The data contains nine transforms representing ones and zeros that make up a digital data word. It is typical what is stored in the track. A separate clock track is normally recorded. Not possible. From the reproduced data itself, the bit cell limit in each track Appropriate locking must be determined in order to define the

Because the speed of the magnetic media on which data is recorded varies slightly, The frequency of the clock pulse that defines the edge of the bit cell that is emitted is It must be changed to match changes in speed. The speed of the magnetic medium changes. to provide a clock pulse with a frequency that changes as the It is a well known method to provide a voltage controlled oscillator (vC○) that tracks the converted conversion. Ru. Rocking 2 is proper in itself It is not sufficient to provide a The phase must also be detected. wide (two forms of magnetic tape recording used) The system uses ANS engineering standard phase encoding (PE) and ANSI standard GCR notation. This is a recording method. In the PE recording method, there is always a bit in the middle of one bit cell. There is one transformation at the edge of one bit cell, and often there is one transformation at the edge of one bit cell. exist. In the GCR recording system, if one bit cell performs one conversion If so, this is in the middle and not at the edges of this bit cell. all Not all OCR bit cells contain translations. The recorded bit is 1. In order to properly determine whether the bit is have phase information to determine whether a single transformation occurs in the cell. Is required.

Most prior art PE and GCR tape systems use used an analog phase-locked loop and analog data detection circuit for . U.S. Patent No. 4,109,236 to Be5enfetder The digital circuit for monitoring and detection is shown. IBM technical desk Roja Plechin, April 1981, No. 23, No. 11.

The paper entitled ``Digital Phase Error Detector'' by Robert Faher is a paper on digital phase error detection. shows the output device.

In the prior art, a phase-locked loop and associated circuitry are used for each data track. It is provided. This requires a controlled oscillator for each trunk. There is another problem currently associated with efforts such as CGR. In such recording systems, sequences of bit cells often occur without conversion. . Due to the high density and nature of the medium, the transformation at the edge of this series of bit cells often results in a shift, and the resulting transformation appears as a phase error. For this reason, In an attempt to compensate for the apparent phase error in this track, This causes a shift in the frequency of the controlled oscillator.

One object of the present invention is to use a common controlled oscillator to clock all tracks. Digital data that reduces costs by providing lock pulses The aim is to provide a data clocking and detection system.

Moreover, the purpose of the present invention is to achieve the above-mentioned high density)? Reduces sensitivity to tracking problems The purpose of the present invention is to provide a digital tape clock detection system that enables

It is an object of the present invention to provide a digital replacement for the analog circuitry normally associated with such functionality. The purpose of this invention is to provide a digital data and phase detection circuit.

It is an object of the invention to control the frequency of an oscillator with a relatively small phase error. is compensated by the count in the phase counter associated with the track in question The purpose is to compensate for large errors in phase by changing the This way In this way, phase deviations such as those caused by skew are compensated for in each individual track. It is.

It is an object of the present invention to provide a data and phase detection circuit in which dropout recovery is enhanced. It is provided by.

Summary of the invention According to the present invention, a data clock for a digital data storage system is provided. A tracking and detection system is provided for the phase detection device for all multiple tracks. includes a common controlled oscillator that generates clock pulses. Each truck The phase detector for clocks uses multiple clock pulses for each bit cell, in some cases includes a binary counter that counts 16 clock pulses. . The phase error of the transform in the regenerated data is determined by the counter in this counter. Determined with respect to If the range immediately before or after the center of the bit cell If the conversion occurs at counts, e.g. counts 4-7 and 8-11, then The correction output representing the magnitude of the phase error is given to a commonly controlled oscillator. It will be done.

If this size becomes even larger, for example in the range of counts o~3 and 11~15. If it falls within Phase correction is performed by changing the count in the digital counter. Ru. For example, when the data conversion falls within the count range 0 to 3, the count and if this transformation occurs within the range 11 to 15, A count is added to the counter. In this way, for various tracks The counters are adjusted differently one by one to accommodate trunk-to-trunk skew.

According to another feature of the invention, added for controlling the common controlled oscillator The correction output has a pulse width proportional to the magnitude of the phase error. Alternatively, supplement The positive signal may be a fixed-width .xi. pulse that represents only the polarity of the phase error. either In this case, correction information from all tracks is combined and added for oscillator correction. It will be done.

According to the invention, a controlled oscillation circuit provided for each track of the prior art is replaced by one oscillator. This results in cost savings and bit Reduces the problem of erroneous compensation of controlled oscillators (VCOs) caused by congestion of do. By individually correcting each counter in each phase detection device, this Inventive tape clocking/detection system detects data frequency (media speed) provides good tracking of transient fluctuations in the tape and head skew. provides good tracking of relatively long period phases such as those caused by -.

The above and other objects, features and advantages of the present invention have been described in more detail below. It will be better understood from the description and appended claims.

Brief description of the drawing FIG. 1 shows the prior art use of a separate VCO for each track of a storage system. shows, FIG. 2 shows the data clocking and detection system of the present invention; FIG. 3 shows the phase detection device of the present invention, and FIG. 4 shows the data detection device of the present invention. , 5A to 5H and 6A to 6G show waveforms and are described in more detail. Figure 5A shows the GCR data and Figure 5B shows the most significant bit of the phase counter. ri, 6 FIG. 5C shows the corrected addition signal, Figure 5D shows the corrected subtraction signal; Figure 5E shows the output of the data integration counter, and Figure 5F shows the output for one track. Figure 5G shows the clock synchronized with the data, and Figure 5H shows the NRZ data. Figure 6A shows the phase error pointer, Figure 6A shows the VCO clock output, and Figure 6A shows the VCO clock output. Figure 6B shows the GCR data for one track, and Figure 6C shows the GCR data for one track. indicates the most significant bit of the phase counter for Figure 6D shows the phase counts for said track and Figure 6E for another track. Figure 6F shows the phase counter data for other tracks. indicates the most significant bit, and Figure '6G shows the phase counts for other tracks.

Description of the preferred embodiment Figure 1 shows multiple tracks, in this figure two track locking and detection systems. Showing the stem. The magnetic tape drive system uses PE in nine tracks. Or record data in GCR format. Transformations in the data being played is detected by the signal edge detection device 11. The phase detection device 12 detects when the conversion occurs. Detecting the phase of the conversion with respect to the clock pulse that defines the oscillator bit cell.

A controlled oscillator (vco) i3 produces these clock pulses. this The output of the phase detector 12 is passed to a filter 14 which produces a voltage that controls an oscillator 13. can be added to This clock pulse defines the bit cells of data. Detection of data by a data detection device 15 that produces an output that does not return to zero with the clock. Used in production.

According to the invention as shown in FIG. A clock pulse is generated for the phase detection device 18 for the phase detection device 18. data replay The tracks represented are fed to an edge detection device 2o which detects data representing the transformation. It will be done.

If such conversions occur, they will occur in the middle of the bit cell. must occur. These conversions and clock pulses from VCol6 represents the phase error of the conversion with respect to the clock pulse defining the bit cell. is applied to the phase detection device 18 which produces a corrected output. If the conversion is bit If it occurs earlier than the center of the cell, the output C0RRECTION UP will occur. and if the conversion occurs late after the bit, middle of the cell, the output C0R FIECTION DOWN is generated. The correction output of the phase detection device is an OR game. It is combined at 22.24. Signal C0RRECT]: ON UP All nine are combined in OR gate 22 and filtered in filter 26. applied to VC016 to increase the frequency by producing a signal that is filtered . At all nine outputs C0RRECTIONDOWN the OR gate 24 and its output is filtered in filter 26 to output clock signal 2. This results in a voltage being applied to VCol 6 to reduce the frequency of the pulse.

These clock pulses are used along with the recovered data for digital data detection. added to circuit 30, this circuit provides a clock that is synchronized with the data to be reproduced. ・Along with the pulse, produces an output representing the reproduced data in a form that does not return to zero. . The digital data detection device of the present invention also detects data that is accompanied by and that is suspicious. generates a phase pointer that identifies the pointer. These phase pointers are assigned to the bit cells. Display the data represented by the transformations that occur extremely quickly or slowly. The phase pointer is connected to both the magnetic tape storage system and associated teller correction circuitry. It is used in

The VCol6 of the present invention has a predetermined number of clock pulses for each bit cell. arise. In this example, "," is usually indicated by 0 to 15 as shown in FIG. 6A. There are 16 clock pulses.

FIG. 3 shows the phase detection circuit 18 repeated for each of the nine tracks. There is. This circuit uses a digital register that counts clock pulses from the VGO. It includes a phase counter 32. Counter 32 normally cycles, one bit cell When the count of 16 clock/ξ pulses that defines do.

Playback data from the associated track produces a pulse at the time of the detected conversion. is added to the conversion detection device 34.

The decoding logic includes wind generator 36 and AND gates 38-44. , signals C0RRECTION UP and C0RRECTION DOWN, and produces signals 5HORT and LONG. These signals are is generated according to the temporal period in which the transformation occurs with respect to the center of . Referring again to Figure 6A. , if the conversion occurs in the very low range corresponding to count O~3 , ·ξcis5HORT is generated. The signal C0RRECT IQNUP is ) Generated if the conversion occurs in the range corresponding to O~7, and if the conversion occurs in the range corresponding to If it occurs within the range corresponding to counts 8 to 15, output C0RRECTION D OWN is generated and if the conversion is in the very high range corresponding to counts 12-15 If this occurs, a pulse LONG is generated.

Referring again to FIG. 3, pulse 5HORT marks the opening completion window for counts 0-3. is generated by AND gate 44 in response to the output of code circuit 36. Output C0RR ECT ON UP responds to a window that completes between counts 0 and 70 Responsive to the window generated by gate 42 and completed between counts O and 7. The output C0RRECTION UP is generated by the AND gate 42 Signal C0RRECTION in response to a window that completes between counts 8 and 150. DOWN is generated and the AND gate 38 completes opening of counts 12-15. generates a signal LONG in response to the code.

Signal C0RRECTI○N UP and C0R with width proportional to phase error To generate RECT ON DOWN, the outputs of AND gates 40 and 42 are are added to the pulse width logic 46 and 48 respectively. Logic 46.48 is , yielding a pulse with a width proportional to the period between the bit cell conversion and center Ru.

Logic 48 generates a norm ξ that starts at the data edge and stops in the middle of the cell. generate. Counter 45 indicates that the conversion is 10 in the cell. Count how long after the interval occurs. If the latter transformation occurs, then Logic 46 generates a signal proportional to 450 counts.

The signals C0RRECTION UP and C0RRECT I○N DOWN are v CO control? ,: Other signal C0RRECTION UP Oyohi C0R To be combined with RECT 0NDOWN, OR game) 22.24 (Figure 2) added to. In this way, the frequency of ■GO is controlled by the phase error. It is possible.

In the case of even larger phase errors, the counts may be added with respect to the phase counter 32. is subtracted. When AND gate 44 produces pulse 5HORT, the count is subtracted from the phase counter 32. AND gate 38 produces a pulse LONG. A count is added to phase counter 32. Because of this, another has the effect of increasing or decreasing the phase detection device of one track relative to the track. do. This may be caused by factors such as head or tape skew. Used to compensate for phase deviations.

This information bit contains an error when the conversion occurs within the extreme range above and below the bit cell. An indication is generated to the effect that it exists. AND gate 50 is activated when this condition occurs. Generate a relative pointer.

Figure 4 shows the data detection arrangement repeated for each of the nine tracks. Ru. The data and output of the phase counter 32 (Figure 3) are 4-bit data integrals. is given to counter 52. The data detection circuit 54 detects bit cell moss. Generates output that displays the high or low condition of the counter at .

In the case of GCR data, the NRZ data circuit 56 determines the end of the current bit cell. Compare the conditions at with those of the last bit cell in 7 lip-flop 92. to produce an output representing NRZ data. For PE data, the data service Cycle circuit 90 performs two-level tracking of PF and data cells. NRZ de The data sensor circuit 56 then uses the data separator circuit 56 as the integrated data produces an NRZ data output. In the second half of the test, it is determined whether the signal is high or low. clock circuit 58 is a clock output synchronized with the NRZ data output for either data density. generate force.

The operation of the data clocking and detection system of the present invention is illustrated by an example of its operation. This can be better understood from Figures 5A to 5H and Figures 6A to 6G. cormorant. In Figure 5A, the first transformation 60 in the data is the transformation in Figure 5B. Occurs exactly in the middle of the bit cell as defined by the lock.

In this case a complete fixed state exists. The next conversion 62 is slow (, bit cell intermediate Even if it occurs later, within the period defined by counts 8 to 11 of the phase counter. Ru. As shown in Figure 5D, the signal C0RRECTION DOWN is generated. It will be done. The next transformation 64 occurs very quickly. This is the time in the middle of the bit cell. It should have occurred at point 66. The phase error pointer is shown in Figure 5H. It is generated as follows. The last transformation 68 is early with respect to the middle of bit self 0. arise. Signals COR1-C ION U, P are generated as shown in Figure 5C. It will be done. FIG. 5E shows the output 2 of the data integration counter 52 in detecting this data. It shows. NRZ data circuit 56 produces the output shown in FIG. 5F. . The clock 58 is a clock synchronized with the data and has the waveform shown in FIG. 5G. generate. Figure 5', It, shows that the transition point 64 causes an accidental large phase error. 5 shows an error pointer generated by AND gate 50 for display. .

Figures 6A-6G illustrate two tracks where one track is skewed relative to the other. The conditions of the phase detection device for the track are shown. Figure 6B shows one track. FIG. 6C shows the phase counter 32 for this track. The most significant bit is shown. Figure 6E shows the regenerated GC for another track. FIG. 6F shows the most significant bit of the phase counter 32 for this track. It shows the cut. Figures 6D and 6G show the phase shift for the two trunks. mount. Convert counter to 76 (Karan) Skip 15 to 14 By placing from to zero, you can delete or skip a count in the phase count Note that conversion 72 occurred as quickly as . smell of another truck In this case, a count is changed in phase by repeating count 12 in transform 78. The conversion 74 occurred so late that it was added to or duplicated in the count. Therefore, the obtained 2 The phase counter for two tracks increases as the phase skew of one relative to the other increases. The result was that

Although specific embodiments of the invention have been shown and described herein, various modifications may be made to the invention. Be within the spirit and scope. Accordingly, the appended claims cover all such modifications. It is intended to be comprehensive.

Jo 7sho (no changes to the content) Procedural amendment (formality) %Restem ≠ 0) %Restem ≠ 0) 7 Kink°J9ke Munstem 6. Person who makes corrections Relationship to the incident: Applicant S storage °・〒1ノ+2−record・code 0 and 15、correction command Date: April 5th, Showa 1996 (shipping date) 6, subject to amendment international search report

Claims (1)

[Claims] 1. Digital data represented by conversions in successive bit cells is multiplexed. Data for digital data storage systems that are stored and played back on tracks. In the data clocking and detection system, Each associated transistor with respect to the clock pulse defining said bit cell. each of said multiple tracks yielding a corrected output representative of the phase error of the transform that can be applied; a phase detection device for; each reproduced conversion and said digital data in response to said clock pulse. a data detection device for each of the multiplex trunks; a phase detection device and a data detection device for each of the multiple tracks; a commonly controlled clock pulse for said multiple tracks that produces clock pulses that are A combination of an oscillator and a correction output of the phase detection device corresponds to the controlled oscillator. generating a control signal applied to the multiplex track with respect to the bit cell; A device for changing the frequency of said clock pulse according to the phase error of the conversion in A data clocking and detection system with 2. The controlled oscillator generates a predetermined number of clocks for each bit cell. - generate pulses and each phase detection device is configured to count said clock pulses. a teinotal phase counter, which typically corresponds to one bit cell. Complete counting of the predetermined number of clock pulses at the same time ・Claim 1, item 4 that is overridden built-in data clocking and detection system. 3. The phase detection device is configured such that the conversion in the reproduced data is based on the clock signal. ...produces an addition correction output when it occurs at half the count of cell 7, and When the conversion occurs in the other half of the count, a subtractive correction output is produced. 2. The data clocking and detection system as described in Section 2. 4 Connected to the output of the phase count to prevent large phase errors in the conversion. A device for generating long and short signals is further provided, and the long and short signals are applied to the phase counter. Claim No. 1 given for said counter for subtracting/adding the count 3. The data clocking and detection system as described in Section 3. 5. Further provide a decoding logic connected to the binary output of the phase counter, and the decoding logic The logic is the count in the counter or the middle of the hit cell. When a conversion occurs in the data when it is in a very low range, it produces a short pulse. , when the decoding logic is in a very high range after the middle of the bit cell. When a conversion occurs in the data, it produces a long pulse, and the short pulse produces the given to said counter to subtract from the phase counter, said long ξ signal is applied to the phase counter to add it to the phase counter. The data clocking and detection system according to claim 3. 6. The phase correction logic connected to the binary output of said preset counter. further provided, the phase correction logic is configured such that the count of the counter is 15 lower before the middle of produces an additive correction output when a transformation occurs in said data when in the range Phase correction logic determines when the counter counts after the middle of the bit cell. Claims that result in a subtractive correction when the conversion of the data occurs when it is in a high range. 3. The data clocking and detection system according to paragraph 3. 7 The above combination device is an OR gate, the correction output from the data detection device being applied to the OR gate; added, a filter, the output of the OR gate being applied to the filter; Claims wherein the output of the filter is added to control said controlled oscillator. The data clocking and detection system according to paragraph 1. 8. The phase detection device detects a pulse having a width proportional to the phase error of the conversion. Data clocking and detection as claimed in claim 1 resulting in a certain subtractive correction output. system. 9. The data detection device includes an integrating counter, and the clock pulse is The regenerated transformation is applied to the counter. data according to claim 1, which produces a digital signal representing the data. ・Clocking and detection system. 10. Conversion in the data and binary count in the phase counter In response, the count of said counter is in the low range or When a conversion occurs on said data when is in a high range, the error pointer The data converter according to claim 1 further comprising a conversion error detection circuit for generating a signal. Clocking and detection system. 11. The digital data represented by the transformations in successive focus cells is a digital data storage system that is stored on and reproduced from a reproducible medium In a data clocking and detection system for the magnitude of the phase error of the conversion with respect to the clock pulse defining the bit cell; a phase detection device that generates a correction output having a pulse width representing the a controlled generator for generating clock pulses applied to the phase detection device; an oscillator, and the correction output of the phase detection device is applied to the controlled oscillator. and the magnitude of the phase error as represented by the width of the corrected output pulse. a data clocking and sensing system that controls the frequency of the oscillator according to the frequency of the oscillator; Mu. 12. The phase detection device comprises: Dial to count multiple clock pulses during the duration of each pinto cell. a digital counter and a binary output of said counter, said conversion is connected to said bit producing said correction output having a width proportional to the number of counts that deviate from the center of the cell; and decoding logic according to claim 11. system. 13. Digital data represented by conversions in successive bit cells, A digital data storage system that is stored on a reproducible medium and then replayed. In data clocking and detection systems for 7 A diode for counting multiple clock pulses for each bit cell. a digital counter and defining the bit cells in response to the output of the counter; Phase detection that produces an output representing the phase error of the conversion with respect to the clock pulse a device; a controlled oscillator for generating said clock pulses and connected to said phase detection device; control the oscillator in response to a phase error, and wherein the phase error is relatively and a logic device that subtracts/adds a count to the phase counter when the count is large. Data clocking and detection system. 14. said controlled oscillator generates data reproduced from said reproducible medium; It is a common oscillator for multiple tracks, and a phase detection device is provided for each track. 12. The data clocking and detection system of claim 11. 15. The system further comprises: The combined correction outputs of the phase detectors are applied to the controlled oscillator. the data clock according to claim 14; King cum detection system.