JPS59501089A - Level sensitive reset circuit for digital logic - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Rehel Sensitive Circuit Components for Digital Logic The present invention provides a novel method for providing fast reset action for digital logic circuits. With respect to circuits, the reset action relies on a storage element to generate the reset signal. Does not exist.

亙兙池■ In the use of digital logic circuits, often the digital counter is turned off. There is a need to reset such circuits. If the digital counter turns off If the reset circuit is turned on, but then turned on quickly, the reset circuit will and that it is not fully reset when the circuit turns on. It can occur.

For example, suppose a digital counter is counting to 100. Coun The tar is then turned off, but then quickly turned on. Konoto The counter wants to be zero, but the rapid turn on Therefore, the reset circuit does not recover and the counter may be at any number rather than zero. be. This problem is especially true when circuits requiring capacitor discharge are used. Can be seen. In such a circuit, if the power supply is turned off, the supply The voltage will rapidly decrease to zero. However, such a capacitor circuit must be discharged at some point before the circuit can be properly reset again. Uses capacitors that must be used.

In sterilization equipment, it is important that time or quantity measurements are accurate; Digital logic circuits such as digital counters that can be used to make measurements It is especially important that it is properly reset. For example, if you want to sterilize an object The counter that measures the amount of UV radiation used has not been properly reset. If so, the counter may not start counting from its zero point? sterilization may be incomplete.

Therefore, it is an object of the present invention to use a storage element such as a capacitor to generate a cent signal. Provide a circuit to reset digital logic circuits without relying on elements That's true.

Another object of the invention is to provide a quick reset for digital logic circuits and Provide a self-test to determine if a quick reset has actually occurred. That is.

Other objects and advantages of the invention will become apparent as the description progresses. A circuit is provided that does not use a capacitor that must be discharged. For this reason When the power supply is turned off and the voltage decreases, the power supply is turned on again. The action of the present invention will occur as soon as the digital logic circuit is reset. .

For this reason, the circuit of the present invention provides a first signal when a predetermined condition occurs. including a switch operative to supply the power. A bistable device connected to the output of the switch. the stabilizer is activated to receive a first signal, and the stabilizer is in a first state. is operative to provide an output reset signal in response to the first signal. Reset The output decile logic circuit receives this output reset signal, so the bistable device Concatenated to output. Places the bistable device in a second state, thereby causing an output reset signal. from a feedback means or digital logic circuit to provide a signal to truncate the signal. Connected to a bistable device.

In the illustrative example, to determine when the above-mentioned conditions have occurred. Means will be provided. The determining means includes LED, and the switch includes a phototransistor optically coupled to the LED. The bistable device is a flip-flop, and the phototransistor is connected to the clock of the flip-flop. the feedhacking means is coupled to the flip-flop glue input; Concatenated to input. The feed hack means is connected to the digital logic circuit or the like. and means for detecting that the amount has been reset to a predetermined amount.

In an illustrative embodiment, the digital logic circuit includes a multi-stage counter, and The feed hack means is connected to check the top 8 hints of the counter. tied. The foot hack means includes a NOR gate, and outputs the upper 8 bits. the output of the NOR gate is connected to the input of the NOR gate, and the output of the NOR gate is connected to the input of the NOR gate; connected to the top.

A further detailed description of the invention is provided in the following description and claims, and in the appendix. Illustrated in the accompanying drawings.

Drawing L11 Firefly Death- FIG. 1 is a block diagram of a circuit constructed in accordance with the principles of the present invention.

Figure 2 shows one of the inventions used to reset a multi-stage digital counter. 2 is a schematic circuit diagram in the form of .

■ Noboru 1 body screams, but the aim star escapes Referring to FIG. 1, resistor 10 consists of zenataiodes 12 all connected in series. and to limit the maximum current flowing through the light emitting diode (LED) 14. used. Zena diode 12 requires a certain voltage to conduct; The LED 14 has an inherent offset voltage that makes it particularly difficult to conduct. Since a certain voltage is required, when the sum of these two voltages is reached, the LED 14 The optically coupled phototransistor 16 will be conductive. Figure 1 shows As shown, the collector of transistor 16 connects lines 18 and 20 to and the emitter of transistor 16 is connected to the power supply through resistor 22. and grounded.

In short, diodes 12 and 14 are connected to the voltage at which the reset action begins. Used to program levels. When transistor 16 is conductive , the current flowing through resistor 22 produces a positive continuous voltage across resistor 22; The voltage is applied via line 26 to the clock input of flip-flop 24. . Lines 18 and 20 connect data to flip-flop 24 via line 28. (D) Connected to the input.

Although not intended to be limiting, flip-flop 24 is preferably (JIO34013 type). It is similar to the type Esocitriga Phrysopfuronop.

on the power supply voltage to the D input of flip-flop 24 and on its clock input. In response to the increasing voltage, the Q output of flip-flop 24 goes high. Flipf The Q output on line 3o of flip-flop 24 is the reset (R) of flip-flop 24. It is an output reset signal that will not go low unless a high signal is applied to the input. others For this purpose, line 30 is connected to the reset input of logic 32 to be reset. Coun A logical function such as that of a controller is in a certain state each time the unit is turned on. Assume that it has to be reinitialized to . When the logical function is an operation, The logic circuit is reset in response to a signal generated by flip-flop 24. will be done.

Reset condition decoder 34. is provided, and line 36. Reset condition de It forms part of a feedback circuit that includes coder 34 and line 38. Applicable The feed hack circuit connects logic 32 to the reset input of flip-flop 24. be done. The reset condition decoder 34 determines whether the logic to be reset is actually reset. Decide what happens. If it is reset, a high signal will occur and the flip Applied to the reset input of flop 24, pulling line 3o low and applied to logic 32. Remove the reset signal that is generated.

Referring now to Figure 2, the glue for use in the sterilization chamber in which sterilization is carried out is shown. A set circuit is provided. In this example, disposable items are placed in a drawer. and UV sterilization is applied.

A counter is used as a measuring device, but the counter is closed when the drawer is closed. count until the disposable item is placed in its correct position in the drawer. shall not be started.

In the embodiment of FIG. 2, resistor 10 has a unique predetermined offset voltage. In series with a diode 40, which is a standard silicon rectifier with voltage. LED 14a and LED 14b are phototransistors 16a and 1, respectively. 6b.

L E D l 4. a and the phototransistor 16a have their drawers closed. LED 14b and phototransistor 16b to indicate that the disposable item is in its correct position within the drawer. To position. When the power is turned on, if the voltage is constant and reaches the voltage level, the diode will conduct electricity. will guide you. However, the drawer of the phototransistor 16a is closed. The phototransmitter 16b will not turn on unless the disposable item is removed from the drawer. It will not turn on unless it is in that correct position inside. the drawer is open block the actual light path when The light path is opened when the drawer is closed. photo tiger registers 16a and 16b turn on and reset when the drawer is closed. Begins action. In this embodiment, the optical coupler is a power-only Provides both a set and a process (to zero the counter) reset. Ru.

There is a door open alarm circuit coupled to the emitter of I-Land Disc 16a; It operates under certain conditions. Emitters of transistors 16a and 16b are connected to the inputs of L7AND gates 1-42 via lines 43 and 44, respectively. be done. AND gate 42 has both transistors 16a and 16b conductive. Provides a high output signal only when High output signal on output 46 of AND gate 42 is supplied to the clock input of flip-flop 24, and The data (D) input of 4 is coupled to a voltage source.

When flip-flop 24 is supplied with a positive continuous clock signal, the flip-flop The Q output of loop 24 will be high, so it will be routed through line 48 to the amplifier counter. An output reset signal is supplied to the reset input of 5o. to amp counter 5o The Q output of counter 50 must become zero in response to the high rate of cent entry. do not have. If all Q outputs of counter 50 are zero, NOR gate 52 provides a high output through line 54 to the reset input of flip-flop 24. There will be. The Q output of flip-flop 24 then goes low and the counter -50 is allowed to count normally. The output of any of the counters 50 If not zero, NOR gate 52 will have a continuously low output, thereby causing a fault. prevents flip-flop 24 from being reset and flip-flop 2 The Q output of 4 is always kept high, preventing the counter from counting to 50. Probably.

Although not intended to be limiting, in this illustrative example counter 50 is 1 of type 4020. It is a 4-stage ripple counter. The NOR gate 52 is the top 8 hits of the counter 50. It acts to check that the reset is actually being reset. If Coun. If the top 8 hints of the gate 52 are reset, the NOR gate 5 is reset as described above. 2 produces a high output on line 54 to the reset input of flip-flop 24. and causes the Q output of flip-flop 24 to be low, thereby causing counter 50 to Remove reset signal. By checking the upper 8 bits, this circuit effectively determine whether the reset was successful at least to a predetermined degree. Ru.

Sterilization chamber drawer is opened and then quickly closed or the mains supply voltage is removed If the reset signal generator is turned on and then quickly turned back on, the A reset signal that is independent of the constant time will be generated. opening the drawer or destructive activities such as removal of the voltage supply use a capacitor in the reset circuit can occur relatively frequently without any associated problems.

When using a ripple counter like Counter 50, the output will be slightly off. and in this manner the conversion of the outputs of the counters is not always simultaneous. child Therefore, a transient state may appear at the output of NOR gate 52. To avoid this problem , by the amount of time necessary for the false output to be provided by NOR gate 52. resistor 56 and capacitor 58 are connected to the delay network to shift the 07 output. It is set up as a network.

While illustrative embodiments of the invention have been illustrated and described, the novel spirit and scope of the invention It should be understood that various modifications and substitutions may be made without departing from the invention.

So international search report Special table 59-501089 (5)

Claims (1)

[Claims] 1. a switch that operates to provide a first signal when a predetermined condition occurs; Itchi and output in response to the first signal when receiving the first signal and being in a first state; a bistable device operative to provide a reset signal; a reset circuit coupled to the output of the bistable device for receiving the output reset signal; the digital logic circuit to be stored and the bistable device in a second state, thereby from the digital logic circuit to provide a signal to abort the output reset signal of the A device characterized in that it comprises feedbank means coupled to said bistable device. A circuit for resetting digital logic circuits. 2. Contains a diode and an LED to determine when the predetermined conditions occur. 2. The circuit according to claim 1, comprising means for determining. 3. Clause 2, wherein the switch comprises a transistor optically coupled to the LED. The circuit described. 4. The bistable device is composed of a flip-flop, and the switch is configured to control its clock. an input, said feedback means being coupled to said reset input; The circuit described in item 1. 5. The circuit according to item 1, wherein the digital logic circuit comprises a counter. 6. The feed hacking means uses a weighing set predetermined by the digital logic circuit. 2. The circuit according to claim 1, including means for sensing that an event has occurred. 7. A means for determining when a predetermined condition occurs and the above synopsis. a switch that operates to supply a first signal when a predetermined condition occurs; , The determining means includes an LED and the switch is optically coupled to the LED. a transistor connected to the output of the switch and in a first state; a bistable device operable to provide an output reset signal in response to the first signal; a flip-flop, with the switch connected to its clock input; a bistable device including a flip-flop for receiving the output reset signal; a digital counter to be reset connected to the output of the flip-flop; provides a signal that causes the chip to enter the second state and thereby abort its output reset signal. A field connected from the digital counter to the flip-flop to Equipped with a means of hacking, Said feed hacking means is coupled to said flip-flop input; and said feedbank means is configured to carry out a weighing process predetermined by said digital counter. digital, characterized in that it includes means for sensing that it has been set; A circuit for resetting logic circuits. 8. The digital logic circuit comprises a multi-stage counter, and the feed hack means is the first term that is connected to check and check the upper 8 bits of the counter. The circuit shown. 9. The feedback means includes a NOR gate, and the output of the upper 8 bits is coupled to the input of the NOR gate, and the output of the NOR gate coupled to the bistable device. 9. The circuit according to claim 8, wherein the circuit is connected to 10. The bistable device consists of a flip-flop, and the switch controls its clock. and said feedback means is coupled to a reset input thereof. The circuit according to item 8. 11. A device configured to provide a first signal when a first predetermined condition occurs. a first switch that moves; operative to provide a second signal when a second predetermined condition occurs; a second switch; means for supplying a third signal only when said first and second signals are supplied; and, and supplying a reset signal when receiving the third signal and being in the first state. an operative bistable device and an output of said bistable device for receiving said reset signal; a digital logic circuit to be reset coupled to the bistable device in a second state; and thereby provide a signal that aborts the reset signal. comprising feed hack means coupled from the logic circuit to the bistable device; A circuit for resetting a logic circuit characterized by the following. 12. a first means for determining when the first condition occurs; and a first means for determining when the first condition occurs; and a second means for determining when the condition occurs. Road. 13. The first means and the second means each include LED, and the first means and the second means each include LED. The first and second switches are optically connected to the first and second LE D, respectively. 13. The circuit of claim 12, which is coupled to. 14. The bistable device includes a flip-flop, and the switch controls its clock. an input, the feedhack means being coupled to a reset input thereof. The circuit according to item 11. 15. The digital logic circuit consists of a multi-stage counter, and the feed bank means The 11th term is connected to check the upper 8 bits of the counter. The circuit described. 16. The feed hacking means is a scale predetermined by the digital logic circuit. 12. The circuit of claim 11, including means for sensing that it has been set. 17. The feed hack means includes a NOR gate, and the output of the upper 8 bits is coupled to the input of the NOR gate, and the output of the NOR gate is connected to the bistable device. 17. The circuit according to claim 16, which is connected. 18. The bistable device includes a flip-flop, and the switch controls its clock. an input, said feedback means being coupled to said reset input; The circuit according to item 17.