JPS5949288U - Tamper prevention circuit for billing device - Google Patents
Tamper prevention circuit for billing deviceInfo
- Publication number
- JPS5949288U JPS5949288U JP14463882U JP14463882U JPS5949288U JP S5949288 U JPS5949288 U JP S5949288U JP 14463882 U JP14463882 U JP 14463882U JP 14463882 U JP14463882 U JP 14463882U JP S5949288 U JPS5949288 U JP S5949288U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- billing device
- memory
- prevention circuit
- tamper prevention
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Lock And Its Accessories (AREA)
- Control Of Vending Devices And Auxiliary Devices For Vending Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は課金装置の一例を示す概略図、第２図は端末機
の一例を示すブロック図、第３図はキーホルダーの一例
を示す概略的断面図、第４図はメモリ検出セット部の一
例を示す回路図、第５′図〜第７図はメモリ検出セット
部の動作説明図である。
ＰＣ・・・フォトカプラ、ＥＸ・・・排他的オア回路。Fig. 1 is a schematic diagram showing an example of a charging device, Fig. 2 is a block diagram showing an example of a terminal, Fig. 3 is a schematic sectional view showing an example of a key chain, and Fig. 4 is an example of a memory detection set part. The circuit diagrams shown in FIGS. 5' to 7 are explanatory diagrams of the operation of the memory detection set section. PC...Photocoupler, EX...Exclusive OR circuit.
Claims (1)
子を持つキーホルダーと、このキーホルダーの挿入によ
り負荷を使用させると共に第２の端子が前記第１の端子
と接続されて前記メモリに情報を書込む端末機と、前記
キーホルダーの挿入により前記メモリから情報を読取る
親機とを有する課金装置において、前記第２の端子の電
圧変化を検出する手段を備え、この手段の出力信号によ
り前記負荷を使用させるようにした課金装置のいたずら
防止回路。A key chain having a built-in memory and a first terminal to which the memory is connected, and a second terminal connected to the first terminal to allow a load to be used by inserting the key chain and to transmit information to the memory. The billing device has a terminal for writing information and a master device for reading information from the memory by inserting the key chain, further comprising means for detecting a voltage change at the second terminal, and controlling the load using an output signal of the means. A tamper-proof circuit for the billing device that was made available for use.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14463882U JPS5949288U (en) | 1982-09-24 | 1982-09-24 | Tamper prevention circuit for billing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14463882U JPS5949288U (en) | 1982-09-24 | 1982-09-24 | Tamper prevention circuit for billing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5949288U true JPS5949288U (en) | 1984-04-02 |
Family
ID=30322486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14463882U Pending JPS5949288U (en) | 1982-09-24 | 1982-09-24 | Tamper prevention circuit for billing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5949288U (en) |
-
1982
- 1982-09-24 JP JP14463882U patent/JPS5949288U/en active Pending
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