JPS5949018A - Analog switch circuit - Google Patents

Analog switch circuit

Info

Publication number
JPS5949018A
JPS5949018A JP57160028A JP16002882A JPS5949018A JP S5949018 A JPS5949018 A JP S5949018A JP 57160028 A JP57160028 A JP 57160028A JP 16002882 A JP16002882 A JP 16002882A JP S5949018 A JPS5949018 A JP S5949018A
Authority
JP
Japan
Prior art keywords
gate
transmission gate
turned
type
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57160028A
Other languages
Japanese (ja)
Other versions
JPH0227851B2 (en
Inventor
Yoshiro Nakayama
仲山　芳郎
Noritoshi Abe
安部　文紀
Takafumi Nagasawa
長沢　尚文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP57160028A priority Critical patent/JPS5949018A/en
Priority to KR1019830004042A priority patent/KR860001485B1/en
Priority to US06/531,178 priority patent/US4611135A/en
Publication of JPS5949018A publication Critical patent/JPS5949018A/en
Publication of JPH0227851B2 publication Critical patent/JPH0227851B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H03K17/163—Soft switching
    • H03K17/164—Soft switching using parallel switching arrangements

Landscapes

  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce switch noises and to transmit an analog signal with no distortion, by connecting a transmission gate in parallel to another transmission gate of a larger size. CONSTITUTION:When a control signal D is changed to H from L, a delay signal D1 and its inverse signal obtained from a circuit 15 are applied to n and p type TR10 and 9 of a transmission gate 8. Therefore, the gate 8 is not immediately turned on, and a transmission gate 11 connected in parallel is immediately turned on. In this case, just a small switch noise is generated since the size of the gate 11 is small. Then a large switch noise is produced when the gate 8 is turned on. This switch noise, however, is absorbed by the input side via the gate 11 since the gate 11 is previously turned on and furthermore an input signal source 7 has a low impedance compared with a load 6. When the signal D is turned to L, it is tried to turn off the gate 8 after a delay time elapses. In this case, the noises produced when the gate 8 is turned off is also absorbed by the input side since the gate 11 is turned on.

Description

【発明の詳細な説明】 （イ）技術分野 本発明は、絶縁ゲート電界効果トランジスタを用いて、
アナログ信号の伝送を制御するアナログスイッチ回路に
関する。[Detailed description of the invention] (a) Technical field The present invention uses an insulated gate field effect transistor to
The present invention relates to an analog switch circuit that controls the transmission of analog signals.

（ロ）従来技術 一般に、アナログスイッチ回路は、第１図に示すように
、第１及び第２の電極が各々共通接続されたＰ型及びＮ
型の絶縁ゲート電界幼果トランジスタ（以１、単にトラ
ンジスタと呼ぶ）（１）及び（２）より構成される伝送
ゲート（≦）を有しており、各々の共通電極が入力端子
（４）及び出力端子（５）に接続されている。又、出力
端子（５）及び入力端子（４）は、負荷（６）及びこの
負荷（６）より低インビーダン子の入力信号源（７）に
接続される。そして、Ｎ型及びＰ型のトランジスタ（２
）及び（１）や各ゲートには、制御信号り及１びその反
転信号が印加され、伝送ゲート（≦）のオンオフ制御が
行なわれる。(B) Prior Art Generally, as shown in FIG. 1, analog switch circuits have P type and N
It has a transmission gate (≦) consisting of an insulated gate electric field infant transistor (hereinafter simply referred to as a transistor) (1) and (2) of the type, and each common electrode is connected to an input terminal (4) and It is connected to the output terminal (5). Further, the output terminal (5) and the input terminal (4) are connected to a load (6) and an input signal source (7) having a lower impedance damper than the load (6). Then, N-type and P-type transistors (2
) and (1), and the control signal 1 and its inverted signal are applied to each gate, and the on/off control of the transmission gate (≦) is performed.

（ハ）従来技術の欠点 一般に、アナログ信号を伝送する伝送ゲートは、オン抵
抗を小さくしなくてはならないため、伝送ゲートを構成
するＰ型及びＮ型トランジスタのサイズを、一般のトラ
ンジスタに比べ大きくしなくてはならない。しかし／よ
から、トランジスタのサイズを大きくすると、ゲート・
ソース容量及びゲート・ドレイン容量も大きくなってし
まうため、従来技術では、伝送ゲートのオンオフ切替時
に、ゲートの電圧変化がこれらの容ｆＡ　’ｃ介して出
力に漏れ込み、切替ノイズが出力側に現われてしまうと
いう欠点があった。(c) Disadvantages of conventional technology Generally, transmission gates that transmit analog signals must have low on-resistance, so the sizes of the P-type and N-type transistors that make up the transmission gate are made larger than ordinary transistors. I have to. However, if you increase the size of the transistor, the gate
Since the source capacitance and gate/drain capacitance also become large, in the conventional technology, when the transmission gate is switched on and off, the gate voltage change leaks into the output through these capacitors fA'c, and switching noise appears on the output side. There was a drawback that

に）発明の目的 本発明は、上述の欠点に鑑み、伝送ゲートに該伝送ゲー
トよりサイズの小さい伝送ゲートヲ並列接続する）こと
により、切替ノイズを極力減少させ、アナログ信号を否
なく出力端子に伝送する新規なアナログスイッチ回路を
提供するものである。In view of the above drawbacks, the present invention reduces switching noise as much as possible by connecting a transmission gate in parallel with a transmission gate smaller in size than the transmission gate, and transmits analog signals to the output terminal without fail. The present invention provides a novel analog switch circuit that

０→実施例 第２図は、本発明によるアナログスイッチ回路の実施例
を示す回路図であり、（甲は第１及びガ（２の電極が各
々共通接続され、共通電極が各々入力端子（４）及び出
力端子（５）に接続されたＰ型及びＮ型トランジスタ（
９）及び（１０）より構成される伝送ゲートであり、出
力端子（５）及び入力端子（４）には、第１図と同様、
負荷（６）及び負荷より低インピーダンスの入力信号源
（力が接続される。（ＩＩ）は第１及びｉ２の電極が各
々共通接続されたＰ型及びＮ型トランジスタ（１２）及
び（１３１より構成され、伝送ゲート（穀よりサイズの
小さい伝送ゲートであり、この伝送ゲート（す）が伝送
ゲート億）に並列に接続されている。又、第２図におい
て、α４）は制御信号Ｄｋ大入力る制御端子、０暖及び
（１６）は遅延回路、（１７）はＯＲゲート、（［→及
び（Ｊ傷はインバータである。0→Embodiment FIG. 2 is a circuit diagram showing an embodiment of the analog switch circuit according to the present invention. ) and P-type and N-type transistors (
9) and (10), and the output terminal (5) and input terminal (4) have the same terminals as in Fig. 1.
The load (6) and the input signal source (power) having a lower impedance than the load are connected. (II) is composed of P-type and N-type transistors (12) and (131) whose first and i2 electrodes are respectively connected in common. The transmission gate (a transmission gate smaller in size than a grain) is connected in parallel to the transmission gate (100).In addition, in Fig. 2, α4) inputs the control signal Dk. Control terminals, 0 and (16) are delay circuits, (17) is an OR gate, ([→ and (J) are inverters.

そこで、制御信号、Ｄが「Ｌ」から「１１」になると、
伝送ゲート（鞄のＮ型及びＰ型トランジスタ００）及び
（９）のゲートには、制御信号りが遅延された信号Ｄ１
　及びその反転信号が印加されているので、伝送ゲート
（書）はすぐにはオンしないが、並列接続された伝送ゲ
ートＩのＮ型及びＰ型トランジスタ０３）及び（１２）
のゲートには、ＯＲゲートα力を介して制御信号りが即
座に印加されるため、伝送ゲート（ｌ−Ｄはすぐにオン
する。このオン時には、伝送ゲート（す）のサイズが小
さいため、小さな切替ノイズしか発生しない。そして、
その後、遅延信号Ｄ□が１−Ｈ」となって、伝送ゲート
（８）がオンする際、大きな切替ノイズが発生するが、
先に並列に接続された伝送ゲー）（ＩＩ）がオンしてお
り、しかも、出力端子（５）に接続された負荷（６）に
比べ、入力信号源（力の方が低インピーダンスなので、
発生した切替ノイズは並列に接続された伝送ゲート（１
１）ヲ介して、入力側に吸収されてしまい、負荷（６）
側には切替ノイズはほとんど現われない。Therefore, when the control signal D changes from "L" to "11",
The transmission gate (N-type and P-type transistor 00 of the bag) and the gate of (9) receive a signal D1 which is a delayed control signal.
Since the transmission gate and its inverted signal are applied, the transmission gate does not turn on immediately, but the N-type and P-type transistors 03) and (12) of the transmission gate I connected in parallel
Since the control signal is immediately applied to the gate of 1 through the OR gate α, the transmission gate (LD) is immediately turned on.At this time, since the size of the transmission gate is small, Only small switching noise occurs.And,
After that, when the delay signal D□ becomes 1-H and the transmission gate (8) turns on, a large switching noise is generated.
The transmission gate (II) connected in parallel earlier is on, and the impedance of the input signal source (power) is lower than that of the load (6) connected to the output terminal (5).
The generated switching noise is transmitted through the transmission gates (1
1) The load (6) is absorbed by the input side through the
Almost no switching noise appears on the side.

又、制御信号りが「Ｈ」から１Ｌ、Ｊになると、遅延回
路（１５）の遅延時間経過後、先ず、信号Ｄ□が「Ｌ」
となり、伝送ゲート（β）がオフしようとする。Also, when the control signal D changes from "H" to 1L and J, the signal D□ first becomes "L" after the delay time of the delay circuit (15) has elapsed.
Therefore, the transmission gate (β) is about to turn off.

ところが、この時、遅延信号Ｄ２は未だ「Ｈ」であって
、ＯＲゲート０７）の出力ＧもｒＨＪなので、□′伝送
ゲート（ｖ）はオン状態にある。このため、伝送ゲート
（ツがオフする際、大きな切替ノイズが発生するが、オ
ン時と同様、この切替ノイズは並列に接続された伝送ゲ
ート（す）を介して入力側に吸収されてしまい、負荷（
６）側には現われない。その後、遅延信号Ｄ２が「Ｉ、
」になるため、伝送ゲート（す）もオフになる。このよ
うに、オン時にもオフ時にも切替ノイズは負荷（６）側
にほとんど現われない。However, at this time, the delay signal D2 is still "H" and the output G of the OR gate 07) is also rHJ, so the □' transmission gate (v) is in the on state. For this reason, when the transmission gate turns off, a large switching noise is generated, but just as when it is turned on, this switching noise is absorbed by the input side via the transmission gate connected in parallel. load(
6) Does not appear on the side. After that, the delayed signal D2 becomes “I,
”, the transmission gate is also turned off. In this way, almost no switching noise appears on the load (6) side both when on and when off.

次に、伝送ゲートを構成するｐ　、ｊＪす及びＮ型トラ
ンジスタのゲートを定電流で制御する場合の実施例につ
いて、第３図を参照しながら説明する。Next, an embodiment in which the gates of the p-type, jj-type and n-type transistors constituting the transmission gate are controlled by constant current will be described with reference to FIG.

第３図において、入力信号源（７）からのアナログ信号
を負荷（６）に伝送するための伝送ゲート（印には、第
２図の実施例と同様、この伝送ゲート（β）よりサイズ
の小さい伝送ゲート（Ｌりが、並列に接続されている。In Fig. 3, a transmission gate (marked with a mark) for transmitting an analog signal from an input signal source (7) to a load (6) is larger in size than this transmission gate (β), as in the embodiment of Fig. 2. Small transmission gates (L) are connected in parallel.

又、第３図において、（２１（２１＋（２乃０；３）は
定電流源、（２４）（２５）噛）（２−７）は一対のＰ
型及びＮ型トランジスタより（ＩＩ７成され、制御信号
りに応じて伝送ゲート（β）及び（す）全＋１“ｑ成す
るＰ型及びＮ型トランジスタのゲートを定電流源に切替
接続するための切替スイッチ、ｆｆ、７ｔｔｉは遅延回
路、◇刹はＯＲゲート、（３０）及び（３１）はインバ
ータである。尚、以下の説明においては、全ての定電流
は同一とする。Also, in Fig. 3, (21 (21 + (2~0; 3) is a constant current source, (24) (25)) (2-7) is a pair of P
For connecting the transmission gate (β) and the gates of the P-type and N-type transistors (total +1'q) to a constant current source according to the control signal. The changeover switches, ff, and 7tti are delay circuits, ◇ is an OR gate, and (30) and (31) are inverters.In the following description, all constant currents are assumed to be the same.

そこで、制御信号りがｒＬＪからＪ　ＨＪになると、切
替スイッチのＮ型トランジスタｃｑ２１（、翌ｑびＰ型
トランジスタＣ３４）＜３５１がオンするので、伝送ゲ
ート（β）のＰ型及びＮ型トランジスタ（９）及びＧＯ
）の各ゲートは、各々、定電流源（２０）及び０１）に
接続され、又、並列に接続された伝送ゲート（す）のＰ
型及びＮ型トランジスタ（１２１及び０階の各ゲートは
、各々、定電流源（２り及び（２３に接続される。この
ため、ゲートと基板との間の容量、即ち、ゲート容量Ｃ
１ｐ及びＣＩＮトＣ２，及０’　Ｃ２Ｎは、各々、充電
が開始される。ところが、伝送ゲート（す）は伝送ゲー
ト勢）よりサイズが小さいため、ゲート容量Ｃ２Ｐ及び
Ｃ２、は、各々Ｃ１Ｐ及びＣＩＮより容量が小さく、従
って、サイズの小さな伝送ゲート（ｊｌｌ）が伝送ゲー
ト億）より先にオンする。このため、第２図の実施例と
同様、オン時の切替ノイズは伝送ゲー１４１）を介して
入力側に吸収されてしまい、負荷（６）側には現われな
い。Therefore, when the control signal changes from rLJ to JHJ, the N-type transistor cq21 (and the next P-type transistor C34) of the changeover switch turns on, so the P-type and N-type transistors ( 9) and GO
) are respectively connected to constant current sources (20) and 01), and the transmission gates (20) and 01) are connected in parallel to each other.
The gates of type and N type transistors (121 and 0th floor are connected to constant current sources (2 and (23), respectively. Therefore, the capacitance between the gate and the substrate, that is, the gate capacitance C
Charging of 1p, CINtoC2, and 0'C2N is started. However, since the transmission gate is smaller in size than the transmission gates, the gate capacitances C2P and C2 are smaller than C1P and CIN, respectively, so the smaller transmission gate (jll) is Turn on earlier. Therefore, as in the embodiment shown in FIG. 2, the switching noise when the switch is on is absorbed by the input side via the transmission gate 141) and does not appear on the load (6) side.

又、制御信号りがｒＨＪからｒＬＪになると、切替スイ
ッチのＰ型及びＮ型トランジスタ０６）及び（３７）ｔ
、Ｊ：、すぐにオンし、伝送ゲート申）のＰ型及びＮ型
トランジスタ（９）及びθ０の各ゲートは、各々、定電
流源（２υ及び（イ）に接続され、ゲート容量ＣＩＦ及
びＣＩＮは蓄えられた電荷は放電され始める。ところが
、制御信号りがｒＨＪからｒＬＪになっても、遅延回路
（２８）の遅延信号Ｄ工は未だｆ−ＨＪであって、ＯＲ
ゲー）（２９）の出力Ｇも「Ｈ」なので、伝送ゲート（
ＩＩ）はオン状態のままである。このため、放電が進み
伝送ゲート（８）がオフする際、大きな切替ノイズが発
生するが、オン時と同様この切替ノイズは、並列に接続
された伝送ゲートの）を介して入力側に吸収されてしま
い、負荷（６）側には現われない。その後、遅延信号Ｄ
□が「Ｌ」になるため、ＯＲゲート（２９）の出力Ｇも
ｒＬＪとなり、伝送ゲート０−Ｄを構成するＰ型及びＮ
型トランジスタ０２）及び（１３）のゲートは、切替ス
イッチのＰ型及びＮ型トランジスタ（泗及び０伽を介し
て、定電流源（２３）及び（２２１に各々接続される。Also, when the control signal changes from rHJ to rLJ, the P type and N type transistors 06) and (37) t of the changeover switch
, J:, immediately turned on, the gates of the P-type and N-type transistors (9) and θ0 of the transmission gate are connected to constant current sources (2υ and (a), respectively, and the gate capacitances CIF and CIN The accumulated charge starts to be discharged.However, even if the control signal changes from rHJ to rLJ, the delay signal D of the delay circuit (28) is still f-HJ, and the OR
Since the output G of the transmission gate (29) is also "H", the transmission gate (
II) remains on. Therefore, as the discharge progresses and the transmission gate (8) turns off, a large switching noise is generated, but like when it is turned on, this switching noise is absorbed by the input side via the transmission gate (8) connected in parallel. Therefore, it does not appear on the load (6) side. After that, the delayed signal D
Since □ becomes "L", the output G of the OR gate (29) also becomes rLJ, and the P type and N
The gates of the type transistors 02) and (13) are connected to the constant current sources (23) and (221), respectively, through the P type and N type transistors (02 and 0) of the changeover switch.

そして、ゲート容ｉ％−０２Ｆ及び０２Ｎに蓄えられた
電荷が放電され、伝送ゲート皓）はオフする０ 尚、第３図の実施例では、伝送ゲート（８）及び（す）
を構成するゲートに急峻に変化する矩形状の電圧が加わ
らず、ゲート電圧がなめらかに変化するので、より切替
ノイズの防止に効果がある。又、第３図の実施例におい
て、各定電流源の定電流値は限らずしも同一にする必要
がなく、例えば、伝送ゲート（β）と（す）のサイズ比
が１０＝１であり、定電流源体１）と（２渇の電流比及
びＣＤと（２３）の電流比をサイズ比とほぼ同じように
１０：１にした場合には、図中、Ａ点とＢ点の間に、さ
らに、遅延回路を挿入すればよい。Then, the charges stored in the gate capacitance i%-02F and 02N are discharged, and the transmission gates (8) and (3) are turned off.
Since a rectangular voltage that changes abruptly is not applied to the gate forming the gate, and the gate voltage changes smoothly, it is more effective in preventing switching noise. Furthermore, in the embodiment shown in FIG. 3, the constant current values of the respective constant current sources do not necessarily have to be the same; for example, the size ratio of the transmission gates (β) and (S) is 10=1. , when the current ratio of constant current sources 1) and (2) and the current ratio of CD and (23) are set to 10:1, which is almost the same as the size ratio, between points A and B in the figure. Additionally, a delay circuit may be inserted.

（へ）効果 本発明によるアナログスイッチ回路は、上述の如く、非
常に簡単な回路で切替ノイズを大幅に減少させることが
でき、従って、アナログ信号を歪なく伝送することが可
能となる。(f) Effects As described above, the analog switch circuit according to the present invention can significantly reduce switching noise with a very simple circuit, and therefore can transmit analog signals without distortion.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のアナログスイッチ回路を示す回路図、第
２図は本発明によるアナログスイッチ回路の実施例を示
す回路図、第３図は本発明によるアナログスイッチ回路
の他の実施例を示す回路図である。 主な図番の説明 （１）（９）θつ・・・Ｐ型トランジスタ、　（２）（
１（１）（Ｌ３）・・・Ｎ型トランジスタ、（３）（８
）０υ・・・伝送ゲート、　（４）・・・入力端子、　
（５）・・・出力端子、　（６）・・・負荷、　（７）
・・・入力信号源、　（１！’１）（Ｉｒ）（２功・・
・遅延回路、θη（２１ト・・ＯＲゲート、（１と９（
ｔ！］）（３（ｌｌ（’ＩＩ）・・・インバータ、　（
イ）（２１）（２卯、３）・・定電δ１こ源、φ）（穴
（２ｊｉ）（２７）・・・切替スイッチ。 １図 り 第２図 第７（図FIG. 1 is a circuit diagram showing a conventional analog switch circuit, FIG. 2 is a circuit diagram showing an embodiment of the analog switch circuit according to the present invention, and FIG. 3 is a circuit diagram showing another embodiment of the analog switch circuit according to the present invention. It is a diagram. Explanation of main drawing numbers (1) (9) θ... P-type transistor, (2) (
1 (1) (L3)...N-type transistor, (3) (8
)0υ...transmission gate, (4)...input terminal,
(5)...Output terminal, (6)...Load, (7)
...Input signal source, (1!'1) (Ir) (2)
・Delay circuit, θη(21t・・OR gate, (1 and 9(
T! ])(3(ll('II)...Inverter, (
a) (21) (2 u, 3)...Constant current δ1 source, φ) (hole (2ji) (27)...switch switch. 1 diagram 2 figure 7 (figure

Claims (1)

【特許請求の範囲】[Claims] １）負荷が接続される出力端子と、前記負荷より低イン
ピーダンスの入力信号源に接続される入力端子と、第１
及び第２の電極が各々共通接続されたＰ型及びＮ型の絶
縁ゲート型電界効果トランジスタより構成され、各々の
共通電極が前記入力端子及び前記出力端子に接続された
ｔＰＪｌの伝送ゲートとを備え、該第１の伝送ゲートを
介してアナログ信号を伝送するアナログスイッチ回路に
おいて、第１及び第２の電極が各々共通接続されたＰ型
及びＮ型の絶縁ゲート型電界効果トランジスタより構成
され、前記第１の伝送ゲートよりサイズの小さい第２の
伝送ゲートを前記第１の伝送ゲートに並列接続し、前記
第２の伝送ゲートをオンさせた状態で前記第１の伝送ゲ
ートのオンオフ切替を行なうようにしたことを特徴とす
るアナログスイッチ回路。1) an output terminal connected to a load, an input terminal connected to an input signal source having a lower impedance than the load;
and a P-type and N-type insulated gate field effect transistor whose second electrodes are respectively connected in common, and each common electrode includes a transmission gate of tPJl connected to the input terminal and the output terminal. , an analog switch circuit for transmitting an analog signal through the first transmission gate, which is composed of P-type and N-type insulated gate field effect transistors whose first and second electrodes are commonly connected, respectively; A second transmission gate smaller in size than the first transmission gate is connected in parallel to the first transmission gate, and the first transmission gate is switched on and off while the second transmission gate is turned on. An analog switch circuit characterized by:
JP57160028A 1982-09-13 1982-09-13 Analog switch circuit Granted JPS5949018A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP57160028A JPS5949018A (en) 1982-09-13 1982-09-13 Analog switch circuit
KR1019830004042A KR860001485B1 (en) 1982-09-13 1983-08-30 Analog switch circuit
US06/531,178 US4611135A (en) 1982-09-13 1983-09-09 Analog switch circuit and signal attenuator employing an analog switch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57160028A JPS5949018A (en) 1982-09-13 1982-09-13 Analog switch circuit

Publications (2)

Publication Number Publication Date
JPS5949018A true JPS5949018A (en) 1984-03-21
JPH0227851B2 JPH0227851B2 (en) 1990-06-20

Family

ID=15706392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57160028A Granted JPS5949018A (en) 1982-09-13 1982-09-13 Analog switch circuit

Country Status (1)

Country Link
JP (1) JPS5949018A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58146131A (en) * 1982-02-25 1983-08-31 Toshiba Corp Mosfet switch circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58146131A (en) * 1982-02-25 1983-08-31 Toshiba Corp Mosfet switch circuit

Also Published As

Publication number Publication date
JPH0227851B2 (en) 1990-06-20

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