JPS5948808A - Signal generator - Google Patents

Abstract

PURPOSE:To simplify the constitution of a signal generator, by providing an oscillator which produces the clock signal corresponding to the video period of the composite video signal of the standard TV system and generating the memory control pulse, the control pulse and various types of synchronizing signals based on the clock signal. CONSTITUTION:The component encoded digital video signal is impressed to a memory circuit 11 via an input terminal 1. A master oscillator 2 of a signal generator 6 produces a clock signal having a frequency of (148X8) times as high as the horizontal scanning frequency and applies it to a frequency divider 3. A decoder 4 produces the horizontal and vertical synchronizing signals, burst flag pulse and vertical blanking pulse, etc. from the pulse train of the divider 3 and delivers them to output terminals 51-5n respectively. At the same time, the decoder 4 delivers control pulses to a switch circuit 7 and D/A converters 12-14 and also delivers the analog luminance signal and the 1st and the 2nd color difference signals to output terminals 15-17. The control signals are converted into color video signals of the standard TV system by the signals of terminals 15-17 and terminals 51-5n. Thus the constitution can be simplified for a signal generator.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a signal generation device, and in particular, it generates various synchronization signals related to video signals, pulses, etc. for accessing a memory circuit for storing pixel data, respectively. The present invention relates to a signal generating device that generates a signal using a clock signal.

Prior Art Conventionally, digital audio signals obtained by digital pulse modulation such as pulse code modulation (PCM) are added with digital video signals of auxiliary information such as color still images, and are recorded on a disc-shaped recording medium (hereinafter referred to as Digital audio discs are known, in which changes in bit strings are recorded in chronological order on a disc (referred to as a "disc"). Such digital audio discs generate the green signal by changing the light intensity of the reflected light or transmitted light from the disc, or by changing the capacitance formed between the disc and the reproducing electrode. Read 9 is played.

Inside this digital audio disc playback device,
In addition to the digital audio signal reproducing circuit, the digital video signal reproducing circuit described above is provided. Furthermore, within this digital video encoding and reproducing circuit, there is a memory circuit for accumulating and reading out digital video signals (pixel data), a control circuit for accessing this memory circuit, and six pixels read out from the memory circuit. an encoder that outputs a composite video signal of a predetermined standard television format after passing the data through a D/A converter; and various synchronization signals (e.g., vertical synchronization signal, horizontal synchronization signal, It is comprised of a signal generator that generates a burst flag pulse, a vertical blanking pulse, etc.), a memory control pulse for accessing the memory circuit, and other components.

Problems to be Solved by the Invention However, in the above-mentioned signal generation device, the PV synchronization era generation circuit and the memory control pulse generation circuit, which generate various synchronization signals related to the video signal, are separately dedicated. Since the clock oscillator No. 1g is used, the circuit becomes complicated and expensive, and there is also a drawback that a beat occurs between the output clock signals of the two clock signal oscillators.

Therefore, an object of the present invention is to provide a signal generation device that can share the same oscillator and generate TV synchronization signals, memory control pulses, etc. by selecting the output clock signal frequency of the oscillator to a predetermined frequency. .

Means for Solving the Problems The present invention sets the video period of a standard television composite video signal to a period that is approximately an integer multiple of the number of addresses required to write pixel data for the -scanning axis into a memory circuit. 2 of the horizontal scanning frequency of the composite video signal.
A single oscillator that generates and outputs a clock signal selected to have a frequency that is an integer multiple of the above frequency, and the output clock signal of this oscillator is supplied to the memory control pulse, D/A converter control pulse, and various synchronization signals to the above clock. The decoder has the same structure as a decoder that generates signals based on signals, and one embodiment thereof will be described below with reference to FIGS. 1 to 5.

Embodiment FIG. 1 shows a block system diagram of an embodiment of a signal generator according to the present invention. This embodiment is applied to a reproducing apparatus for a digital audio disc recorded by the digital video signal recording method previously proposed by the present applicant in, for example, Japanese Patent Application No. 57-67818. In the above recording method, the product of the number of pixels per scanning line and the effective number of scanning lines for one screen in a standard television system is extremely close to 2;
By generating a digital video signal selected to have a value not exceeding 218 and recording it on a recording medium, a commercially available memory element can be effectively used as a memory circuit for storing a reproduced digital video signal in a device that reproduces this recording medium. The address signal generation circuit can be commonly configured.

Here, as an example, three channels of digital audio signals and one channel of digital video signal are recorded on a disk in chronological order in the signal format shown in FIG. can be transmitted using component encoding. In Figure 2, 5YNC is a frame (block)
Ch-1 to ch-3 are the digital audio signals of the above three channels, and Ch-4 is the above one.
16 bits of one channel digital video signal,
Each multiplex position of one word is shown. Also, P and Q shown in Figure 2
are 16-bit error code reduction signals, for example, p=w1■Vv2■W3■W4 (
1) Q=', I''-Wl(IT3-W2■T2-W3■
'l'-W4 This is a signal generated according to the equation (2). However, (1).

(2) In the formula, W, , W2. 'A'B, W4 is c
Each 16-bit digital signal of h-1 to ch-4 (the base is a digital signal in each optical block),
'P is an auxiliary matrix of a predetermined polynomial, and ■ represents addition modulo 2 for each corresponding bit.

Furthermore, in FIG. 2, CRC is a 23-bit error code detection signal, and Ch-1 to Ch-4, which are arranged in the same block,
This is the 23-bit remainder obtained when each word of P and Q is divided by a generator polynomial of x23+x5+X+X+1, and during playback, the 9th to 12th bits of the same block are
The signal up to the 7th bit is divided by the generator polynomial, and when the resulting remainder is zero, it is used to detect that there is no error. Furthermore, in Figure 2, Adr is used for random access, etc.? Each pit data is distributed by the lil control signal, and 1 bit data is distributed in 1 block.
For example, all bits of the control signal are transmitted in 196 blocks (ie, the control signal is composed of 196 bits).

lc and U are 2 bits for reserve called user's pit. As shown in Fig. 2, a total of 130 bits from YsYNc to U constitute one block, and the digital signal is divided into blocks at a sampling frequency of 44.1 kHz, for example, a digital audio signal.
It is synthesized at the same frequency as z and recorded in time series. Therefore, when the rotational speed of the disk is 90 Orpm, recording and reproduction are performed in 2940 blocks per rotation of the disk, so the above 196-bit control signal is
．． It is recorded and played back 15 times in one rotation period IHj.

The digital video signal in which one word is transmitted at the position of Ch-4 mentioned above is, for example, a digital luminance signal sampled at a sampling frequency of 9 MHz and then quantized with an 8-pit quantization number, and 2. It consists of two types of digital color difference signals sampled with 25 hil-1z and then quantized with 8 bits of quantization, and the data of four sampling points of the digital luminance signal and the data of two digital color difference signals. A total of six pieces of data, each of which is data for one sample point, are transmitted in time series as a unit. Here, the number of sample points per one scanning line of the digital luminance signal is approximately 456 when the horizontal scanning frequency is 15.6251 kHz, if only the image information is transmitted without transmitting the horizontal blanking period, etc. By setting the number of effective scanning lines for frame 17 to 572, as mentioned above, the number of pixels per scanning line (number of sample points) and the number of effective scanning lines for one screen can be The product is very close to 218 and can be taken as a value not exceeding 2. As a result, the digital luminance signal can be efficiently stored in four 64 kRAMs (random access memories) per bit, and the two types of digital color difference signals can be stored in four 64 kRAMs (random-access memories), and the number of sampling points of the scanning line is smaller than that of the digital luminance signal. -, so there are 64 bits each, one per bit.
Can be efficiently stored in kRAM. Therefore, if the pixel data of the − sample point is 8 bits, then 48 (=8×(4+
1+1)) of 64 kRAMs can efficiently store one frame of the component-encoded digital video signal.

Note that one unit of pixel data for transmission of a digital video signal (i.e., four digital luminance signal pixel data,
Six pieces of pixel data (one each of the two types of digital color difference signal pixel data) are stored at the same address in the memory circuit. Therefore, here, the number of sample points per scanning line of the digital luminance signal is 456, and the number of sample points per scanning line of the two types of digital color difference signals is 114 (-
4), the pixel data of the digital video signal for the -traversing line is stored in the memory circuit 11 shown in FIG. 1, which will be described later.
114 addresses, respectively.

During the signal played from a digital audio disc,
The component encoded digital video signal described above is serially applied to the memory circuit 11 via the input terminal 1 shown in FIG. Further, in FIG. 1, the master oscillator 21, frequency divider 3, and decoder 4 constitute a signal generating device 6.

Next, the output clock signal frequency of the master oscillator 2 will be explained. As is well known, the video period during which image information is to be transmitted is -horizontal synchronization period (
I H) Shorter than T2. As will be described later, the memory circuit 11 reads out the accumulated pixel data during this video period T1, and inputs it to the input terminal l during the horizontal blanking period l112T.
Assuming that incoming pixel data is controlled to be stored, the clock signal that is the basis for generating the memory control pulse for accessing the memory circuit 11 has a cycle within the video period Ill and the -scanning line. Because it is necessary to sequentially read out pixel data from 14 addresses, it is desirable in terms of circuit configuration that the video period TI be divided into 114 or an integral multiple thereof. Furthermore, in order to generate various synchronization signals, it is desirable in terms of circuit configuration that the repetition frequency of the clock signal is an integral multiple of the horizontal scanning frequency fII.

Therefore, if the video period '1'1 is divided into 114 parts, the IH period T2 will be divided into 141 parts. In order to obtain the required resolution, each division interval (denoted by K)
If it is divided into 8, the output clock signal frequency of master oscillator 2 will be 141 x 8 x fH (
However, fH is the horizontal scanning frequency).

The clock signal taken out from the master oscillator 2 is supplied to a frequency divider 3, where the clock signal is divided by a required frequency division ratio into a plurality of pulse trains with different repetition frequencies, and then sent to a decoder 4, respectively. Figure 4 (5) shows the waveform of the clock signal taken out from the master oscillator 2, in which 8 pulses are generated in the - division interval (one time period of IH), and 41 pulses are generated in the video period. 114×8 pulses are output as a clock signal. The decoder 4 generates a horizontal synchronization signal, a vertical synchronization signal, a burst flag pulse, a vertical blanking pulse, etc. from the pulse train from the frequency divider 3, and sends these TV synchronization signals to output terminals 5t to 5n and an encoder (not shown). ) Output to others.

Further, as shown in FIG. 5, the decoder 4 generates a switching pulse (data pulse L!) with a repetition frequency of IH (=141 K) and a pulse width of 114, and a pulse with a repetition frequency of 141 fH, respectively. 7. During the period 114 shown in FIG. 5 when the switching pulse is at a high level (that is, the video period), the switch circuit 7 outputs a pulse with a repetition frequency of 141 fn to the read address counter 8b. During the period 27 in which the switching pulse is at a low level (that is, the horizontal blanking period), a pulse with a repetition frequency of 141 f is switched and outputted to the write address counter 8a. Among the 16-bit output of the write address counter 8a, The output of the upper 8 bits is applied to the driver 9a, and the output of the lower 8 bits is applied to the driver 10a.Similarly, the output of the upper 8 bits and the lower 8 bits of the 16-bit output of the read address counter 8b is applied to the driver 9a. are applied to the drivers 9b and 10b, respectively.

The fourth signal generated by driver ga, 9bU decoder 4
Pulses CAW and CAR shown in Figure (E) (11 in Figure 5)
During the period indicated by 4, CAR is applied to the driver 9b, and during the next period 27i, CAvυ is applied to the driver 9a. Pulse R shown in (D)
AW, RAR are applied (however, BAR is applied to the driver 10b during the above period 114, and RAW is applied to the driver 10a during the next period 27).The drivers 9a, 9b are pulsed CAW, It is driven while CAR is at a low level and outputs the upper 8 bits of the address signal to the 8-pit address terminals of the memory circuit 11. Similarly, the drivers 10a and 10b are pulse RA
It is driven while W and RAR are at low level to output the lower 8 bits of the address signal to the address terminal of the memory circuit 11.

The decoder 4' is further provided in FIGS. 4(B), (C) and (I).
The pulses RAS, CAS', and WE shown in FIG.
First, the pulse plate W becomes low level, the driver 10a is driven, and the lower 8 bits of the input address signal from the address counter 8a are supplied to the address terminal of the memory circuit 11. In this state, When pulse Aha falls, the lower 8 bits of the address signal are taken into the memory circuit 11.Next, pulse dW becomes low level, and in this state pulse CAS falls, so the driver The upper 8 bits of the write address signal output from zN9a are taken into the memory circuit 11. Next, the pulse WE shown in FIG. Middle, input terminal 1
The input reproduced digital video signal is written to the above-mentioned predetermined address.

Here, the memory circuit 11 performs the sinking operation during the low level period of the pulse shown in FIG.
The 1-word, 16-bit digital video signal multiplexed at the position shown by Ch-4 in the figure is composed of two pixel data with a quantization number of 8 pits, and the two pixel data (one word) are transmitted at 44.1 kHz. Therefore, six pixel data are transmitted on average during the H period. These six pixel data are accumulated in a buffer memory (not shown) and written to the memory circuit 11 during the low level period (27K) shown in FIG. 5 above.

Pixel data for one scanning line is written into 114 bands of the memory circuit 11.

Note that the count value (address) of the address counter 8a is
There are 114 different values in the video period in IH, but if the pixel data to be written is, for example, a group of pixel data in one column at the far left of the screen, a group of pixel data in the second column, etc., The number increases by a certain number.

As mentioned above, the memory circuit 11 includes, for example, 48 64K
It is composed of a RAM, and when reading, during the period 114 of the pulse shown in Fig. 5, the image period in the first IH is determined by the reading address signal which counts pulses with a repetition frequency of 141 fH and increases by 1. from address O to 11
Read out the pixel data stored at address 3, then read out the pixel data stored at address 3, and then
During the video period within H, the pixel data stored at addresses 114 to 227 is read out, and in the same manner, pixel data for one scanning line is sequentially read out from address 114 for each video period. Note that during this readout, the pulse RAS
.

The 6C3 stone 61 is generated at the timing shown in FIGS. 4(B) to 4(E), but the pulse WE is always at a low level.

Among the pixel data read out from the memory circuit 11, the pixel data of the digital luminance signal is read out to the D/A converter 12, and the pixel data of the first digital color difference signal is read out to the D/A converter 12.
The pixel data of the second digital color difference signal is read out to the A converter 13, and further, the pixel data of the second digital color difference signal is read out to the VA converter 14. Here, during a period in which four pieces of pixel data of the digital luminance signal are read out, one piece of pixel data of each of the first and second digital color difference signals is read out. The D/A converter 12 receives the repetition frequency a141x4 generated by the decoder 4.
Digital-to-analog conversion is performed based on the control signal of fH and an analog luminance signal is output to the output terminal 15. On the other hand, the D/Ai converters 13 and 14 output the repetition frequency 141 generated by the decoder 4. Digital-to-analog switching is performed based on the control pulse of fu, and the first color difference signal obtained thereby is output to the output terminal 16, and the second color difference signal is output to the output terminal 1'7. .

Each analog signal taken out from these output terminals 15 to 17 is applied to an encoder (see diagram), and here, various synchronous 1M signals from output terminals 51 to 5n and standard television format (for example, NTSC system) is converted to a color video signal.

Thus, according to the non-embodiment, memory control #7
．． Ibuhyaku, box, decoy short, 6W1 stroke, work, WE.

A clock signal from a single master oscillator 2 is commonly used for the control clocks of the D/A transformers 12 to 14, the counting clocks of the address 7 counters 8a and 8b, and various TV synchronization signals. can be generated.

Application Example The above embodiment was applied to a playback device for a disc recorded using the digital video signal recording method previously proposed by the applicant, but it can also be applied to a playback device for a digital audio disc. The invention can also be applied to a device that reads pixel data from an image file in a predetermined format.

Effects As described above, according to the present invention, the clock signal frequency is selected to a predetermined frequency, so that the memory 1Tfll # pulse, the secondary side 1 pulse, and various 'rV synchronization signals are generated based on the output clock signal of the same master oscillator. This has the advantage that the circuit configuration can be simplified and the generation of beats between clock signals can be prevented.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the device of the present invention;
Fig. 2 is a diagram schematically showing the structure of one frame of a digital signal reproduced by a reproducing device in which the device of the present invention is used; 4(A) to 4(F) are time charts for explaining the operation of FIG. 1, respectively, and FIG. 5 is a diagram showing an example of an output signal waveform of a main part of the apparatus shown in FIG. 1. DESCRIPTION OF SYMBOLS 1... Digital video signal input terminal, 2... Master excavator, 3... Frequency divider, 4... Decoder, 5.
~5n...q' v synchronization signal output terminal, 6... Signal generator, 7... Switch circuit, 8a... Address counter for filling, 8b... Address counter for reading, 11. ...Memory circuit, 12-14...D/
A converter, 15... Luminance signal output terminal, 16.17.
...Color difference signal output terminal. Figure l Figure 4 Figure 5 - Ginseki

Claims (1)

[Claims] A memory circuit that stores pixel data and reads out the stored pixel data in a predetermined format and a memory control pulse for accessing the memory circuit and its control circuit respectively, and outputs the pixel data read out from the memory circuit]) A control pulse is output to the D/A converter that performs /A conversion, and further the 1) /A
In a signal generating device that outputs various synchronizing signals related to a video signal to an encoder which is supplied with an output signal of a converter and obtains a composite video signal of a standard television system, the video period of the composite video signal of the standard television system is , - having a period that divides pixel data for scanning lines into periods that are approximately an integral multiple of the number of addresses required to write into the memory circuit, and that is an integral multiple of 2 or more of the horizontal scanning frequency of the composite video signal. It consists of a single oscillator that generates and outputs a clock signal with a selected frequency, and a decoder that is supplied with the output clock signal of the oscillator and generates the memory control pulses, control pulses, and various synchronization signals based on the clock signal. A signal generator characterized by: