JPH0732477B2 - Digital video signal playback device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generator, and in particular, various common synchronizing signals related to a video signal, a pulse for accessing a pixel data storage memory circuit, and the like are commonly used. The present invention relates to a signal generator that generates by using a clock signal.

2. Description of the Related Art Conventionally, a digital audio signal obtained by digital pulse modulation such as pulse code modulation (PCM) is added with a digital video signal of auxiliary information such as a color still image so that a disc-shaped recording medium (hereinafter referred to as " It is known as a "digital disc", which is recorded in chronological order as changes in the pit train that intermittently occur. Such a digital audio disk detects a change in the light intensity of the reflected light or the transmitted light from the disk, or a change in the capacitance formed between the disk and the electrode of the reproducing needle, and the recorded signal is read and reproduced. It

In the playback device of this digital audio disk,
In addition to the digital audio signal reproducing circuit, the above digital video signal reproducing circuit is provided. Further, in the digital video signal reproducing circuit, a memory circuit for accumulating and reading a digital video signal (pixel data), a control circuit for accessing the memory circuit,
An encoder that outputs pixel data read from the memory circuit after passing through a D / A converter to output a composite video signal of a predetermined standard television system, and various synchronization signals (for example, vertical synchronization) supplied to this encoder. Signal, horizontal synchronizing signal, burst flag pulse, vertical blanking pulse, etc.) and a signal generator for generating a memory control pulse for accessing the memory circuit.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention Therefore, in the above-mentioned signal generator, the TV sync signal generation circuit for generating various sync signals related to the video signal and the memory control pulse generation circuit are separately dedicated clocks. Since the configuration has the signal oscillator, the circuit is complicated and expensive, and a beat is generated between the output clock signals of the two clock signal oscillators.

Therefore, an object of the present invention is to provide a signal generator capable of generating a TV sync signal, a memory control pulse, etc. by sharing the same oscillator by selecting the output clock signal frequency of the oscillator as a predetermined frequency. .

Means for Solving the Problems According to the present invention, pixel data obtained from a recording medium on which a digital video signal is recorded is input via a buffer memory, and the input pixel data is stored at a specified address, Of the accumulated pixel data, a memory circuit for reading out pixel data stored at a specified address in a predetermined format, and an input address of the pixel data is generated by counting an input clock signal. , A write address generation means for outputting this address to the memory circuit based on a write address generation timing signal, and an address of a storage destination of pixel data read from the memory circuit by counting an input clock signal, Address is read based on the address read timing signal. A read address generating means for outputting to the circuit, a digital / analog converter for performing digital / analog conversion of the pixel data read from the memory circuit based on a control signal, and a video signal for the output signal of the digital / analog converter. And an encoder for outputting a composite video signal of a standard television system by adding various synchronization signals related to, and a period for dividing the pixel data into a period of a number that is an integer multiple of the number of addresses required to write the pixel data in the memory circuit. Mochi,
And a single oscillator for generating and outputting a reference clock signal selected at a frequency that is an integer multiple of 2 or more of the horizontal scanning frequency of the composite video signal, and a write control signal that enables writing of data in the memory circuit. A read control signal that enables reading of data stored in the memory circuit, a write address generation timing signal and the clock signal of the write address generation means, and a read address generation timing signal to the read address generation circuit. And the clock signal, a control signal to the digital / analog conversion circuit, and various synchronization signals to the encoder,
A decoder for generating based on the reference clock signal of the single oscillator, and during the horizontal blanking period of the composite video signal, the clock signal and the write address generation timing signal are supplied to the write address generation means. Supplying and outputting a write address to the memory circuit, further outputting a write control signal to the memory circuit to write the pixel data to an address specified by the write address, and during the video period of the composite video signal, The clock signal and the read address generation timing signal are supplied to the address generating means to output the read address to the memory circuit, and further the read control signal is output to the memory circuit to be designated by the read address generating means. Read out the pixel data stored in the address .

Embodiment FIG. 1 shows a block system diagram of an embodiment of a signal generator according to the present invention. This embodiment is applied to a reproducing apparatus of a digital audio disc recorded by the digital video signal recording system proposed by the present applicant in Japanese Patent Application No. 57-67818. The above recording method, very close to the product 2 ¹⁸ to the number of effective scanning lines of one screen in the number of pixels and the standard television scheme per scan line, and 2
By generating a digital video signal selected to a value not exceeding ¹⁸ and recording it on a recording medium, a commercially available memory element can be effectively used as a memory circuit for storing a reproduced digital video signal in a device for reproducing this recording medium. In addition, the address signal generating circuit can be commonly configured.

Here, as an example, in a signal format as shown in FIG. 2, three channels of digital audio signals and one channel of digital video signals are recorded on a disk in a time series, and the digital video signals are component codes. It shall be transmitted in an encrypted format. In FIG. 2, SYNC indicates a multiplex position of a sync signal of a fixed pattern of 8 bits indicating the beginning of a frame (block), Ch-1 to Ch-3 are digital audio signals of the above three channels, and Ch-4 is The 16-bit, 1-word multiplex position of one channel digital video signal is shown. Further, P and Q shown in FIG. 2 are 16-bit error code correction signals, for example, P = W ₁ W ₂ W ₃ W ₄ (1) Q = T ⁴ · W ₁ T ³ · W ₂ T ² · W is a ₃ T · W ₄ (2) composed signal generated by the equation. However, (1),
In the equation (2), W ₁ , W ₂ , W ₃ , and W ₄ are 16-bit digital signals of Ch-1 to Ch-4 (normally digital signals in different blocks), and T is an auxiliary matrix of a predetermined polynomial. , Indicate addition modulo 2 for each corresponding bit.

Further in FIG. 2, CRC is 23 an error code detection signal of bits, Ch-1~Ch-4, P , each word of the Q for example ^{X 23 + X 5 + X 4} + X + 1 becomes generator polynomial to be arranged in the same block It is a 23-bit remainder obtained by dividing by, and the signals from the 9th bit to the 127th bit of the same block at the time of reproduction are divided by the above-mentioned generating polynomial, and when the remainder obtained by this is zero, It is used to detect that there is no error. Further, in FIG. 2, Adr is a control signal used for random access, etc., and each bit data is dispersed, and one bit is transmitted in one block. For example, all bits of the control signal are transmitted by 196 blocks. (That is, the control signal consists of 196 bits).

Furthermore, U is a spare 2 bit called a user's bit. Then, one block signal is composed of a total of 130 bits from SYNC to U shown in FIG. 2, and the digital signal is synthesized in this block unit at the same frequency as the sampling frequency 44.1 kHz of the digital audio signal, for example, and the time series. Recorded Therefore, when the number of rotations of the disk is 900 rpm, 2940 per disk-revolution
Since the block is recorded and reproduced, the 196-bit control signal is recorded and reproduced 15 times in the disk rotation period.

Further, the digital video signal in which one word is transmitted at the position of Ch-4 is, for example, a digital luminance signal quantized by a quantization frequency of 8 bits after being sampled at a sampling frequency of 9 MHz, and at 2.25 MHz respectively. It is composed of two types of digital color difference signals quantized by a quantization number of 8 bits after sampling, and data of four sample points of the digital luminance signal and one sample of each of the two types of digital color difference signals. A total of 6 points data are transmitted in time series. Here, the number of sampling points per scanning line of the digital luminance signal is such that when only the image information is transmitted without transmitting the horizontal blanking period, the horizontal scanning frequency is 15.6.
In case of 25kHz, it can be about 456, and by setting the number of effective scanning lines for one frame to be 572, the number of pixels per scanning line (the number of sampling points) and the effective scanning lines of one screen are as described above. very close to the product of the number 2 ^18, and can be a value not exceeding 2 ^18. As a result, the digital luminance signal can be efficiently stored in four 64kRAMs (random access memory) per bit, and the two types of digital color difference signals have the number of sampling points per scanning line of the digital luminance signal, respectively. Therefore, each bit can be efficiently stored in one 64 kRAM. Therefore, when the pixel data of one sample point is 8 bits, 48 (= 8 × (4 + 1 + 1)) 64 kRAMs can efficiently store the component-coded digital video signals for one frame.

It should be noted that digital video signal transmission of one unit of pixel data (that is, four digital luminance signal pixel data,
Six pieces of pixel data, each consisting of two kinds of digital color difference signal pixel data, are stored at the same address in the memory circuit. Therefore, here, the number of sampling points per scanning line of the digital luminance signal is 456, and the number of sampling points per scanning line of the two types of digital color difference signals is respectively. Therefore, the pixel data of the digital video signal for one scanning line is stored in the address 114 of the memory circuit 11 shown in FIG.

In the signal reproduced from the digital audio disc,
The component-encoded digital video signal is serially applied to the memory circuit 11 via the input terminal 1 shown in FIG. Also in FIG. 1, the master oscillator 2,
The frequency divider 3 and the decoder 4 form a signal generator 6.

Next, the output clock signal frequency of the master oscillator 2 will be described. As it is well known, video period upon which the image information is transmitted as shown by T ₁ in FIG. 3, one horizontal synchronization period (1
H) Shorter than T ₂ . As will be described later, the memory circuit 11 controls the accumulated pixel data to be read during this video period T ₁ and to accumulate the pixel data that has entered the input terminal 1 during the horizontal blanking period T ₂ −T _1. Memory circuit
The clock signal, which is the basis for generating the memory control pulse for the access of 11, has its cycle read pixel data sequentially from the 114 addresses where the pixel data for one scanning line is accumulated within the video period T ₁ . Due to need, the video period T ₁ is 114
Alternatively, it is desirable in terms of circuit configuration that the period is divided into an integral multiple thereof. To further generates various synchronizing signals, a repetition frequency of the clock signal, it is on the circuit configuration desired is an integer multiple of the horizontal scanning frequency f _H.

Therefore, if the video period T ₁ is divided into 114, the 1H period T ₂ is divided into 141. Further, assuming that each divided section (which is indicated by K) is divided into eight in order to obtain the required resolution, the output clock signal frequency of the master oscillator 2 becomes 141 × 8 × f _H (where f _H is the horizontal scanning). frequency).

The clock signal extracted from the master oscillator 2 is supplied to the frequency divider 3, where it is divided by a required frequency division ratio into a pulse train having a plurality of different repetition frequencies, and then supplied to the decoder 4. To be done. FIG. 4 (A) shows the waveform of the clock signal extracted from the master oscillator 2, and shows one divided section K (1H 8 pulses are generated for each video period, and 114 pulses are generated during the video period.
× 8 pulses are output as a clock signal. The decoder 4 generates a horizontal synchronizing signal, a vertical synchronizing signal, a burst flag pulse, a vertical blanking pulse, etc. from the pulse train from the frequency divider 3 and outputs these TV synchronizing signals as output terminals.
Output from 5 _{1 to} 5n to encoder (not shown) and others.

Further, the decoder 4 has a repetition frequency as shown in FIG.
In IH (= 141K), the pulse width 114K of when to quenching pulse (data gate pulse), outputs the repetition frequency 141 f _H pulse respectively generated by the switch circuit 7. The switch circuit 7 reads out a pulse having a repetition frequency of 141f _H during the 114K period (that is, the video period) in which the switching pulse shown in FIG.
Output to the 27K period (that is, the horizontal blanking period) during which the switching pulse is low level
The 141f _H pulse is switched and output to the write address counter 8a. Of the 16-bit output of the write address counter 8a, the output of the upper 8 bits is applied to the driver 9a, and the output of the lower 8 bits is applied to the driver 10a.
Similarly, the outputs of the upper 8 bits and the lower 8 bits of the 16-bit output of the read address counter 8b are applied to the drivers 9b and 10b, respectively.

The drivers 9a and 9b generate pulses ▲ ▼ and ▲ ▼ (shown in FIG. 5) generated by the decoder 4 and shown in FIG.
During the period indicated by 114K, ▲ ▼ is applied to the driver 9b,
In the next 24K period, ▲ ▼ is applied to the driver 9a. ) Is applied, and the drivers 10a and 10b generate pulses ▲ ▼ and ▲ shown in FIG.
▼ is applied (however, ▲ ▼ is 114K above)
Is applied to the driver 10b during the period of
Is applied to the driver 10a during the period. ) The drivers 9a and 9b are driven while the pulses ▲ ▼ and ▲ ▼ are at the low level, and the upper 8 bits of the address signal are stored in the memory circuit.
It outputs to the 8-bit address terminal of 11. Similarly, the drivers 10a and 10b are driven while the pulses ▲ ▼ and ▲ ▼ are at the low level, and output the lower 8 bits of the address signal to the address terminal of the memory circuit 11.

The decoder 4 further generates pulses ▲ ▼, ▲ ▼, and WE shown in FIGS. 4 (B), (C), and (F) and inputs them to a predetermined terminal of the memory circuit 11. As a result, at the time of writing, as shown in FIGS.
When ▼ becomes low level and the driver 10a is driven, the lower 8 bits of the write address signal from the address counter 8a are supplied to the address terminal of the memory circuit 11, and when the pulse ▲ ▼ falls in this state. Then, the lower 8 bits of the address signal are taken into the memory circuit 11. Next, the pulse ▲ ▼ becomes low level, and the pulse ▲ ▼ falls in this state. At this time, the upper 8 bits of the output write address signal of the driver 9a is taken into the memory circuit 11. Next, FIG. 4 (F)
Since the pulse WE shown in (1) rises, the memory circuit 11 writes the reproduced digital video signal received at the input terminal 1 at the above-mentioned predetermined address during the high level period of this pulse WE.

Here, the memory circuit 11 performs the writing operation in the low level period of the pulse shown in FIG. 5, but as described above, the 1-word 16-bit digital video signal multiplexed at the position shown as Ch-4 in FIG. Since it is two pixel data with a quantization number of 8 bits and two pixel data (1 word) are transmitted at 44.1 kHz, six pixel data are transmitted on average in the 1H period. The six pixel data are stored in a buffer memory (not shown) and written in the memory circuit 11 during the low level period (27K) shown in FIG.

Pixel data for one scanning line is written in the address 114 of the memory circuit 11.

The coefficient value (address) of the address counter 8a is 1H.
Although it takes 114 different values in each video period, when the pixel data to be written is, for example, the pixel data group in the leftmost column of the screen, the pixel data group in the second column, ... It will increase.

The memory circuit 11 is composed of, for example, 48 64 kRAMs as described above, and at the time of reading, 114K of pulse shown in FIG.
During the period of, the pixel address accumulated from addresses 0 to 113 is read during the video period within the first 1H by the read address signal which increases by 1 with the pulse of the repetition frequency 141f _H , and then within 1H. Pixel data accumulated at addresses 114 to 227 is read during the video period of, and similarly, pixel data for one scanning line is sequentially read from the address of 114 for each video period. During this reading, the pulses ▲ ▼, ▲ ▼, ▲ ▼, ▲
The black triangles are generated at the timings shown in FIGS. 4 (B) to 4 (E), but the pulse WE is always at the low level.

Of the pixel data read from the memory circuit 11, the pixel data of the digital luminance signal is read to the D / A converter 12, the pixel data of the first digital color difference signal is read to the D / A converter 13, and The pixel data of the second digital color difference signal is read out to the D / A converter 14. Here, one pixel each of the first and second digital color difference signals is read during a period in which four pixel data of the digital luminance signal are read. The D / A converter 12 performs digital-analog conversion based on the control pulse of the repetition frequency 141 × 4f _H generated by the decoder 4 and outputs an analog luminance signal to the output terminal 15. On the other hand, D / A converters 13 and 14
Respectively performs digital-analog conversion based on the control pulse of the repetition frequency 141f _H generated by the decoder 4, and outputs the first color difference signal thus obtained at the output terminal.
16 and outputs the second color difference signal to the output terminal 17.

Each analog signal taken out from these output terminals 15 to 17 is applied to an encoder (not shown), where various analog sync signals from the output terminals 5 _{1 to} 5n and a standard television system (for example, NTSC system) are used. ) Is converted into a color video signal.

Thus, according to this embodiment, the memory control pulse
▼, ▲ ▼, ▲ ▼, ▲ ▼, ▲
▼, ▲ ▼, WE, D / A converter 12 to 14 control pulse,
Counting pulses for address counters 8a and 8b, and various TVs
The synchronizing signal or the like can be generated by commonly using the clock signal from the single master oscillator 2.

Application Example The above-mentioned embodiment is applied to a reproducing apparatus of a disk recorded by the digital video signal recording method previously proposed by the present applicant, but the present invention is not limited to this, and a digital video signal of a composite encoding method is applied. Can be applied to a reproducing apparatus of a digital audio disk in which is recorded in addition to a digital audio signal, and further to an apparatus for reading pixel data from an image file in a predetermined format.

Effects As described above, according to the present invention, the output clock frequency of the oscillator 2 in the signal generating device 6 and the pixel data are stored in the memory circuit.
11 has a cycle of dividing into a period of an integer multiple of the number of addresses required to write to 11, and selects a frequency that is an integer multiple of 2 or more of the horizontal scanning frequency of the composite video signal. Various control signals (RAS, CAS, WE, RAW, CAW, RAR, CAR) to control circuits (8a, 8b, 9a, 9b, 10a, 10b, 7), output clock signals to two address generating means, and A single oscillator 2 sends various synchronization signals to an encoder (not shown).
By using the output clock signal of 1., the write address and read address of different values are obtained, and writing and reading of data are controlled, so that the circuit configuration of the signal generator of the digital video signal reproducing device is simplified. In addition to the above, it is possible to eliminate the adverse effect of the video signal due to the malfunction of the memory and to prevent the beat between the output clock signals.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the device of the present invention,
FIG. 2 is a diagram schematically showing the structure of one frame of a digital signal reproduced by a reproducing device in which the device of the present invention is used, FIG. 3 is a diagram explaining a video period and the like within one horizontal synchronizing period, and FIG. FIGS. 5A to 5F are time charts for explaining the operation of FIG. 1, and FIG. 5 is a diagram showing an example of an output signal waveform of the main part of the apparatus shown in FIG. 1 ...... digital video signal input terminal, 2 ...... master oscillator, 3 ...... divider, 4 ...... decoder, 5 ₁ through 5n ...... TV
Sync signal output terminal, 6 ... Signal generator, 7 ... Switch circuit, 8a ... Write address counter, 8b ... Read address counter, 11 ... Memory circuit, 12-14
...... D / A converter, 15 …… Luminance signal output terminal, 16,17 …… Color difference signal output terminal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H04N 5/93 (72) Inventor Hideo Sato 3-12 Moriya-cho, Kanagawa-ku, Yokohama, Japan Victor Co., Ltd. (72) Inventor Hiroyuki Sugiyama 3-12 Moriya-cho, Kanagawa-ku, Yokohama, Japan Victor Co., Ltd. (72) Inventor Koji Tanaka 3--12 Moriya-cho, Kanagawa-ku, Yokohama Local Victor Company of Japan (56) References JP-A-53-85112 (JP, A) JP-A-53-129521 (JP, A)

Claims (1)

[Claims] 1. Pixel data obtained from a recording medium on which a digital video signal is recorded is inputted through a buffer memory, the inputted pixel data is accumulated at a specified address, and the accumulated pixel data is accumulated. Among them, a memory circuit that reads out pixel data stored at a specified address in a predetermined format, and an address to which the pixel data is written is generated by counting an input clock signal, and this address is generated as a write address. A write address generating means for outputting to the memory circuit based on the timing signal, and an address of the storage destination of the pixel data read from the memory circuit by counting the input clock signal, and the read address generating timing signal Read out to the memory circuit based on Dress generating means, a digital / analog converter for digital / analog converting the pixel data read from the memory circuit based on a control signal, and various synchronizations related to the video signal to the output signal of the digital / analog converter. An encoder that outputs a composite video signal of a standard television system by adding a signal, and has a cycle of dividing the pixel data into a period of a number that is approximately an integer multiple of the number of addresses required to write to the memory circuit,
And a single oscillator for generating and outputting a reference clock signal selected at a frequency that is an integer multiple of 2 or more of the horizontal scanning frequency of the composite video signal, and a write control signal that enables writing of data in the memory circuit. A read control signal for enabling reading of data stored in the memory circuit, a write address generation timing signal and the clock signal to the write address generation means, and a read address generation timing to the read address generation circuit. A decoder for generating a signal and the clock signal, a control signal to the digital / analog conversion circuit, and various synchronization signals to the encoder based on a reference clock signal of the single oscillator, During the horizontal blanking period of the composite video signal, the clock signal and the writing A dress generation timing signal is supplied to the write address generation means to output a write address to the memory circuit, and a write control signal is output to the memory circuit to write the pixel data to an address designated by the write address. During the video period of the composite video signal, the clock signal and the read address generation timing signal are supplied to the address generating means to output a read address to the memory circuit, and further a read control signal is output to the memory circuit. Then, the digital video signal reproducing apparatus is characterized in that the pixel data stored at the address designated by the read address generating means is read.