JP2982574B2 - Digital video recording method and digital video recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video recording method and apparatus for recording, reproducing, or transmitting a digitized component video signal, for example , an apparatus such as a digital VTR.

[0002]

2. Description of the Related Art Conventionally, digitization of a component video signal has been performed according to the recommendation of CCIR601 (reference: CCIR Rec. 601 "Encoding parameters of").
digital television for studios ").

According to this recommendation, the sampling frequency is 13.5 MHz for the luminance signal and 6.75 M for the color difference signal.
Hz, both luminance signal and color difference signal are 10 per sample.
Quantized with bits. The number of effective samples in one horizontal scanning period is 720 for the luminance signal Y and 360 for the two color difference signals Cb and Cr. With an aspect ratio of 4: 3, the scanning method is 525 lines / 60 Hz (hereinafter, 525 lines / 60 Hz).
/ 60 Hz) and 625 lines / 50 Hz (hereinafter abbreviated as 625/50 system) are digitized. FIG. 2 shows the structure of sample points in this recommendation. As shown in the figure,
A point where the luminance signal component Y and the color difference signal components Cb and Cr of each line are sampled and a point where only the luminance signal component Y is sampled appear alternately in the horizontal direction.

Therefore, the luminance signal component Y is divided into the color difference signals Cb,
A component involving Cr and a component not involving a color difference signal are divided, and the former is referred to as a Yc component and the latter as a Yi component. In the following, Yc, Cb, and Cr at sample points at the same position will be described.
A sample of a component or a sample of a single Yi component is collectively referred to as a pixel, and a sample of each component at the same sample point belongs to a pixel at the same position.
That is, the sample of the Yc, Cb, and Cr components belongs to the pixel 201 in FIG. 2, and the Yi component belongs to the pixel 202.

There is a standard called D-1 as a conventional video tape recorder for recording and reproducing component digital signals sampled in accordance with the above-mentioned CCIR601 recommendation. Where D
In the case of -1, the data actually recorded / reproduced on the tape is the MSB of the sample quantized by 10 bits.
And only the upper 8 bits including.

For details of D-1, see, for example, the first reference, SMPTE 227M 19-mm type D-1 cassette-hel
ical data and control records (SMPTE Journal, Marc
h 1992), and as a second document, “D-1 Digital VTR Format” (Broadcasting Technology, Vol. 43, No. 12, N
ovember 1990).

FIG. 17 shows a tape pattern in the D-1 digital VTR. In D-1, 525/60
In the case of the system, the television screen of one field is divided into five segments, and in the case of the 625/50 system, the television screen of one field is divided into six segments, and complete signal processing is performed for each data of 50 horizontal scanning periods. . One segment of data is distributed to four recording channels in quarters. Video data for one segment is combined into one video sector for each distributed channel, and four sectors for one field form video sectors 2, 3, 4, and 5 in FIG. These four video sectors 2, 3, 4, and 5 are arranged on four different tracks as shown in FIG. 17, and are respectively recorded / reproduced by four different heads. That is, the video data distributed to the four recording channels each constitute one video sector, and are recorded / reproduced by different heads.

At this time, distribution to the four recording channels is performed for each sample of each of the Y, Cb, and Cr components. This is shown in FIG. FIG. 3 shows a part of a television screen, and shows channel numbers of recording channels in which samples of Y, Cb, and Cr components are recorded at each sample point for three lines.

As shown in FIG. 1, with respect to any component of Y, Cb, and Cr, eight samples (upper, lower, left, right, and diagonal) around one sample (the left and right portions of Y include one pixel). The interval, Cb, and Cr are viewed at two pixel intervals), and are always recorded on a recording channel different from the central sample. This takes into account the modification when a head clock occurs, and aims at obtaining a reproduced image having no visual problem.

[0010] Here, the head clog means that one recording head or reproducing head temporarily or permanently fails during recording or reproduction, and data recorded by the recording head or reproducing head is lost. This means that all playback data results in an error. Therefore, when the head clog occurs, the error correction code cannot be corrected due to too many error samples, and only error detection is performed in decoding the error correction code. At this time, the digital VTR generally performs a process called “modification” described below to prevent the image quality from deteriorating.

The modification is a process of replacing an error sample detected by an error correction code with a selective interpolation filter from peripheral pixels having no error in the upper, lower, left, and right directions to make the sample visually inconspicuous. Therefore, in order for the retouching to work effectively, it is necessary that samples around the error sample be as error-free as possible.

In the channel division of D-1, considering the above points, as shown in FIG. 18, an error sample due to the head clog is always an error sample as viewed from the Y, Cb, and Cr components. Is recorded on a different recording channel.

[0013]

Generally, digital VT
Errors in R do not occur uniformly for all byte data recorded. For example, when the above-mentioned head clog occurs, it is considered that all byte data recorded or reproduced by the head will have an error. Further, if a scratch is made on the magnetic tape as a recording medium in the longitudinal direction of the tape, all data recorded at the same position from the end of the tape on all tracks become errors. Also, small scratches on the tape result in burst errors in the reproduced data. As described above, various errors occur depending on the cause of the error. Generally, it can be said that the error is likely to occur simultaneously with byte data adjacent on the magnetic tape.

On the other hand, considering on a television screen, in the case of the component system, one pixel has Y
Three samples of the c, Cb, and Cr components or one sample of the Yi component belong. If any one of the samples belonging to the same pixel has an error, the pixel is recognized as an error pixel. Therefore, when it is assumed that the same number of data errors occur in the entire screen, it can be said that the number of erroneous pixels in the entire screen is smaller when the data belonging to the same pixel has an error at the same time.

As described above, Y belonging to the pixel at the same position
When the data of c, Cb, and Cr are close to each other on a tape, errors that are generally likely to occur in a digital VTR are likely to occur simultaneously in data belonging to pixels at the same position on a screen. Can be reduced.

However, in the case of D-1 described above, samples of the Cb component and Cr component belonging to the pixel at the same position are always recorded by the same head, but samples of the Y component are not necessarily recorded by the same head . As you can see,
Y recorded by the same head as the sample of the Cb and Cr components
Component samples are separated by up to two pixels. Yc, C
Since one pixel is formed only when the three components of b and Cr are aligned, two pixels which are close to each other are different from each other.
If a sample of one pixel is in error at the same time, two error pixels are generated as a result, and there is a problem that the number of error pixels in the entire screen increases.

The present invention solves the above-mentioned conventional problems, and reduces the number of error pixels in the entire screen.
It is another object of the present invention to provide a digital video recording method capable of improving the quality of a reproduced image after error correction by dispersing error pixels over the entire screen, and an apparatus for implementing the method .

[0018]

SUMMARY OF THE INVENTION A digital video recording method according to the present invention provides an even-numbered image on each scanning line constituting one screen.
A pixel of the first type has a luminance signal component (Yc) of the first type and
And two color difference signal components (Cb, Cr).
The odd-numbered pixels have a luminance signal component of the second type (Y
a digital video signal as constituted by i)
To four signal components (Yc, Cb, C
r, Yi) is equally recorded for each component.
4 recording channels and samples that make up one screen
Record data equally for each recording channel and each component
Divide into three or four segments, and for each channel
Even-numbered and odd-numbered segments are different
A scanner configured to be scanned by the printhead
To record digital video signals on tape
Pixel on each scanning line that constitutes one screen.
Divide into 6 or 8 pixel groups that follow
And for each pixel group constituting one screen,
Each pixel that constitutes a pixel group should be recorded
To the same standard segment number
Determined by turn, on the first line that composes one screen
For each pixel that makes up the first pixel group in
The channel in which each pixel is to be recorded is determined in advance.
Determined by the standard channel number pattern
Two horizontally adjacent pixel groups on the scanning line
The pixels that make up the right pixel group are recorded
The channel number pattern indicating the power channel should be on the left
Each pixel that constitutes the pixel group of
For each channel number pattern that represents a channel,
Channel number shifted by 1 or 3
Channel number pattern
Is determined and two vertically adjacent pixel groups on the same screen
Each pixel in the lower pixel group in the loop
Channel number pattern indicating the channel on which
Each pixel in the upper pixel group is recorded.
Channel number pattern that represents the channel to be
Channel number shifted by 1 or 3
Channel number pattern composed of channel numbers
And a first luminance signal constituting each pixel
Value data of the component and two color difference signal components and
Each pixel belongs to sample value data 2 of the luminance signal component
Channel number patterns and cell groups corresponding to pixel groups
Segment of the recording channel indicated by the segment number pattern.
The even-numbered pixel by recording the
First type luminance signal component (Yc) and two color difference signals
Sample value data of components (Cb, Cr)
Record with the same head and belong to adjacent pixels on the screen.
Sample data recorded by different recording heads,
Samples of two adjacent color difference signal components on the screen
Data is stored in different records for each component.
Digital video recording characterized by recording in a video
Is the way.

[0019]

[0020]

In the digital video recording apparatus according to the present invention, an even-numbered pixel on each scanning line constituting one screen is the
One type of luminance signal component (Yc) and two color difference signals
No. components (Cb, Cr)
Element is composed of a second type of luminance signal component (Yi)
Digital video signals that make up one screen
Of four signal components (Yc, Cb, Cr, Yi)
Recording channels to record the data equally for each component
Channel and sample data for one screen
3 or 4 to record evenly for each component for each channel
Segments (SEG 0, SEG 1, SEG 2,
Digit to be recorded on tape divided into SEG 3)
Video recording device, four recording channels
And sample data for one screen in three or four
And a signal circuit for recording the four signal components (Y
c, Cb, Cr, Yi) for one scan line period
Memory and four values for each of the four signal components
Component addresses and four recording channels
A channel address corresponding to four values,
Or 3 or 4 for each of the 4 recording segments
And the same recording channel as the segment address corresponding to the
Channel, recorded in the same recording segment, same
Represents the serial number within one scan line of the signal component sample of
It consists of a sample address,
A set of pixels every 6 or 8 pixels is called a pixel group.
Segment address is assigned to all pixel groups.
The same predefined standard segment number
Pattern, channel address constitutes one screen
For the first pixel group of the first line,
Set a fixed standard channel number pattern.
Standard channels for each horizontal and vertical pixel group
Channels shifted by 1 or 3 in channel number pattern
Channel number pattern consisting of numbers
Write address generation that generates such a write address
Raw circuit, also component address and channel
Address, segment address, and sample address
Channel address and segment address.
Is the recording channel number and input at the input to the recording circuit.
Issue a read address that matches the segment number.
And a read address generating circuit for generating the read address.
Samples of 4 Tsunoshin No. components of a digital video signal,
For each scanning line period, the write address of the line memory
The write circuit generates a write address and stores the
Generates a read address for the sample stored in the memory
By reading from the read address generated by the circuit,
And a first type of luminance signal forming an even-numbered pixel.
Component (Yc) and two color difference signal components (Cb, Cr).
Sample data from the same recording channel on the tape.
Segment with the same recording head, and
Sample data belonging to adjacent pixels are recorded differently
Recording with the head, and two color difference signals adjacent on the screen
The sample data of the component
A digital video recording apparatus characterized in that recording is performed using different recording heads .

[0022]

According to the present invention distributes the digital component video signal into four recording channels, and distributes into three or four segments for each recording channel, by using the two recording heads for each channel In a digital video recording method for recording, sample data of a luminance signal component and sample data of two color difference signal components sampled at the same position on a television screen are treated as a set of pixel data for each sample point,
Set the recording channel and segment where pixel data is recorded
Assigned periodically every 6 or 8 pixels . Then horizontal
Group of 6 or 8 pixels adjacent in the vertical and vertical directions
Shift the channel number by 1 or 3 for each loop
Record. Thus, the recording channel and the segment to which the pixel data of the sample point at the same position are distributed are determined. Data of the same segment on the same recording channel
Since the recording is performed by one recording head determined by the arrangement of the recording heads on the scanner and the arrangement of the scanning trajectory of each recording head on the recording medium, sampling is performed at the same position on the television screen constituting one pixel data. The sample data of the luminance signal component and the sample data of the two chrominance signal components are distributed to the same segment of the same recording channel, and therefore must be recorded by the same recording head.
For respectively, at the same time the luminance signal component and two color difference signal components is, sample data of two sample points adjacent on a television screen, so configuring different pixel data even try taking any component, different recording heads Can be recorded.

Thus, even when head clogging occurs, the number of error pixels on the television screen is reduced, and errors are corrected by sample data belonging to pixels recorded by different recording heads adjacent to the error pixels. Can be.

Further, with respect to a set of pixel data assigned to the same segment of the same recording channel, the order of the pixel data is replaced by a permutation in this set.
Since the recording channel and the segment to which the pixel data is distributed do not change before and after the replacement, the sample data of the luminance signal component and the sample of the two chrominance signal components sampled at the same position on the television screen constituting one pixel data. The data is always recorded by the same recording head, and at the same time, for each of the luminance signal component and the two color difference signal components, the sample data of two adjacent sample points on the television screen are recorded by different recording heads. can do.

At this time, on the television screen distributed to the same segment of the same recording channel, a luminance signal component and 2
The sample data of the sample points that are close to each other for each of the three color difference signal components are arranged in the order in which they are close to each other before performing the above-described permutation, but by changing this order, the same data is recorded on the recording medium. It is possible to record in the same segment of the recording channel at locations remote from each other.

As a result, even if errors occur consecutively on the same track, the sample data of the pixels adjacent to the error pixel does not become an error, so that the error pixel can be corrected.

[0027]

[0028]

[0029] In digital video recording apparatus according to the present invention distributes the digital component video signal into four recording channels, further 3 for each recording channel
Divided into four or four segments for each channel
In a digital video recording apparatus for recording on a recording medium using two recording heads, sample data of a luminance signal component and sample data of two color difference signal components sampled at the same position on a television screen are combined.
3 samples of data or color difference signal components
When sample data have the luminance signal component and pixel data of lumped for each sample point, one line of the image
Write address of line memory that stores raw data
Write according to the above recording method generated by the generating circuit
Each pixel data is stored in the address. This allows
For each segment of each recording channel on in-memory
Each pixel data is arranged in the divided area. This pixel
Data is read by the read address generation circuit.
Each address of the 4-channel recording circuit according to the address
Recording channel, each segment, and each record
Reading is performed so that the recording channel matches the segment.

Thus, the sample data of the luminance signal component and the sample data of the two color difference signal components belonging to the pixel at the same position on the television screen are recorded by the same recording head, and at the same time, adjacent pixel data on the television screen are mutually It is recorded by different recording heads.

Thus, even when head clogging occurs, the number of error pixels on the television screen can be reduced, and errors can be corrected by sample data belonging to pixels recorded by different recording heads adjacent to the error pixels. Can be.

[0032]

EXAMPLE In an example of the present invention, the following 18 will be described.
Consider a video tape recorder that records and reproduces digital video signals sampled by MHz sampling.

In the 18 MHz sampling, the sampling frequency is 18 MHz for the luminance signal and 9 MH for the color difference signal.
At z, both the luminance signal and the color difference signal are quantized at 8 bits per sample. The number of valid samples in one line is
The luminance signal Y has 960 samples and the two color difference signals Cb and C
r is 480 samples. This method uses an aspect ratio of 1
In order to obtain the same horizontal resolution as that of the conventional CCIR601 recommendation in the wide television system of 6: 9 and the scanning system of 525 lines / 60 Hz and 625 lines / 50 Hz,
The sampling frequency is set to four-thirds of 13.5 MHz and the band in the horizontal direction is widened.

The structure of the sample points in this 18 MHz sampling can be represented in FIG. 2 similarly to the recommendation of CCIR601. That is, a point where the luminance signal component Y and the color difference signal components Cb and Cr of each line are sampled and a point where only the luminance signal component Y is sampled alternately appear. Thus, similarly to the conventional example, the color difference signal components Cb,
A luminance signal component accompanied by Cr is represented by Yc, and a luminance signal component not accompanied by a color difference signal component is represented by Yi.
A sample of the Cb and Cr components or a sample of a single Yi component is referred to as a sample belonging to the pixel at the same position.

Digital VTR in Embodiment of the Present Invention
3 is shown in FIG. In the figure, reference numeral 1 denotes a rotary cylinder, and as shown in FIG.
a, r1a, r2a, and r3a are mounted on the rotary cylinder 1, and another four recording heads r0b, r1b, r2b, and r3b are mounted at 180-degree intervals. Similarly, two sets of four reproduction heads p0 each
a, p1a, p2a, p3a and p0b, p1b, p2
b, p3b are recording heads r0a, r1a, r2a, r3
a, r0b, r1b, r2b, and r3b are attached at 90 degrees. Here, the number of signals to be simultaneously recorded is called the number of recording channels, and in the embodiment of the present invention, four channels are used. In the above recording head, r0a and r0b are recording heads of recording channel 0, and r1a and r0r
1b is the recording head of recording channel 1, r2a and r2
b is the recording head of recording channel 2, r3a and r3b
Represents a recording head of the recording channel 3. Also,
The reproducing heads p0a and p0b are reproducing heads for recording channel 0, p1a and p1b are reproducing heads for recording channel 1, p2a and p2b are reproducing heads for recording channel 2, and p3a and p3b are reproducing heads for recording channel 3. Represents.

The winding angle of the tape is 180 degrees. That is, when the four recording heads r0a, r1a, r2a, and r3a on the a side operate in the first half rotation of the cylinder 1, b
Four recording heads r0b, r1b, r2b, r3b
Does not work, and in the next half rotation, the four recording heads r0 on the b side
Each time the cylinder 1 makes a half turn, the a side and the b side are switched such that b, r1b, r2b, and r3b operate and the four recording heads r0a, r1a, r2a, and r3a on the a side do not operate. In this way, each recording head forms one recording track each time the cylinder 1 rotates half a turn.
The same applies to the reproducing head.

FIG. 4 shows a tape pattern according to the embodiment of the present invention. In the 525/60 system, one field of effective data is recorded by three scans. During this time, the cylinder 1 rotates 1.5 times, and three tracks are formed for each recording channel. In the 625/50 system, valid data of one field is recorded by four scans. During this time, the cylinder 1 makes two rotations, and four tracks are formed for each recording channel.

Here, four tracks corresponding to one-half rotation of a cylinder in one field are collectively called a segment, and are sequentially referred to as 0, 1, 2 (525/60 system) or 0, 1, 2. , 3 (625/50 system). That is, in the 625/50 system, T1, T
2, T3, T4 are segment 0, T5, T6, T7, T
8 is called segment 1, and T9, T10, T11, and T12 are called segment 2, and data of one field is T1 to T1.
It is recorded on 12 tracks of 2 3 segments. Also, 5
In the 25/60 system, T1, T2, T3, and T4 are similarly set to segment 0, T5, T6, T7, and T8 are set to segment 1, T9, T10, T11, and T12 are set to segment 2 and T2.
13, T14, T15 and T16 are called segment 3,
Data of one field is 4 segments 1 of T1 to T16
It is recorded on six tracks.

As described above, in the case of the 525/60 system, when the tracks recorded by the recording heads r0a, r1a, r2a, and r3a on the a side are T1, T2, T3, and T4 (segment 0), respectively, the cylinder 1 Are rotated half a turn, T5, T6, T7, and T8 (segment 1) are the recording heads r0b, r1b, r2b, and r3b on the b side, respectively.
Then, the cylinder 1 further makes a half turn, and T9, T10, T
11, T12 (segment 2) are recorded by the recording heads r0a, r1a, r2a, r3a on the a side, respectively. In the case of the 625/50 system, the recording head r0 on the a side
Tracks recorded by a, r1a, r2a, and r3a are:
When they are T1, T2, T3, and T4 (segment 0), respectively, T5, T6, T7, and T8 (segment 1) are recording heads r0b, r1b, r2b, and r3 on the b side, respectively.
b, T9, T10, T11, T12 (segment 2)
Are the recording heads r0a, r1a, r2a,
At r3a, T13, T14, T15, and T16 (segment 3) are the recording heads r0b, r1b, and r on the b side, respectively.
2b, r3b.

In the embodiment of the present invention, error correction using a so-called product code is performed. The first error correction code is called an outer code, and each of the Yc, Yi, Cb, and Cr components constitutes one outer code for each line of each recording channel. Therefore, the number of outer codes per line of one recording channel is 4, and the number of data bytes per outer code is 120. This 12
An 8-byte check byte is added to the 0-byte data by Reed-Solomon code.

Next, to form a product code, the outer-coded data is arranged in a two-dimensional array. The array is configured using one field memory for each recording channel. FIG. 9 shows a memory map of the field memory for the 525/60 system, and FIG. 10 shows a memory map of the field memory for the 625/50 system. In both figures, one column of data in the vertical direction is called a column, and one row of data in the horizontal direction is called a row.

First, in the case of the 525/60 system, a total of 128 bytes of 120 bytes of the outer encoded video data and 8 bytes of the outer check data are written in FIG. The data is arranged as one column of data in the vertical direction so that the portion written as 8 bytes becomes the outer check data. Similarly, in the case of the 625/50 system, 120 bytes of outer encoded data and 8 bytes of outer encoded data are used.
The check data is arranged in one column in FIG.

In the embodiment of the present invention, the number of valid lines to be recorded is set to 255 in the case of the 525/60 system per field.
, And 304 in the case of the 625/50 system. As described above, the number of outer codes per line of one recording channel is four, so the number of outer codes for one field per field is 255 * 4 = 525/60 system.
304 * 4 = 12 for 1020, 625/50 system
It becomes 16 pieces. That is, as shown in FIGS. 9 and 10, the matrix in the 505/60 system is 1020 bytes in the horizontal direction and 1216 bytes in the 625/50 system.

On the other hand, the encoding of the inner code, which is the second error correction code, is performed while reading data in the horizontal direction of the matrix, thereby forming a so-called product code. The inner code is 8 in the case of the 525/60 system.
8-byte check data is added to 5-byte video data. In the case of the 625/50 system, 76
8-byte check data is added to byte video data.

After synchronizing data is added to each inner code, appropriate digital modulation is performed and recorded on a tape. A block of data obtained by combining the synchronous data and the inner code is called a sync block.

As described above, the error correction matrix is composed of one field of data for each channel. On the other hand, as described above, one field data is divided into three segments in the case of the 525/60 system, and divided into four segments in the case of the 625/50 system. At this time, 120 rows of video data and 8 rows of outer parity are divided into three or four parts, respectively, and each is recorded in one segment. That is, in the case of the 525/60 system, as shown in FIG. 9, reading is started in the horizontal direction from point D, and up to point d, when 1/3 of the outer check data is read, then A
Moving to the point, the data is read out in the horizontal direction and 1/3 of the video data is read up to the point a to form one segment. In the next one segment, after reading from the point E to the point e, the process moves to the point B and reads out to the point b. When the next one segment is read from the point F to the point f, the process proceeds to the point C and is read to the point c. In the case of the 625/50 system, as shown in FIG. 10, reading is started in the horizontal direction from point E, and after reading 1/4 of the outer check data up to point e, the process proceeds to point A. The data is read out in the horizontal direction and 1/4 of the video data is read up to the point a to form one segment. In the next one segment, after reading from point F to point f, the process moves to point B and reads out to point b. When the next one segment is read from the point G to the point g, the process proceeds to the point C and is read to the point c. If the next one track is read from point H to point h, D
Move to point and read up to point d.

FIG. 1 is a block diagram showing the overall configuration of a digital video recording apparatus according to one embodiment of the present invention.

In the figure, reference numeral 110 denotes an input terminal to which a component digital signal is input; 101, a luminance signal and a color difference signal 113 are separated from a component digital signal 111 in which a luminance component and a color difference component are time-division multiplexed; A digital interface circuit for outputting 114; a channel / segment distribution circuit 102 for allocating channels and segments in which each pixel is recorded in a manner described later, and outputting data 115 for channels 0 and 1 and data 116 for channels 2 and 3; 1
03 is an outer encoding circuit that performs outer correction encoding on the 0 and 1 channel data, and 104 is an outer encoded 0 and 1 channel data 117 that is 0 channel data 118 and 1 channel data 1
19 is a demultiplexer, 105 is a field memory constituting an error correction matrix, 106 is a field memory control circuit that controls writing and reading of the field memory, 107 is a recording signal processing circuit that performs inner coding and digital modulation, etc. And 108 are recording heads for recording data on the tape.

The component digital signal 111 input from the input terminal 110 is SMPTE standard 125M
(SMPTE Journal, September 1991) as shown in luminance signal sample Y and two color difference signal samples C
b and Cr are signals which are time-division multiplexed alternately in the order of Cb, Y, Cr and Y, and at the same time, the horizontal and vertical synchronization timings are encoded and multiplexed in the data.

In this embodiment, as described above, the sampling frequency of the luminance signal component is 18 MHz and the sampling frequency of the color difference signal component is 9 MHz, so that the clock rate of the multiplexed signal 111 is 36 MHz.
It is. The digital interface circuit 101 detects the multiplexed synchronization data from the component digital signal 111, and outputs the horizontal and vertical synchronization signals 11
4 is restored. At the same time, the luminance signal component Y and the two chrominance signal components Cb and Cr are separated to each other at 18 MHz.
The luminance signal component 112 and the color difference signal component 113 are output at the clock rate of.

The synchronization control circuit 109 generates a necessary synchronization signal in each section of the recording apparatus of this embodiment from the horizontal and vertical synchronization signals 114 and sends it to each section.

Channel / segment distribution circuit 102
For each sample of the luminance signal 112 and the chrominance signal 113 according to the method of the present invention described later, the channel and the segment where the pixel is recorded are determined for each pixel, and the data 115 of the 0 and 1 channels are determined according to the determined channel. The data is output in two systems of data 116 of 2 and 3 channels. Here, the data is divided into two systems in order to unify the signal processing clock at 18 MHz and to suppress the circuit scale. Thereafter, the same processing is performed in the two channels of channels 0 and 1 and channels 2 and 3, but FIG. 1 shows only the channels of channels 0 and 1 for simplicity.

The outer encoding circuit 103 adds 8 check bytes to 120 bytes of data for the data of channel 0 and channel 1 as described above, and forms four outer codes per line for each channel. . The formed outer code is alternately demultiplexed into 0 channel and 1 channel.
Sent to

The demultiplexer 104 divides the outer-coded data 117 into 0-channel data 118 and 1-channel data 119, and outputs the data in two systems. Thereafter, the same processing is performed for each channel, but FIG. 1 shows only the 0 channel, and the other 3 channels are omitted.

The field memory 105 forms the error correction matrix shown in FIGS. In accordance with a write address and a write control signal 120 generated by the field memory control circuit 106, the outer encoded data 118 is written in the column direction of the matrix formed by the field memory 105. When the outer code for one field is written, the field memory 105 is read according to the read address and the read control signal 121 generated by the field memory control circuit 106.
Are read out in the order of the row direction of the matrix formed by.

The read data 122 is sent to the recording signal processing circuit 107, and is subjected to inner coding, addition of a synchronization signal,
The data is converted into a recording bit string 123 by processing such as digital recording modulation and parallel / serial conversion, and is sent to the recording head 108 on the rotating cylinder, where the data is recorded on the tape. At this time, the recording head 108 has a configuration as shown in FIG.

In the above-described recording apparatus, the above-mentioned 8
An embodiment of the present invention will be described which is a method of distributing each sample to each recording channel and each segment described above so that effective repair can be performed even if one of the recording or reproducing heads fails. This processing is performed in the channel / segment distribution circuit 102 in FIG.

First, when the number of recording channels is represented by NCh,
As described above, NCh = 4 channels. When the number of segments per field is represented by NSeg,
As described above, NSeg = 3 segments in the case of the 525/60 system, and NSeg = 4 segments in the case of the 625/50 system.

The number of effective lines in one field is NLin
As described above, NLinFld = 255 lines in the case of the 525/60 system and NLinFld = 304 lines in the case of the 625/50 system. Assuming that the number of effective pixels per line is NSplLin, NSplLin = 960 pixels as described above. For the input component digital video signal, 1
Assuming that the effective line number in the field is lin and the effective pixel number in one line is pix, lin is 0 to NLi
an integer up to nFld-1, pix ranging from 0 to NSplLi
Expressed as an integer up to n-1.

As described with reference to FIG. 2, samples of Yc, Cb, and Cr components belong to pixels with even-numbered pixels, and samples of Yi components belong to pixels with odd-numbered pixels. Therefore, the number of effective samples of each of the Yc, Cb, Cr, and Yi components is 480 samples per line. If the number of bytes of sample data per segment of one recording channel per component is expressed as NSplSeg, NSplSeg = 480/4/3 = 40 bytes in the case of the 525/60 system, and 40 bytes in the case of the 625/50 system. NSplSeg = 480 /
4/4 = 30 bytes.

First, samples of the Yc, Cb, Cr, and Yi components of each pixel are distributed to four outer codes, four recording channels, three in the case of the 525/60 system, and four segments in the case of the 625/50 system. . At this time, each Y
Samples of c, Cb, Cr, Yi components are three or four
Make sure each segment is evenly distributed. This is to prevent the error data from being biased to a specific component even if all of the specific segments are erroneous due to a head clog or the like. If the minimum segment distribution cycle for that is expressed as PSegDist, then PSegDist = 6 pixels in the case of the 525/60 system, and PSegDist = 8 pixels in the case of the 625/50 system. Therefore, one line of pixels is assigned this cycle PSegD.
Divide by ist. That is, grp = int (pix / PSegDist) (1) ph = pix mod PSegDist (2) Here, the above number of cycles per line is NG
If rpLin, NGrpLin = NSplLin
/ PSegDist and N for 525/60 system
GrpLin = 160 cycles, N for 625/50 system
GrpLin = 120 cycles. At this time, grp is an integer from 0 to NGrpLin-1 and ph is 0 to P
It is an integer up to SegDist-1. Also, “x m
"od y" represents the remainder of x divided by y, and "int
(X) "represents the largest integer not exceeding x (the same applies hereinafter).

Here, the arrangement of the segments is determined as follows for each cycle described above. That is, when each sample of the Yc, Cb, Cr component or Yi component belonging to the pixel with the pixel number pix is arranged in the segment with the segment number seg, seg = segInit [ph] (3). However, segInit [ph] is an arrangement of segments for one cycle, and the segments are evenly distributed to each component as described above. For example, in the case of the 525/60 system, segInit [0] = 0 segInit [1] = 1 segInit [2] = 2 segInit [3] = 0 segInit [4] = 1 segInit [5] = 2 (4) In the case of the 625/50 system, segInit [0] = 0 segInit [1] = 0 segInit [2] = 1 segInit [3] = 1 segInit [4] = 2 segInit [5] = 2 segInit [6] = 3 segInit [7] = 3 (5) Since all the segments are distributed once to both the even-numbered pixels and the odd-numbered pixels, Yc, Cb, Cr belonging to the even-numbered pixels All segments are distributed once for both the component samples and the Yi component samples belonging to odd-numbered pixels. It is. Thus, the number of samples NSplSeg for each component per one segment of one recording channel is equal to NGrpLin / NCh for the four components, which is NSplSeg in the case of the 525/60 system as described above.
= 40 samples, NSplSe for 625/50 system
g = 30 samples.

Next, the distribution of the recording channels is determined for one cycle of the segment distribution. This is because the arrangement of recording channels for one cycle is set to chInit [ph] in the same manner as the segment distribution, and each Y channel belonging to each pixel is
The c, Cb, Cr component or Yi component is assigned to the recording channel. At this time, if the channel number is shifted by one or three every cycle, the number of channels Nch
Since = 4, the recording channels can be evenly distributed to each component. Further, by shifting the channel number for each line, the recording channel for recording the pixel at the same position on the adjacent line is changed. That is, when a sample of each component belonging to the pixel of the pixel number pix is to be arranged on the recording channel of the channel number ch, ch = (chInit [ph] + grpOfstCh * grp + linOfstCh * lin) mod NCh (6) Here, grpOfstCh represents the shift amount of the channel number for each cycle and takes a value of 1 or 3, and
linOfstCh represents the shift amount of the channel number for each line, and takes an appropriate integer from 0 to NCh-1.

For example, segInit [ph] takes the value shown in equation (4) or (5), and grpOfst
When Ch = 1, appropriate chInit [ph] and lin
Examples of the value of OfstCh are shown in (Table 1) and (Table 2). (Table 1) shows the case of the 625/50 system, and (Table 2) shows the value of the 525/60 system.

[0065]

[Table 1]

[0066]

[Table 2]

All the samples in one line are distributed to the recording channels and segments determined as described above, and a number splSeg is sequentially assigned to each component for each sample distributed to the same segment of the same recording channel. That is, splSeg = grp / NCh (7).

For example, in the 525/60 system, segI
nit [ph] is the value of equation (4), grpOfstCh is 1, chInit [ph] is chInit [0] = 0 chInit [1] = 3 chInit [2] = 2 chInit [3] = 0 chInit [4] = When 3 chInit [5] = 3 (8), pix, grp, ph, ch, seg, s
FIG. 5 shows what each value of plSeg looks like. In the 625/50 system, segInit [ph] is the value of equation (5), grpOfstCh is 1, chInit
[Ph] is changed to chInit [0] = 0 chInit [1] = 2 chInit [2] = 1 chInit [3] = 3 chInit [4] = 0 chInit [5] = 2 chInit [6] = 1 chInit [7] = 3 (9), pix, grp, ph, ch, seg, s
FIG. 6 shows what each value of plSeg looks like.

FIGS. 5 and 6 show equations (1) and (4) for the pixel of pixel number pix for the first four lines of the field.
(2), (3), (6), and (7) are shown.
In both figures, the state of the head for recording / reproducing each pixel is shown in the row indicated by head. In this line,
0a indicates that recording is performed by the recording head r0a or reproduction is performed by the reproducing head p0a, and 0b indicates that recording is performed by the recording head r0b.
1a is recorded by the recording head r1a or reproduced by the reproducing head p1a, and 1b is recorded by the recording head r1b or reproduced by the reproducing head p0b. p1b, 2a is recorded by the recording head r2a or reproduced by the reproducing head p2a, 2b is recorded by the recording head r2b or reproduced by the reproducing head p2b, 3a indicates that the recording is performed by the recording head r3a or reproduced by the reproducing head p3a.
Is recorded by the recording head r3b or read head p
3b indicates that the content is reproduced.

From FIG. 5, when only the pixels having an even pix among the 24 pixels from 0 to 23 are viewed for each line,
It can be seen that a combination of four channel numbers and three segment numbers is arranged once each. Also, p
The same applies to the case where only ix has an odd number of pixels, and the combination of the channel number and the segment number is repeated with a cycle of 24 pixels. Also in FIG. 6, a combination of four channel numbers and four segment numbers is arranged once every 32 pixel periods. Therefore, pix
Also for the Yc, Cb, and Cr components belonging to even-numbered pixels, and for the Yi component belonging to pixels having an odd pix,
All combinations of channel numbers and segment numbers are equally assigned.

Further, when only the state of head distribution for the Y component is extracted from FIG. 5 (that is, the row of head is extracted), as shown in FIG. 7, the state of head distribution for the Cb component or Cr component is also extracted from FIG. That is, when pix takes out an even number value from the head row), the result is as shown in FIG. It can be seen from FIG. 7 that no matter which sample is taken, the sample adjacent vertically and horizontally and diagonally is recorded and reproduced by a different head from the sample at the center. Also,
FIG. 8 is the same. The same applies to the head distribution in FIG.

As described above, each component Yc, Cb, Cr, Y
The head on which each pixel is recorded is determined so that each recording channel and segment is equally allocated to i. At this time, the samples of the components Yc, Cb, and Cr belonging to the pixel at the same position where the pixel number pix is even are the pixel numbers p
ix and the same head determined by the line number lin, and at the same time, the pixel data of the adjacent sample points on the television screen for the luminance signal component Y and the color difference signal components Cb and Cr are recorded and reproduced by different heads. Could be distributed. Therefore, even if a head clog occurs, the number of error pixels on the television screen is reduced, and correction can be performed by pixel data adjacent to the television screen.

Equations (4), (5), (Table 1),
The values shown in (Table 2) are examples, and there are other appropriate values.

For example, in the case of the 525/60 system, segInit [0] = 0 segInit [1] = 2 segInit [2] = 1 segInit [3] = 0 segInit [4] = 2 segInit [5] = 1 (10 ), GrpOfstCh is 1, chInit [p
h], linOfstCh can be set to the values shown in the following (Table 3) to obtain the same effect.

[0075]

[Table 3]

Next, a set of pixel data distributed to recording channels and segments as described above will be described.
A method of changing the order of pixel data in the same segment of the same recording channel will be described.

Here, a component number comp is defined to distinguish each of the Yc, Cb, Cr, and Yi components, and 0 is set for the Cb component, 1 for the Cr component, 2 for the Yc component, and 2 for the Yc component.
Set to 3 for the Yi component.

By the above-described distribution of each pixel to recording channels and segments, each component Yc, Cb, Cr, Yi
The video sample of line number lin (0 to NLi
nFld-1), recording channel number ch
(Integer from 0 to NCh-1), segment number se
g (integer from 0 to NSeg-1), sample number splSeg (0 to NSplSeg-1) in the segment
Up to an integer). That is, all data are (comp, lin, ch, se
g, splSeg).

In order to record data belonging to pixels adjacent to each other on a television screen as far as possible on a tape,
The process of changing the order of data is generally called shuffling. At this time, the same address (comp, lin, ch, se) is used so that the arrangement of the pixels to the recording channel and the segment determined so far is not broken.
The order of NSplSeg byte data having g) is exchanged therein. Hereinafter, this is referred to as intra-segment shuffling.

In the intra-segment shuffling, the addresses (comp, lin, ch, seg, splSe)
g) with respect to the addresses (comp, lin, ch, seg, splOCSe)
g). That is, if comp = 0, 1, 2 (data of components Yc, Cb, Cr), splOCSeg = (baseFactor * splSeg + chOfst [ch] + segOfst [seg] + linOfst * lin) mod NSSpSeg (11), co In the case of = 3 (in the case of the data of the component Yi), it is assumed that splOCSeg = (baseFactor * splSeg + chOfst [ch] + segOfst [seg] + linOfst * lin + compOfst) mod NSplSeg (12). Here, baseFactor is a constant that takes a relatively prime integer with respect to NSplSeg from 1 or 1 to NSplSeg-1, chOfst [ch] is an array of integer constants from 0 to NSplSeg-1 and is a value for each channel, segOfst [seg ] Is from 0 to NSpl
An array of integer constants up to Seg-1, values for each seg, linOfst is an integer constant from 0 to NSplSeg-1, and compOfst is 0 to NSplSeg-
It is an integer constant up to 1.

According to equations (11) and (12), s
A one-to-one mapping from plSeg to splOCSeg is defined. baseFactor determines how far two samples differing by 1 in splSeg after swapping. chOfst [ch] and segOfst
[Seg] determines how much each segment (see FIG. 4) of each recording channel arranged in the longitudinal direction on the tape is shifted from each other in the track direction. linOf
The st determines how far apart pixel data to be recorded on the same segment of the same recording channel on an adjacent line on the television screen is recorded. compOf
The st determines how far the data belonging to the pixel having the Yi component is recorded on the tape in the track direction with respect to the data belonging to the pixel having the Yc, Cb, and Cr components.

For example, as an example of a suitable value of the constants of the equations (11) and (12), the case of the 525/60 system is shown in (Table 4), and the case of the 625 · 50 system is shown in (Table 5). Shown in

[0083]

[Table 4]

[0084]

[Table 5]

By performing intra-segment shuffling as described above, all the data are (comp, lin, c
h, seg, splOCSeg). Y belonging to the pixel at the same position
By applying the equation (11), the data of the c, Cb, and Cr components have the same address splOCSeg even after shuffling within the segment, and are recorded in a close place on the magnetic tape as described later. . On the other hand, the sample of Yi having the same address splSeg as the above Yc is close to the pixel of the above Yc on the television screen, but due to the constant compOfst of the equation (12), sp
IOCseg becomes a value different from the value of Expression (11). As a result, as described later, the data is recorded at a sufficiently distant place on the magnetic tape.

As described above, the data of each of the Yc, Cb, Cr, and Yi components assigned to the same recording channel in one line is encoded into one outer code in the order of the segment number. That is, as described above (co
mp, lin, ch, seg, splOCSeg) of each video sample having an address represented by a set of values:
120 samples having (comp, lin, ch) having the same value are used as the above-described video data, and the above-described outer encoding is performed. At this time, as described above, each outer code is
And one column of FIG. 10, as described above, this one column is three in the case of the 525/60 system,
In the case of the 625/50 system, it is divided into four segments. This can be expressed as follows.

Row = NSplSeg * seg + splOCSeg (13) where row is the vertical address of the matrix as shown in FIGS. 9 and 10.

On the other hand, out of the four outer codes belonging to the same line, the outer code composed of the Cb component data is written in a column adjacent to the column in which the outer code composed of the Yc component data is written. The outer code consisting of Cr component data is written in a column next to the column, and the outer code consisting of Yi data is written in the column next to the column. Line up.

Therefore, four data having the same splOCseg value of the four outer codes belonging to the same line are arranged side by side in the horizontal direction of the field memory. That is, according to equations (11) and (12), three samples of the Yc, Cb, and Cr components belonging to the same pixel are arranged in the row direction of the field memory, and the samples of the Yi component belonging to the pixel adjacent to the pixel on the television screen. The sample is written at a position vertically separated from the adjacent column of the field memory. Similarly, samples of Yc, Cb, and Cr components belonging to pixels adjacent to each other on the television screen are written in the same column at positions separated in the vertical direction.

As described above, since the data read from the field memory in the horizontal direction is recorded on the tape, the data of the Yc, Cb, and Cr components belonging to the same pixel arranged in the horizontal direction are sequentially read from the field memory. It is read and recorded as continuous data. On the other hand, the Yi component of the pixel adjacent to the pixel on the television screen or Yc,
Since the data of the Cb and Cr components are read while being shifted in the column direction, they are recorded at distant positions on the tape. Therefore, as described above, Yc, Cb, Cc belonging to the same pixel
r data is recorded close to the tape,
Yi component or Y belonging to a pixel adjacent on the TV screen
The data of the c, Cb, and Cr components is recorded at a remote location on the tape.

Therefore, according to the above-described system of the embodiment of the present invention, even when an error occurs continuously on the same track, data adjacent to the error pixel is recorded separately on the same track. There is a high possibility that the error is not an error, so that effective retouching can be performed.

Next, the configuration of the channel / segment distribution circuit 102 for realizing the above-described method as a recording device will be described.

FIG. 11 shows the configuration of the channel / segment distribution circuit. In the figure, reference numerals 1301 and 1302 denote input terminals to which the chrominance signal 113 and the luminance signal 112 are inputted, respectively 1303 and 1304 a line memory for storing the chrominance signal sample and the luminance signal sample for one line period, 1306 a line memory 1304
A write address generating circuit for generating write addresses 1311 and 1312 to the memory, 1307 is a read address generating circuit for generating read addresses 1313 and 1314, and 1308 is a line memory 1303 and 1304
Switching circuit for switching between writing and reading of data, 13
05 is a color difference signal sample 1315 and luminance signal data 13
16 is switched in accordance with an exchange control signal 1317, and an exchange circuit for obtaining 0 and 1 channel data 115 and 2 and 3 channel data 116, 1309 is an output terminal of 0 and 1 channel data 115, and 1310 is 2
And output terminals for the data 116 of the three channels.

Line memory 1303 and line memory 13
04 has the same internal configuration. FIG. 12 shows the internal configuration of these line memories. In FIG. 12, 1401,
Reference numeral 1402 denotes a RAM (Ra) having a capacity for storing a luminance signal sample or a color difference signal sample for one line.
nd Access Memory). RA
M1401 and addresses 1413 and 14 of RAM 1402
14 are supplied from multiplexers 1403 and 1404, respectively. Multiplexers 1403, 1404
Is a write address 1 according to a switching signal 1417 supplied through a terminal 1412 and a switching signal 1420 obtained by inverting the switching signal 1417 by an inverting circuit 1408.
One of the read address 418 and the read address 1419 is supplied to the RAM 1401 and the RAM 1402, respectively. That is, when the switching signal 1417 is 0, the multiplexer 1403 sets the write address 1418 to the address 1418.
13, and the multiplexer 1404 outputs the read address 1419 to the address 1414. At this time, the switching signal 1417 enables the buffer 1405 to supply write data 1416 input from the terminal 1411 to the RAM 1401. On the other hand, since the buffer 1406 is disabled by the switching signal 1420 which is set to 1 at this time, R
No write data is supplied to the AM 1402. Therefore, by using the switching signal 1417 as a write enable signal in the RAM 1401, the write data supplied to the data bus 1422 is written into the RAM 1401. On the other hand, the RAM 1402 is write disabled by the switching signal 1420 and the data bus 142
3, the read data from the RAM 1402 is output. The read data is selected by the multiplexer 1407 in accordance with the switching signal 1420, and the output terminal 1415
Output to Next, when the switching signal 1417 becomes 1, the switching signal 1420 becomes 0, the multiplexer 1403 selects the read address 1419, the multiplexer 1404 selects the write address 1418, and the buffer 1405 disables the buffer 1414.
06 is enabled and the write data 1416 is R
Data written to the AM 1402 and read from the RAM 1401 is selected by the multiplexer 1407 and output from the output terminal 1415.

As described above, the RAM 1401 and the RAM 14
02 alternately inverts the switching signal 1417 line by line, so that the recording data 1416 is written alternately to the RAM 1401 and the RAM 1402 line by line.
418, and the data stored one line before is alternately stored for each line.
By reading data from the RAM 1401 and the read address 1419 in accordance with the read address 1419, continuously input data can be output with one line delay.

In the line memory 1303 of FIG. 11 having the above configuration, the color difference signal sample 113 is used as write data, the write address 1311 is used as a write address, the read address 1313 is used as a read address, and the switch signal 1318 is used as a switch signal.
Supply. The line memory 1304 also supplies the luminance signal sample 112 as write data, the write address 1312 as a write address, the read address 1314 as a read address, and a switch signal 1318 as a switch signal.

FIG. 13 shows line memories 1303 and 1304.
Is shown in a time chart. As shown in the figure, samples of the Cb and Cr components are alternately input to the color difference signal sample 113. Note that Cbn and Crn in FIG.
Represents a sample belonging to the n-th pixel of one line. As described above, since the color difference components belong to the even-numbered pixels, n is an even number. On the other hand, the write address 1311 is represented by the formulas (3), (6), and (7).
It is composed of g, ch, splSeg and comp0 which is the LSB of the component number comp.

As shown in the figure, the Yc and Yi component samples are alternately input to the luminance signal sample 112. Note that Ycn and Yin in FIG. 14 represent samples belonging to the n-th pixel in one line. As described above, since the luminance signal belongs to both the even-numbered pixel and the odd-numbered pixel, n has both an even number and an odd number. On the other hand, the write address 1312 is defined by the seg, ch, splSeg and the component number comp shown in Expressions (3), (6), and (7).
Is configured by comp0 which is the LSB of.

The specific numerical values shown in FIG. 13 correspond to the line of lin = 0 in FIG. For example, Cb0, which is a Cb component sample of the 0th pixel, is one of two RAMs forming the line memory 1303.
Address (comp0, ch, seg, splSe)
g) = (0,0,0,0), so that the effective samples Cb and Cr of one line
Samples are successively written to addresses (comp0, ch, seg, splSeg) represented by equations (3), (6), and (7).

Generates a write address sequence as described above.
The write address generation circuit 1306 performs the synchronization control circuit.
Reset by horizontal and vertical synchronization signals from path 109.
Counter and the count value decoder
Can be easily realized.

Recording channel according to the above-described method of the present invention
And the line memory 130 according to the segment arrangement.
After one line of data is arranged on 3,1304
In addition, by reading this as described below,
Samples of components Yc, Cb, and Cr belonging to the same pixel
Recording / playback with adjacent heads and simultaneously adjacent sample points
Pixel data is recorded and reproduced by different heads.
Swell.

After the effective samples are stored for one line period as described above, the two RAMs inside the line memory 1303 and the line memory 1304 are switched by inverting the switching signal 1318, and the stored one line period is stored. Read out the sample. At this time, the reading is performed in such an order that the splOCseg represented by Expressions (11) and (12) increases from 0. Therefore, the read address 1313 and the read address 1314 are obtained by the following equations, which are inverse functions of the equations (11) and (12), respectively (com
p0, ch, seg, splSeg). That is, when comp = 0, 1, 2 (components Yc, Cb, C
r), splSeg = (baseFactor '* splOCseg-chOfst' [ch] -segOgst '[seg] -linOfst' * lin) mod NSSpSeg (14), and when comp = 3 (data of component Yi) Case), splSeg = (baseFactor '* splOCseg-chOfst' [ch] -segOgst '[seg] -linOfst' * lin-compOfst ') mod NSPlSeg (15) However, baseFactor 'is, baseFactor * baseFactor' is the minimum value satisfying mod NSplSeg = 1 (16), chOfst '[ch] = chOfst [ch] * baseFactor' mod NSplSeg segOfst '[seg] = segOfst [seg] * BaseFactor 'mod NSplSeg linOfst' = linOfst * baseFactor 'mod NSplSeg compOfst' = compOfstst * baseFactor'mod NSplSeg (17). FIG. 14 shows an example of this read address. As shown in the figure, comp0 is set to 0, 0, 1, 1,.
In the order of 0, 1, 0, 1, 2, 3, 2, 3,
Read all of the 0 segments in the order of..., And then read 1 segment and then 2 segments. The resulting output data 1315 and output data 1316 are in the order of Cb, Cb, Cr, Cr, and in the order of Yc, Yc, Yi, Yi, respectively, and the sample order is different from the original order by shuffling.

The read address generation circuit 1307 for generating the above read address series can be easily formed by a counter reset by the horizontal and vertical synchronization signals from the synchronization control circuit 109, a decoder for the count value thereof, and some arithmetic circuits. realizable.

The switching signal 1318 is generated by the switching circuit 1308, and is alternately set to 0 every line.
And 1 are repeated. The switching circuit 1308, the write address generation circuit 1306, and the read address generation circuit 1307 operate in synchronization with an input video signal according to a control signal (not shown) sent from the synchronization control circuit 109 in FIG.

In the examples shown in FIGS. 13 and 14, baseFactor = 1 chOfst [0] = 0 chOfst [1] = 20 chOfst [2] = 0 chOfst [3] = 20 segOfst [0] = 0 segOfst [1] = 33 segOfst [2] = 26 linOfst = 4 compOfst = 34 (18)

Next, the exchange circuit 1305 provides the color difference signal data 1315 and the luminance signal data 1316 after shuffling.
Are divided into data of channels 0 and 1 and data of channels 2 and 3. Figure 1 shows the detailed block diagram.
It is shown in FIG.

A line memory 1303 is connected from a terminal 1701.
, And Cb and Cr component data 1315 read from the line memory 1304 are input from the terminal 1702. As shown in FIGS. 14 and 16, these input data are read out at channel numbers of 0, 1, 0, 1, 2, 3, 2, 3, and 8 clock cycles, respectively . In FIG. 16, Yc,
Put this channel number on the shoulder of each symbol of Yi, Cb, Cr.
Is shown . Data 1316 is the D flip-flop 17
03, 1704, 1705, and 1706, the data is delayed by 4 clocks to obtain delay data 1716. Thus, as shown in FIG. 16, the data 1315 and the delay data 1716 do not overlap the data of the same channel with the same clock. Therefore, the multiplexer 17
07 is 0 and 1 from data 1315 and data 1716
Only the data of the channel is selected to be the data 1717 of the 0 and 1 channels, and the multiplexer 1708 selects only the data of the 2 and 3 channels from the data 1315 and the data 1716, and the data 1 of the 2 and 3 channels is selected.
16 is obtained. For this purpose, the switching signal 1317 input from the terminal 1715 may be inverted every four clocks as shown in FIG. This inverted signal 1715 is shown in FIG.
As shown in FIG. 1, it is supplied from the read address generation circuit 1307. The data 1717 of the 0 and 1 channels is D
Flip-flops 1709, 1710, 1711, 17
The data is delayed by 4 clocks by 12 and output as 0 and 1 channel data 115 at the same timing as the 2 and 3 channel data 116.

The data 115 of the 0 and 1 channels obtained as described above are such that the data of the channel 0 and the data of the channel 1 are alternately arranged, and the Cb, Cr, Yc and Yi components are arranged in the order of each channel. Further, each component is arranged in the order of outer coding. The outer encoding circuit 103 outer-encodes the data 115 for each component of each channel. Two, three
The same applies to the channel data 116.

In the outer-coded data 117, the data of channel 0 and the data of channel 1 are alternately arranged. The demultiplexer 104 alternately divides the data into data 118 of channel 0 and data 119 of channel 1. An error correction matrix is configured for each channel.

A write control signal 120 of the field memory 105 for realizing the matrix shown in FIGS.
As described with reference to FIGS. 9 and 10, the data 118 generated by the field memory control circuit 106 and transmitted in the order of Cb, Cr, Yc, and Yi are stored in four horizontally continuous columns as described above. , Cb, Cr, and Yi.

The outer coded data 118 is written one after another in this manner, and when one field is written, the matrices shown in FIGS. 9 and 10 are formed.

On the other hand, the read control signal 121 of the field memory 105 is generated by the field memory control circuit 106, and includes the vertical and horizontal addresses of the matrix shown in FIGS. In accordance with the read control signal 121, the written data for one field of each channel is read as described above.

As described above, in the digital video recording apparatus according to the embodiment of the present invention, the above-described digital video recording method of the present invention can be realized by using the channel / segment distribution circuit 102 and the field memory 105, and The sample data of the Yc, Cb, and Cr components belonging to each pixel can be recorded using the same recording head, and the sample data of the pixels adjacent to each component on the screen can be dispersedly recorded on the tape. Thus, it is possible to improve the reproduction image quality when an error occurs.

In the above description, when writing the four outer codes belonging to the same line into the field memory, the order of the columns formed by the four outer codes in the matrix shown in FIGS. C
b, Cr, Yi, which are Yc, Cr, Cb,
Yi or Cb, Cr, Yc, Yi or Cr, C
b, Yc, Yi or Yi, Yc, Cb, Cr or Yi, Yc, Cr, Cb or Yi, Cb, C
r, Yc or Yi, Cr, Cb, Yc. This takes into account the following:

The samples of the Yc, Cb, and Cr components belonging to the pixels at the same position arranged in the horizontal direction in the field memory are as follows:
If the data does not extend over the 85-byte boundary of the inner data, it is recorded as the same inner block. Since one line of data is written in four columns each, while the inner data is divided into 85 bytes each, the boundary of the inner data for the four bytes of Yc, Cb, Cr, and Yi data that are continuous in the horizontal direction is: Between Yc and Cb, Cb and Cr
, There is a case where it enters between Cr and Yi. Of these, Cb
Only when the boundary of the inner data overlaps between the Cb and Cr, samples of the Cb and Cr components belonging to the pixel at the same position are recorded as different sync blocks, and otherwise, they are recorded as the same sync block.

When the samples of the Cb and Cr components belonging to the pixel at the same position enter different sync blocks, the Cb and Cr components belonging to the pixel at the same position are not updated simultaneously during shuttle reproduction. When only one of the sync blocks is updated, there is a possibility that the image quality is degraded. Therefore, it is desirable that such a case be minimized. Also,
During reproduction, an error may occur in sync block units due to a synchronization error. In such a case, the Cb and Cr components may not be updated simultaneously.

For example, the order of the four outer codes is C
Assuming that b, Yc, Cr, and Yi, the boundary of the inner data may fall between Cb and Yc, between Yc and Cr, or between Cr and Yi. Of these, Cb belonging to the pixel at the same position
The samples of the Cb and Cr components enter different sync blocks in two cases between Cb and Yc and between Yc and Cr, and it is likely that the Cb and Cr components are not updated simultaneously as described above.

Therefore, by avoiding such a case, the sample data of the Cb component and the sample data of the Cr component are written continuously in the horizontal direction on the field memory as described above, so that they belong to the same pixel. Cb
The case where the sample data of the component and the Cr component are recorded in different sync blocks is reduced, and the image quality during reproduction is improved.

Further, the field memory 10 described above is used.
The reading order from 5 may be as follows.

When data is read from the field memory 105, the number of segments per field is 3 in the case of the 525/60 system. Therefore, when data is read from the same point of the field memory for each field, the head for recording / reproducing each segment is a The side and the b side are switched for each field. For example, when it is assumed that reading is performed as described above starting from point D in FIG. 9 for each field, in the first field, the first 40 rows (seg = 0) are the heads on the a side, and the next 40 rows (seg = 1). Is recorded by the head on the b side and the last 40 rows (part of seg = 2) are recorded by the head on the a side, and in the next field, the first 40 rows (s
(eg = 0) is the head on the b side, and the next 40 rows (s
(eg = 1) is the last 40 rows (s
(eg = 2) is recorded by the head on the b side, and the head for recording or reproducing each segment is switched for each field. In such a case, for example, when a head clog occurs in one head on the side a, the pixel having the same address on the field memory as the pixel of the error distributed to that head becomes b in the next field.
Will be distributed to the side head. Therefore, during reproduction, the data at that address is updated every other field.

On the other hand, in the case of the 625/50 system, the number of segments per field is four. Therefore, when data is read from the same point of the field memory every field, the head for recording / reproducing each segment does not change. In this case, when the head clog occurs in one head on the side a, the pixel having the same address on the field memory as the pixel of the error distributed to that head is also distributed to the same head in the next field. That is, at the time of reproduction, the data at that address is not updated forever.

Therefore, in the case of the 625/50 system, for example, in the first field, starting from point E in FIG.
Point, point A, point a, one track, starting from point F, point f, B
Point b, point b starting from the next track, point G, point g, C
Point, c point, starting from the next track, point H, point h, D
When data is read out so that the points d and d are the next one track, the next field is read out in the same manner starting from the point F or H, so that the read start point of the next field is shifted by one segment. 525/60
As in the case of the system, the head for recording each segment can be switched for each field.

Even in this case, the segment number seg
The present invention is effective only by exchanging the correspondence of the tracks on the tape on which the recording was actually performed, and by doing so, even if either the recording head or the reproducing head fails, recording is performed by the failed head. Or, since the pixels to be reproduced are different in successive fields, the pixel to be modified changes in successive fields, and at the same time the field memory in the reproduction is updated every other field,
Since the pixel data can be replaced with the pixel data at the same position in the previous field, the reproduction image quality is improved.

[0124]

As described above, according to the present invention, sample data of a luminance signal component and sample data of two color difference signal components sampled at the same position on a television screen are recorded using the same recording head. At the same time, for each of the luminance signal component and the two color difference signal components, sample data of two adjacent sample points on the television screen can be recorded by different recording heads.
You. Also in this case, sample data of two sample points close to each other on the television screen for each of the luminance signal component and the two color difference signal components can be recorded on a recording medium at locations separated from each other . Accordingly
As a result, it is possible to effectively correct various errors generated during reproduction, and to improve the image quality of a reproduced image.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a recording apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a sampling structure of digital video data.

FIG. 3 is a plan view showing a head configuration according to an embodiment of the present invention.

FIG. 4 is a schematic view showing a tape pattern according to one embodiment of the present invention.

FIG. 5 is an explanatory diagram showing one distribution example of each pixel in one embodiment of the present invention.

FIG. 6 is an explanatory diagram showing another distribution example of each pixel in one embodiment of the present invention.

FIG. 7 is an explanatory diagram showing an example of distribution of a luminance signal component in one embodiment of the present invention.

FIG. 8 is an explanatory diagram showing an example of distribution of color difference signal components in one embodiment of the present invention.

FIG. 9 is a schematic diagram showing one memory map of a field memory in one embodiment of the present invention.

FIG. 10 is a schematic diagram showing another memory map of the field memory in one embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a channel segment distribution circuit according to an embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a line memory according to one embodiment of the present invention;

FIG. 13 is a timing chart showing a write operation of a line memory in one embodiment of the present invention;

FIG. 14 is a timing chart showing a read operation of a line memory in one embodiment of the present invention;

FIG. 15 is a block diagram showing a configuration of a switching circuit in one embodiment of the present invention.

FIG. 16 is a timing chart showing the operation of the switching circuit in one embodiment of the present invention.

FIG. 17 is a schematic view showing a tape pattern in a conventional example.

FIG. 18 is an explanatory diagram showing channel division in a conventional example.

[Explanation of symbols]

 105 Field memory 1303, 1304 Line memory 1305 Switching circuit 1306 Write address generating circuit 1307 Read address generating circuit 1308 Switching circuit

Claims (8)

(57) [Claims] 1. An even-numbered scanning line on each scanning line constituting one screen
Pixel has a luminance signal component of the first type and two color differences
Odd-numbered pixels are composed of signal components
Digital signal composed of the luminance signal components
Video signal is divided into four signal components constituting one screen.
4 records to record sample data equally for each component
Recording channel and the sample data constituting the one screen.
Data evenly for each recording channel and each component.
Divided into three or four segments,
The even-numbered segment and the odd-numbered segment
Scanner configured to be scanned by a recording head
The digital video signal is recorded on a tape using
In which the pixels on each scanning line constituting the one screen are consecutively arranged.
Divided into 6 or 8 pixel groups, and all the pixel groups constituting the one screen are
Each pixel that makes up each pixel group should be recorded
Segments are the same predefined standard segments
The first picture on the first line constituting the one picture determined by the number pattern
For each pixel constituting the element group, each of the pixels is described.
The channels to be recorded are
The two pixel groups adjacent to each other in the horizontal direction on the same scan line are determined by the channel number pattern.
Pixels in the right pixel group
Channel number pattern representing the channel to be recorded
Indicates the pixels that make up the left pixel group.
Channel number pattern representing the channel to be
Channel with each channel number shifted by 1 or 3.
Channel number pattern consisting of
And two vertically adjacent pixel groups on the same screen.
Each pixel that constitutes the lower pixel group
Channel number pattern representing the channel to be recorded
Indicates that each pixel constituting the upper pixel group is recorded
Channel number pattern representing the power channel
Channel with each channel number shifted by 1 or 3.
Channel number pattern consisting of
Determined such that, said first luminance signal component and two constituting each pixel
Sample value data of a color difference signal component and the second luminance
The sample data of the signal components is
The channel number pattern corresponding to the elementary group; and
The recording channel indicated by the segment number pattern
By recording in the segment of the even number
Luminance signal component of the first type constituting an eye pixel
(Yc) and the color difference signal components (Cb, Cr).
Record the sample value data on the tape with the same head.
Sample data belonging to adjacent pixels on the screen
Are recorded with different heads, and next to each other on the screen.
The sample data of the two adjacent color difference signal components is
Recording with different heads for each component
And a digital video recording method. 2. A pixel group comprising three segments.
The number of pixels to be processed is 6, and the standard segment number pattern is (0,
1,2,0,1,2), standard channel number pattern
Is (0,0,2,0,0,3), (0,0,2,0,
1,3), (0,0,2,0,2,3), (0,0,
2,0,3,3), (0,1,2,0,0,3),
(0,1,2,0,1,3), (0,1,2,0,2,
3), (0, 1, 2, 0, 3, 3), (0, 2, 2,
0, 0, 3), (0, 2, 2, 0, 1, 3), (0,
2,2,0,2,3), (0,2,2,0,3,3),
(0,3,2,0,0,3), (0,3,2,0,1,1)
3), (0, 3, 2, 0, 2, 3), (0, 3, 2,
2. The method according to claim 1, which is any one of (0, 3, 3).
Digital video recording method. 3. A pixel group comprising four segments.
The number of pixels to be processed is 8, and the standard segment number pattern is (0,
0,1,1,2,2,3,3), standard channel number
If the pattern is (0,2,0,2,0,2,0,2),
(0, 2, 1, 3, 0, 2, 1, 3), (0, 2, 2,
0, 0, 2, 2, 0), (0, 2, 3, 1, 0, 2,
The data according to claim 1, which is any one of (3) and (1).
How to record digital video. 4. A pixel group comprising three segments.
The number of pixels to be processed is 6, and the standard segment number pattern is (0,
2,1,0,2,1), standard channel number pattern
Is (0, 2, 1, 1, 3, 0).
How to record digital video. 5. An even-numbered scanning line on each scanning line constituting one screen
Pixel has a luminance signal component of the first type and two color differences
Odd-numbered pixels are composed of signal components
Digital signal composed of the luminance signal components
Video signal is divided into four signal components constituting one screen.
Of the sample data for each component
A recording channel and the sample constituting the one screen
Data is evenly recorded for each component for each recording channel.
Tape divided into three or four segments for recording
Above, even numbered segments and odd numbers for each channel
Segments are scanned by different printheads
Video recorded using a scanner with such a configuration
Recording device, It has the four recording channels and has
Record pull data in the three or four segments
Recording circuit, A line for storing the four signal components in the one scanning line period
Memory and A controller in which four values correspond to each of the four signal components
Component address and each of the four recording channels
A channel address corresponding to each of the four values,
3 or 4 for each of the 3 or 4 recorded segments
And the same segment address as
In the recording channel, recorded in the same recording segment
The one scan line of samples of the same signal component
Consists of sample addresses that represent serial numbers in
And every 6 or 8 consecutive pixels on the scan line
Is referred to as a pixel group, the segment address
Is the same for all the pixel groups.
And the standard segment number pattern
The channel address is the first line that constitutes one screen
Predefined for the first pixel group of
Use a fixed standard channel number pattern, and
And the standard channel for each pixel group in the vertical direction.
Channels with channel number patterns shifted by 1 or 3
Channel number pattern consisting of
Write address that generates such a write address
A generating circuit; Similarly, the component address and the channel
Address and the segment Address and the sample
Address and the channel address and
The segment address is used at the input to the recording circuit.
To match the recording channel number and segment number
Read address generation to generate a read address
And a circuit, The four signals of the input digital video signal
A sample of the components is placed in the line for each scan line period.
Before the write address generation circuit of the memory
Stored at the write address and stored in the line memory
The read address generation circuit generates the sampled data.
By reading from the read address generated, The first type of luminance that constitutes the even-numbered pixel
The sample data of the signal component and the two color difference signal components
The same segment of the same recording channel on tape
Record with the same recording head and adjacent on the screen
The sample data belonging to the pixel
And the two adjacent ones on the screen
The sample data of the color difference signal components
Recording with different recording heads.
Digital video recording device. 6. A pixel group comprising three segments.
The number of pixels to be processed is 6, and the standard segment number pattern is (0,
1,2,0,1,2), standard channel number pattern
Is (0,0,2,0,0,3), (0,0,2,0,
1,3), (0,0,2,0,2,3), (0,0,
2,0,3,3), (0,1,2,0,0,3),
(0,1,2,0,1,3), (0,1,2,0,2,
3), (0, 1, 2, 0, 3, 3), (0, 2, 2,
0, 0, 3), (0, 2, 2, 0, 1, 3), (0,
2,2,0,2,3), (0,2,2,0,3,3),
(0,3,2,0,0,3), (0,3,2,0,1,1)
3), (0, 3, 2, 0, 2, 3), (0, 3, 2,
6. The method according to claim 5, which is any one of (0, 3, 3).
Digital video recording device. 7. A pixel group comprising four segments.
The number of pixels to be processed is 8, and the standard segment number pattern is (0,
0,1,1,2,2,3,3), standard channel number
If the pattern is (0,2,0,2,0,2,0,2),
(0, 2, 1, 3, 0, 2, 1, 3), (0, 2, 2,
0, 0, 2, 2, 0), (0, 2, 3, 1, 0,2,
The data according to claim 5, which is any one of (3) and (1).
Digital video recording device. 8. A pixel group having three segments.
The number of pixels to be processed is 6, and the standard segment number pattern is (0,
2,1,0,2,1), standard channel number pattern
Is (0, 2, 1, 1, 3, 0).
Digital video recording device.