JPS5947891A - Carrier signal generating circuit - Google Patents

Abstract

PURPOSE:To obtain a required carrier for both the NTSC and the PAL systems with a simple constitution, by changing the oscillating frequency of the 1st oscillator oscillated at a multiple of a horizontal frequency so as to apply the required offset to each of the systems. CONSTITUTION:The 1st oscillator 16 oscillated at a multiple of a horizontal frequency fH is set to a different frequency for the PAL and the NTSC systems. An output of the 1st oscillator 16 is frequency-divided at frequency dividing circuits 17, 2, and signals a1-a4 having different phase by 90 deg. each are formed. Then, the frequency offset is applied at the 1st oscillator 16. Signals obtained from D-FFs 4, 10, i.e., two signals phase-shifted at 90 deg. at each horizontal period and having a 90 deg. of phase difference, are applied to converters 12, 6. The 2nd oscillator 19 is oscillated at a chrominance subcarrier frequency, and the signals having a 90 deg. of phase difference are applied to the converters 12 and 6. An adder circuit 13 adds the outputs of the converters 12, 6 and output the carrier required for the frequency conversion of a chrominance signal of a VTR.

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to a carrier signal generation circuit for generating a carrier necessary for frequency conversion of VTItO color (No. 5). [Prior Art] Using an arithmetic filter, ``ν I converter (referred to as the lower converter).
As an example of the iis system, there is one shown in FIG. In Figure 1, 1 is the first oscillator that oscillates at 160 fu (flI is the horizontal frequency), 2 is the frequency divider circuit, and 3 is the 90
Two 40° phase difference. fn 4:l Signal switching circuit that outputs the bow, 4 is the first J) -1='j
゛',, 5 is the first L P I! ', 6 is a converter,
7 digits P A L history fsc + 1f,,,l-1'Ts
c14. ! Second oscillation 8 de, 8 is 13 P F, 9
is carrier output terminal, 10B, 2+) -F, I
='. , 11 is the second LP 11', 12 is the second converter, 13 is the addition η, and 14 is -90°fi/: ;i
'll Jll transfer circuit, 15 is a horizontal periodic pulse input terminal, and 25 is a 1/16o frequency dividing circuit. The original raccoon dog will be explained using FIG. First of all, there will be four different NTSC 4OfH titles. In the No. 11 switching circuit 3, the four 40fil signals, which are the output of the 7 frequency divider circuit 20, are
(40f with a 90° phase shift to H4n- by switching every time)
Two l+ signals are output ``4-''.The 4''F'r switching circuit 3 is constructed in rows as shown in FIG. 6, for example. 81 to a4 are h(・[4 with a 90° phase shift)
The OfH signals, I11 to I-J4, are each frequency-divided from the horizontal synchronizing pulse.

01 to G8 are 2-man NA, ND gate, (
1 o. Mountain. is a 4-person NANI) gate. According to this, the two outputs φ1 and φ2 are such that φ2 is always φ
While the phase relationship of 90°a is maintained for ,
The phase is delayed by 90° for each H. This 1■
A typical phase sum shift process is performed to reduce crosstalk components from adjacent trunks. In this way, two desired outputs are obtained. These two elements τ1 are the first D−1(,F,4 and the second I)l・′,+
:', with the same chronoquil word as io, ``tap 1 white'', IJ-L ~ < 90° θ, 11 (so that the Seki 1 thread is maintained / I. This first, second 2-1) -j+", t", 4, 11'
The 4OfH signal, which is generated by the output of ], is generally a 1° 1] wave, so it contains many 40J'u high ii1...1 wave components.
'C゛8J', '1, 1,000,' 20) L l'
f" 5.11 The secret to this! To reduce the wave components, respectively, 2σ", 7B 1, and the second converter 6, .12 are respectively supplied with A'14. When P is turned on, the oscillation frequency of the oscillator 7 is equal to fsc, B, and fjr off. This is to prevent beat interference to the Y signal.Also, due to the low frequency component of the cross-1 component from the adjacent track, γ selection (R The bow is NTS
Make it different from C time. For example, NTSC- has one field of 1-ju, - and 11. , l-12, l-1,, H
1" 1...J11 White plays J (igll, and in the other field, 1-14, ■13, H2, 115, H
4-o) You can set Llight to Il+, but F A-
LIL'
-l-1i+ binding, one field is H,,113,11
2, H,, H4 are set to High in the order of 1, while the 2nd
The output of the oscillator 7 is supplied to the second converter 12, while the phase is delayed by 90 degrees through the 90 degrees phase Mtt shift circuit 14, and the output is supplied to the first converter 6. Therefore, in the first converter 6, the following formula: Kaketori will be held. (5in2π”Ofu”t) sin2π0fSC@m-(cos 2π(,f8C+40.fH)t-CO
32π(fsc-4OfH)t)...(2) Therefore, when the two converter outputs are added together, CO32π(fsc+'ofH)t...
(3), only the sum frequency component remains and the difference frequency component is removed. For this reason, the output of the emulator 13 has almost no sugerias component, so the conventional trap is no longer necessary for Hl) JI' 8, and for example &;
It is possible to perform iM in a very discrete manner, and of course, there is no need for WM adjustment. Based on the above H71 configuration, the expression '(', carrier generator using an l-type filter value 1:' A TJ/N i'
When considering support for both types of SC, the following points must be considered. (1) Since the frequency of the color subcarrier is different in both systems, the excavation frequency of the second oscillator 7 must be changed. (2) 11, 1 of the −90° phase I1-shifting circuit 14.
changing constants. (3) Changing the BPF80 pot frequency. Particularly when considering the use of IC circuits, (2) becomes a problem. For (1), the oscillation frequency conversion is done using an external X
This is because the addition of ``tal'' can be replaced, and since B P F 8 uses L, it is usually assembled with discrete parts. The simplest way to construct a 190° phase shift circuit is to
This method takes advantage of the fact that the voltage across both ends of C, the voltage across C, 'FD', shifts by 90°. Therefore, the fsc is different.
To support both PAL/N'J'SC, one of the LC's parts must be changed, so this part should be made external.
Must be. This results in problems such as an increase in the number of IC bins and the need to adjust the time constant. Moreover, if the -90° phase shift circuit 14 is sealed within 1 (z), the time constant is 1/2π・4.43MH in PAL.
z and N '1'' 80 o'clock 1/2π・3.58 MH2
There is no choice but to set it somewhere between the two, and this will hinder the performance of the arithmetic filter. [Object of the Invention] An object of the present invention is to provide a new carrier signal generation circuit compatible with both PAL/NTSC systems, which overcomes the above-mentioned disadvantages. [Summary of the Invention] The present invention utilizes the NTS C system and J'
This is done by increasing the oscillation frequency of the oscillator 9 by increasing the oscillation frequency of the oscillator 1. Excavation frequency p of the second oscillator N T
Both the SC system, PA, and I systems use the color subcarrier frequency, and use the phase shift circuit of the oscillator to generate the 2IH signal with a 907Q difference and supply it to the Subconverter. [Embodiment of the Invention] FIG. 2 is a block diagram showing an embodiment of the present invention. In FIG. 2, the same numbers as in FIG. 1 indicate the same components. 16
is 375f in P A L/N 71' SC. The first oscillator oscillates at a frequency of /378 fH, 17 is an i frequency divider circuit, 18 is a PAJ, and two (47-g) fn/(47+7
) Signal switching circuit that outputs fn-1, 19 is PΔJ
,/NTSC. In both cases the second oscillator excavated at 9, 26 is the PA
This is a frequency divider with a variable division ratio of 37.57'378 for L/NTSC. The present invention will be explained in detail using FIG. The output of the first oscillator 16 is frequency-divided by the 1 frequency divider circuit 17.7 frequency divider circuit 2, and is (47--)
, fH/< 47 +-) iH, and the output of the 7-divider circuit 2 has a1 to a whose phases differ by 90 degrees from each other.
4 is made. By doing so, the frequency offset can be increased on the first oscillator 16 side. Also 37
5f, . . , 678fH can be easily divided to fH. (375=3X5X5X5.678=3X3X6X
7) The main parts of the signal tjJ switching circuit 18 are revised as shown in FIG. 6 in the same way as in the conventional example shown in FIG. l'
During AJJ, the signals a to d shown in FIG. 4 are added to the input signals H, to H4, as in the example of FIG. 1. As a result, the outputs φ1 and φ2 of the signal switching circuit 18 become signals whose phase is delayed by 90° for each signal switching circuit 11 and whose phases are shifted by 90° from each other. Also, N '11' S 0 o'clock is a1~a
4, add each signal a to d shown in FIG.
1, φ2 has 90° to each other with the phase reversed for each H.
Obtain out-of-phase signals. The phase shift process described above is performed to reduce crosstalk components from adjacent trunks. The above-mentioned signals for PAL/NTSC shown in FIGS. 4 and 5 can be generated by the example shown in FIG. 6, for example. In Figure 6, 4
0 is a horizontal synchronizing pulse input terminal, 41 is the first D-F,
F,,42 is the second 1)-F,F,,43 is PAL/N
Powered by T8C changeover switch circuit. The number 11 of the switches 46 in FIG. 6 indicates the PAL mode. The horizontal synchronizing signal from the input terminal 40
−+−゛, F, 41.42, and their B4 force is divided by the gates 611 to ()14, which is the logic t7 (in FIGS. 4 and 5). Obtain follow-up signal. D-J(', lii, 4, io, LJ'l's, 11
The construction of +lil+ is the same as that of the conventional example shown in FIG. The second oscillator 19 is a VCO equipped with a phase detection voltage input terminal 26 as shown in FIG. 31 is the first 45° phase] 11 shift circuit, 62 is X't
al, 66 is an inverter, 34 is a -90° phase] 1j is a shift circuit, and 35 is an adder whose addition/q ratio changes depending on the voltage of the input terminal 23. If the input number 48 to the -45° phase shift circuit 31 is expressed as a vector as shown in Figure 8a, the output of the circuit 31 is as shown in Figure 8, and the output signal of the -90° phase sum shift circuit 34 is It is C. Therefore, the output of the inverter 33 becomes d in FIG. 8, and b and d
is a 90° phase difference. As an older brother to this example, VCU
There are signals with a phase shift of 90° in the circuit No. 19, among which the leading phase signal (M) is sent to the second converter 12, and the delayed phase signal is sent to the first converter 6. As a result, as shown in FIG. The -90° phase mt shift circuit 14 in the i ta m 2 ) generator 4H generator 19 It'! ,,PAL/
Both N'vSC and CO oscillate at frequencies with no offset, and are equipped with a phase detector 36, a killer detector 37,
It also serves as the reference signal source for ＼. 40 is a burst signal input terminal, 38 is a phase detection voltage input terminal, and 39 is a killer detection voltage output terminal. first and second converters 6.12, second oscillator 19,
FIG. 7 is shown as an example of a specific circuit of the adder 16. 20 is an input terminal to which the output of the first LPF'5 is applied;
1 is an input terminal to which the output of J and P I4' 11 is applied, and 22 is an output terminal of the adder 13. In Figure 7, the connection between C8 and 3 is shown in Figure 10 (Figure 10), which is the emitter follower (lower) CF of Q44; ) to the base of Qia. The connection point between 1 and 3 and C4 corresponds to the output of the 190° phase shift IFi switch 34 in FIG. 2, and the signal there is represented by vector d in FIG. 10. This is (Jl, no. 1)
, and Q. Therefore, the output of the differential pair of Q and QIO is f in FIG. 10 on the collector side of Q9, and the output of the differential pair of Q and Q is g on the collector side of Q. The output of
R through the differential pair between Q2 and Q3 and the differential pair between Q7 and Q8.
6, it is added 'P+-. Q2 and Q3, and Q, and Q
The base difference voltage with respect to 8 is applied from the phase detection voltage input terminal 23 and changes the addition and q ratio of g and f. These Q2 and Q
Differential pair with 3, Q? and Q8 differential pair, 几. corresponds to the power unit 35 in FIG. The output of the booster 35 is
and C2, the first 45° phase shift circuit 31
It will be affected by it. On the other hand, Q, and Q,. Among the outputs of the differential pair with Qia, the collector side of Qia is e in FIG. Further, among the outputs of the differential pair of Q2 and Q3, the collector side of Q4 is h in FIG. 10, and this is led to the second converter 2 through E1+N of Qia. The operation of the first converter 6 is based on P from the input terminal 2°.
In the A, L method, (47-H) fH,N, and in the TSC method, (47+7), PAL is achieved by switching the f+i signal at fBc with the differential pair of Q24 and Q211 and the differential pair of Q26 and Q27. In the method (475) f
n, N T S C method, (47+7)fu and fsc
It is used to multiply. Kakehiro, output is Q25 and Q
The collector of 27 is connected to R22 and obtained at the output terminal 22. The second converter 2 also operates in the same manner as the first converter 6, but the signal from the input terminal 21 is delayed by 90 degrees with respect to the input terminal 20 and No. 1. fsc in the second converter 12 is advanced by 90° relative to the first converter 6. The outputs of the second converter 12 are Q20i6 and Q3'1
Connect the collector of ``l!'f'' to output terminal 22 and connect it to R22.
60 Therefore, the output terminal 22 is outputted by adding the output of the second converter 6.12. Therefore, the output terminal 22 corresponds to the output of the adder 15 in FIG. 2. NTSC In this method, the sum frequency of (47 + 7) fH is used as the pass band, and this can naturally be a loose one with y%F and one choice. Second used
The oscillator 19 is not limited to the example shown in FIG. For example, it is also possible to use shield/form ■CO such as a-c and d in Fig. 9. In Fig. 9, 50 is a +45'' phase shift circuit, 51 is a -90° phase shift circuit, 52 is a phase inversion circuit, 56, 54, and 55 are q adders, and 61, 62 have a phase difference of 90 degrees from each other. , 61 is the leading signal, and 62 is the output terminal of the delayed signal No. 1.
Since it is fixed at 1, the explanation is omitted here. The output terminals 61 and 62 of CO are respectively connected to the second converter 12 in FIG.
When the first converter 6 is guided, the same effect as in the example shown in FIG. 2 can be obtained. As described above, the present invention generates the frequency offset required for each of the NTSC system and the PAC system by switching the frequency of the first oscillator 160, and adds a 90 degree phase difference to the second oscillator 19 in a vector manner. The oscillation frequency is controlled by changing the addition ratio, and the PCL is controlled by controlling the addition ratio using the output signal of the phase detector.
The above effect can be obtained by configuring a loop. That is, the frequency of the first excavator 16 is NTSC system (
47+-1i-) fH, PAC method (47-100), f
,. (The recording color signal frequency must be set in combination with the switching method of the phase switching circuit 18.)
P has an offset of τfi1.
In the AC system, any frequency may be used as long as it satisfies the following conditions: ``Have a frequency difference of 1fi+ between tracks'' and have an offset of rib', . In addition, the configuration of the second blower 19 does not have to be limited to the configuration described in 1 to 11; however, if it generates a 2-digit signal having a 90' phase difference in terms of a, this specification is applicable. It is possible to implement [Effects of the Invention] According to the present invention, the second oscillator can be used for phase detection and killer detection without complicating the logic circuit.
Since it is possible to eliminate the need for a -90° phase M alarm circuit without increasing the number of circuits by sharing it with C(J), it is possible to save the number of pins of
'l' For both S and C expressions, a sufficient calculation filter +
I can demonstrate my abilities. Furthermore, when these circuits are integrated into an IC, as shown in the embodiment, the second oscillator and sub-converter can be integrated into the IC, and the number of bins is increased and the outer fence does not require a circuit. Naturally, since the second oscillator, phase detector, and killer detector can all be integrated within the IC, the effect is even greater.

[Brief explanation of drawings]

@ Figure 1 is a block diagram showing an example of a conventional carrier generating device, Figure 2 is a block diagram showing an example of an actual mti carrier generating device # according to the present invention, and Figure 3 is a block diagram showing an example of a carrier generating device #1 according to the present invention.
Figure 4 is a block diagram showing a specific example of the main parts of 1)
An explanatory diagram showing a control signal to the signal switching circuit 3 at the time of A L,
FIG. 5 is an explanatory diagram showing a control signal to the signal switching circuit 3 of the NTSC system, and FIG. 6 is a block diagram showing an example of a specific circuit for generating the control signals shown in FIGS. Figure 7 is
FIG. 8 is a circuit diagram showing a specific example of the second excavator, first and second converters in the present invention, and FIG. 9 is a vector diagram illustrating the operation of the second oscillator in the present invention. FIG. 2 is a block diagram showing another example of a second oscillator used in the present invention. 16...1st oscillator generated at 375 f,, /378 fH, 19...2nd excavator, 6...1st converter, 12...2nd converter, proxy valve Sokuji Usuki 1) Toshiyuki, tl 口25 ノ24 2nd prisoner 3rd (a) O 4 prisoner, 1'5 ward d~]-"-shi"-T-"Otsu figure 0 O9 figure J5 Cow Figure 9 (D) , :?5 , (z o10 a

Claims (1)

[Claims] 90° with a phase shift of 90° for each horizontal period from the output of the first oscillator circuit that oscillates at an integral multiple of the horizontal frequency.
A first converter receives one of the two outputs of the phase shift circuit, and a first converter receives the output of the other phase shift circuit. 2 converter, which outputs two signals that oscillate at the color subcarrier frequency and have a phase difference of 90°, one output signal is sent to the first converter, and the other signal output is sent to the second converter. 1. A carrier signal generating circuit comprising: a second oscillator for supplying the signal; and a summation circuit for adding the outputs of the first converter, the meter, and the second converter.