JPH0231916B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a carrier signal generation circuit for generating a carrier necessary for frequency conversion of a color signal of a VTR.

[Prior art]

In the VHS system, the carrier signal generation circuit uses an arithmetic filter to lower the difference frequency component of the output of a frequency converter (hereinafter referred to as converter).
For example, there is one shown in Figure 1.

In Figure 1, 1 is the first oscillator that oscillates at 160 _H ( _H is the horizontal frequency), 2 is the 1/4 frequency divider, and 3 is the signal that outputs two 40 _H signals with a 90° phase difference. switching circuit, 4 is the first D-FF, 5 is the first
LPF, 6 is converter, 7 is PAL _SC +1/8 _H ,
2nd oscillator that oscillates at _SC (SC is color subcarrier frequency) in NTSC, 8 is BPF, 9 is carrier output terminal, 10 is second D-FF, 11 is second oscillator
LPF, 12 is the second converter, 13 is the adder,
14 is a -90° phase shift circuit, 15 is a horizontal periodic pulse input terminal, and 25 is a 1/160 frequency dividing circuit.

The principle will be explained using FIG. First is the case of NTSC. The output of the first oscillator 1 is frequency-divided by 1/4 by the 1/4 frequency divider 2, resulting in four 40 _H signals having phases different by 90 degrees from each other. In signal switching circuit 3, 1/
The four _40H signals that are the output of the 4-frequency divider circuit 2 are switched for each H, and the _40H signal with a 90° phase shift for each H is
output one. The main part of this signal switching circuit 3 is configured as shown in FIG. 3, for example. A ₁ to _{A 4} are each a 40 _H signal that is 90° out of phase with each other, and H ₁ to _{H 4} are each created by dividing the horizontal sync pulse.
A switching pulse with a 4H period that is high for only 1H period out of 4H, G ₁ to G ₈ are 2-input NAND gates, and G ₉ and G ₁₀ are 4-input NAND gates.

According to this, the two outputs φ ₁ and φ ₂ are always φ ₂
While the phase relationship of 90° delay with respect to φ ₁ is maintained, the phase is delayed by 90° for each H.
This phase shift processing for each H is performed to reduce crosstalk components from adjacent tracks.
In this way, two desired outputs are obtained. These two signals are re-beated by the same clock signal in the first D-FF 4 and the second D-FF 10, respectively, so that a correct 90° phase relationship is maintained.

The _40H signals output from the first and second D-FFs 4 and 10 are generally rectangular waves and therefore contain many _40H harmonic components, so the first and second LPFs 5 and 11 remove these harmonic components. After reducing each, the first,
They are supplied to second converters 6 and 12, respectively.

During PAL, the oscillation frequency of the second oscillator 7 has an offset of 1/8 _H from _{the SC} . This is to eliminate beat interference to the Y signal. Also, because of the low-frequency crosstalk components from adjacent tracks, the selection signals H ₁ to _{H 4} in FIG. 3 are different from those used in NTSC. For example, NTSC
For each field H, H ₁ , H ₂ , H ₃ , H ₄ ,
H ₁ ... can be made High in that order, and in the other field, H ₄ , H ₂ , H ₁ , H ₄ ... can be made High in that order, but in PAL, for example, only H ₁ in one field is always made High. , one field is H ₄ , H ₃ , H ₂ ,
Set H ₁ and H ₄ to High in that order.

On the other hand, the output of the second oscillator 7 is supplied to the second converter 12, while the 90° phase shift circuit 14
The phase of the first converter 6 is delayed by 90°.
supplied to

Therefore, in the first converter 6, the following multiplication is performed.

cos2π・40 _H・t・cos2π・_SC・t = 1/2 {cos2π( _SC +40 _H )t +cos2π( _SC −40 _H )t}...(1) On the other hand, in the second converter 12, the first converter Since the _40H signal is delayed by 90 degrees and _{the SC} is ahead by 90 degrees with respect to the input, the following equation is multiplied.

(−sin2π・40 _H・t) sin2π・_SC・t = 1/2 {cos2π( _SC +40 _H )t− cos2π( _SC −40 _H )t} ...(2) Therefore, the two converter outputs When added, it becomes cos2π( _SC + _40H )t...(3), and only the harmonic component remains, and the difference frequency component is removed.

As a result, there is almost no spurious component in the output of the adder 13, so the BPF 8 does not require a conventional trap, and can be done with a very simple form of, for example, one LC element at a time, and of course requires no adjustment. becomes.

When considering how the carrier generator using the arithmetic filter having the above configuration can be compatible with both PAL/NTSC systems, the following points must be taken into consideration.

(1) Since the frequency of the color subcarrier is different in both systems, the oscillation frequency of the second oscillator 7 must be changed.

(2) Changing the time constant of the −90° phase shift circuit 14.

(3) Change the passing frequency of BPF8.

Particularly when considering the use of IC circuits, (2) becomes a problem. This is because, for (1), converting the oscillation frequency can be done by replacing the external X'tal, and since BPF8 uses L, it is usually assembled with discrete components.

The -90° phase shift circuit is most simply constructed with an RC filter, and takes advantage of the fact that by selecting the time constant T to be 1/2π _SC , the voltage across R and the voltage across C are in phase by 90°. . Therefore, _{the SC} is different.
To support both PAL/NTSC, this part must be externally installed to change either R or C. This results in problems such as an increase in the number of IC pins and the need to adjust the time constant.

Also, if the -90° phase shift circuit 14 is sealed within the IC, the time constant is 1/2π 4.43MHz for PAL.
The only option is to set it somewhere between 1/2π and 3.58MHz for NTSC, which will hinder the performance of the arithmetic filter.

Furthermore, in order to prevent the output of the color signal processing circuit during monochrome signals from being recorded and reproduced as a noise component, the color signal processing circuit of a VTR is equipped with a color killer circuit. requires a reference oscillator that oscillates at the color subcarrier frequency. In the conventional example shown in Figure 1,
Since the oscillation frequency of the second oscillator 7 when supporting the PAL system is a frequency shifted by 1/8 fH from the color subcarrier frequency, it is necessary to separately provide a reference oscillator for color killer in addition to the second oscillator 7.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a new carrier signal generation circuit compatible with both PAL/NTSC systems that overcomes the above-mentioned disadvantages.

[Summary of the invention]

In the present invention, the frequency offset required for each of the NTSC system and the PAL system is achieved by switching the oscillation frequency of the first oscillator. The oscillation frequency of the second oscillator is the color subcarrier frequency for both the NTSC system and the PAL system, and the phase circuit of the oscillator is used to generate two signals with a 90 degree difference and supply them to the subconverter.

[Embodiments of the invention]

FIG. 2 is a block diagram showing one embodiment of the present invention. In this embodiment, the frequency of the carrier signal to be generated is the same as that of the VHS system VTR shown in FIG.
However, the difference in frequency itself has nothing to do with the essence of the present invention, and it goes without saying that the present invention can also be applied to a VHS system VTR. The carrier signal frequency in this example is NTSC
In the case of the PAL method, f _SC + (47 + 1/4) fH is selected, and in the case of the PAL method, f _SC + (47 - 1/8) fH is selected. In FIG. 2, the same numbers as in FIG. 1 indicate the same components. 16
is the first oscillator that oscillates at a frequency of _375H / _378H in PAL/NTSC, 17 is the 1/2 frequency divider circuit, and 18 is the
Two (47−
1/8) _H / (47+1/4) Signal switching circuit that outputs _H signal, 19 is PAL/NTSC, _H in both cases
The second oscillator, 26 is PAL/NTSC
This is a frequency divider with a frequency dividing ratio of 1/375/1/378. The principle of the present invention will be explained using FIG.

The output of the first oscillator 16 is a 1/2 frequency divider circuit 17,
The frequency is divided by 1/4 frequency divider circuit 2, and in PAL/NTSC (47
-1/8) _H / (47 + 1/4) _H frequency, 1/4
At the output of the frequency dividing circuit 2, a ₁ to a ₄ having phases different from each other by 90 degrees are produced. By doing this, a frequency offset can be applied on the first oscillator 16 side. Also, both _375H and _378H can be easily divided up to _H. (375=3×5×5×5, 378=3
(x3x6x7) The main parts of the signal switching circuit 18 are constructed as shown in FIG. 3, similar to the conventional example shown in FIG. During PAL, the input signals to H ₁ to _{H 4} are a to d shown in Figure 4, similar to the example in Figure 1.
Add the signal. As a result, signal switching circuit 1
The outputs φ ₁ and φ ₂ of 8 are signals whose phase is delayed by 90 degrees for each H and whose phases are shifted by 90 degrees from each other. Also
In NTSC mode, _a1 to _a4 are a to d shown in Figure 5.
, and φ ₁ and φ ₂ obtain signals whose phases are inverted for each H and whose phases are shifted by 90° from each other.

The phase shift processing described above is performed to reduce crosstalk components from adjacent tracks.

The above PAL/NTSC signals shown in FIGS. 4 and 5 can be generated, for example, by the example shown in FIG. 6. 6th
In the figure, 40 is a horizontal synchronizing pulse input terminal, 41 is the first D-FF, 42 is the second D-FF, and 43 is the horizontal synchronizing pulse input terminal.
This is a PAL/NTSC switch circuit. The switching position of the switch 43 in FIG. 6 shows the PAL mode. The horizontal synchronizing signal from the input terminal 40 is frequency-divided by the first and second D-FFs 41 and 42, and their outputs are logically ANDed by the gates _G11 to _G14 . Obtain the desired selection signal of the figure.

The operations of the D-FFs 4 and 10 and the LPFs 5 and 11 are similar to those in the conventional example shown in FIG.

The second oscillator 19 is a VCO equipped with a phase detection voltage input terminal 23 as shown in FIG. 3
1 is the first -45° phase shift circuit, 32 is X'tal, 3
3 is an inverter, 34 is a -90° phase shift circuit, and 35 is an adder whose addition ratio of two inputs changes depending on the voltage at input terminal 23. If the input equation to the -45° phase shift circuit 31 is expressed as a vector as shown in Figure 8a, then
The output of the circuit 31 is as shown in FIG. 8b, and the output signal of the -90° phase shift circuit 34 is C. Therefore, the output of the inverter 33 becomes d in Figure 8, and b and d are
90° phase difference. As seen in this example, VCO1
There are signals with a phase shift of 90° in the circuit of 9,
Among them, the leading phase signal is sent to the second converter 12.
, the delayed phase signal is guided to the first converter 6 . This eliminates the need for the -90° phase shift circuit 14 in FIG.

In addition, the second oscillator 19 oscillates at a frequency with no frequency offset for both PAL/NTSC.
VCO, phase detector 36, killer detector 37
It also serves as a reference signal source for the Since it can also be used as a reference signal source, there is no need to separately provide a reference signal source for phase detection and killer detection. 40
is a burst signal input terminal, 38 is a phase detection voltage output terminal, and 39 is a killer detection voltage output terminal.

FIG. 7 shows an example of a specific circuit of the first and second converters 6, 12, second oscillator 19, and adder 13. 20 is an input terminal to which the output of the first LPF 5 is applied, 21 is an input terminal to which the output of the LPF 11 is applied, and 22 is an output terminal of the adder 13.

The voltage at the connection point between C ₃ and R ₁₃ in FIG. 7 is shown as a vector at C in FIG. 10, which is led to the base of Q ₁₀ through the emitter follower (hereinafter referred to as EF) of Q ₁₄ . The connection point between R ₁₃ and C ₄ is the second
This corresponds to the output of the -90° phase shift circuit 34 in the figure, and the signal there is represented by d in FIG. 10 as a vector. This leads through the EF of Q ₁₅ to the base of Q ₅ and Q ₉ .

Therefore, the output of the differential pair of Q ₉ and Q ₁₀ is f in Figure 10 on the collector side of Q ₉ , and the output of the differential pair of Q ₄ and Q ₅ is g on the collector side of Q ₅ . It is. These outputs are summed at _R6 via a differential pair of _Q2 and _Q3 and a differential pair of _Q7 and _Q8 . Q ₂ and Q ₃ , and
The base difference voltage between Q ₇ and Q ₈ is applied from the phase detection voltage input terminal 23 and changes the addition ratio of g and f. The differential pair of Q ₂ and Q ₃ , the differential pair of Q ₇ and Q ₈ , and R ₆ correspond to the adder 35 in FIG.

The output of adder 35 is passed through the EF of _Q12 to _R12 and _C2
The signal is guided to the first -45° phase shift circuit 31, which is comprised of the following.

On the other hand, among the outputs of the differential pair of _Q9 and _Q10 , the collector side of _Q10 is e in FIG. 10, and is led to the first converter 6 through the EF of _Q18 . Also Q ₂
Of the outputs of the differential pair of Q4 and _Q3 , the collector side of _Q4 is h in FIG. 10, and this is led to the second converter 12 through the EF of _Q16 .

The operation of the first converter 6 is to convert the (47-1/8) _{H signal} from the input terminal 20 in the PAL system and (47 + 1/4) _H signal in the NTSC system to the differential pair of Q ₂₄ and Q ₂₅ and the Q ₂₆ By switching in _SC with a _differential pair _of
The method is to multiply (47+1/4) _H and _SC . The multiplication output is the collector of Q ₂₅ and Q ₂₇ of R ₂₂
is connected to the output terminal 22.

The second converter 12 also operates in the same manner as the first converter 6, but the input terminal 2
The signal from 1 is relative to the signal from input terminal 20.
It is a signal delayed by 90 degrees, and the input _SC is the second signal.
In the converter 12, the first converter 6
It is advanced by 90°.

The outputs of the second converter 12 are Q ₂₉ and Q ₃₁
Connect the collector of _R22 to output terminal 22.
Therefore, the sum of the outputs of the first and second converters 6 and 12 is output to the output terminal 22. Therefore, the output terminal 22 corresponds to the output of the adder 13 in FIG.

BPF8 is (47−1/8) _H in _SC and PAL systems,
In the NTSC system, the sum frequency of (47 + 1/4) _H is used as the passband, and this may naturally have a loose selectivity characteristic.

This concludes the explanation of FIG. 2, but the second oscillator 19 used in the present invention is not limited to the example shown in FIG.

For example, a configuration like a to c, d in Figure 9
A VCO can also be used. In Figure 9, 5
0 is a +45° phase shift circuit, 51 is a -90° phase shift circuit, 52 is a phase inversion circuit, 53, 54, and 55 are adders, 61 and 62 each have a phase difference of 90°, and 61 is advanced. 62 is an output terminal for the delayed signal.

The operations of these VCOs can be easily estimated from the example shown in FIG. 2, so their explanation will be omitted here. Each
By guiding the output terminals 61 and 62 of the VCO to the second converter 12 and the first converter 6 shown in FIG. 2, the same effect as in the example shown in FIG. 2 can be obtained.

As described above, the present invention provides the first oscillator 16
By switching the frequency of
The frequency offset required for each PAL system is generated, the 90 degree phase difference is added vectorially to the second oscillator 19, and the oscillation frequency is controlled by changing the addition ratio. The above effect can be obtained by configuring a PLL loop by controlling the addition ratio using a signal.

In other words, the frequency of the first oscillator 16 is not limited to (47 + 1/4) _H in the NTSC system and (47 - 1/8) _H in the PAL system, but can be used in combination with the switching method of the phase switching circuit 18 to change the recording color signal. Frequency is NTSC
The PAL method satisfies the conditions of ``having a frequency difference of 1/2 <sub>H</sub> between tracks'' and ``having an offset of 1/4 _{H '} ';
Any frequency may be used as long as it satisfies the following conditions: "Have a frequency difference of 1/8 H" and "Have an offset of 1/8 _H ".

Furthermore, the configuration of the second oscillator 19 does not need to be limited to the above-mentioned configuration;
The present invention can be implemented in any device that generates a signal.

〔Effect of the invention〕

According to the present invention, the −90° phase can be realized without complicating the logic circuit and without increasing the number of circuits by sharing the second oscillator with the VCO for phase detection and killer detection. Since the transition circuit can be eliminated, the number of pins on the IC can be saved,
In addition, sufficient arithmetic filter performance can be demonstrated for both PAL/NTSC formats.

Furthermore, when implementing these circuits into an IC, as shown in the embodiment, the second oscillator and sub-converter can be directly connected within the IC, eliminating the need for an increase in the number of pins and the need for external circuits. Naturally, the effect is even greater because the second oscillator, phase detector, and killer detector can be directly connected within the IC.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional carrier generation device, FIG. 2 is a block diagram showing an embodiment of the carrier generation device according to the present invention, and FIG. A block diagram showing a specific example, FIG. 4 is an explanatory diagram showing the control signal to the signal switching circuit 3 in PAL mode, FIG. 5 is an explanatory diagram showing the control signal to the signal switching circuit 3 in NTSC mode, and FIG. 6 is a block diagram showing a specific example of a circuit for generating the control signals shown in FIGS. 4 and 5, and FIG. 7 is a specific example of the second oscillator and the first and second converters of the present invention. The circuit diagrams shown in FIGS. 8 and 10 are as follows:
FIG. 9, a vector diagram for explaining the operation of the second oscillator in the present invention, is a block diagram showing another example of the second oscillator used in the present invention. 16...First oscillator generating at 375 _H /378 _H , 19... Second oscillator, 6... First converter, 12... Second converter, 26...
1/375/1/378 frequency divider.

Claims (1)

[Claims] 1. A first device that oscillates at a frequency that is an integral multiple of the horizontal frequency.
oscillator, a frequency divider that divides the oscillation output of the first oscillator by 8 and generates four divided outputs with phases different by 90 degrees, and two input terminals, which are supplied to the input terminals. Select first and second frequency converters that generate an output signal having a frequency equal to the sum of the frequencies of two input signals, and two divided outputs whose phases differ by 90 degrees from among the four divided outputs. , supplying the selected one of the divided outputs to the first frequency converter;
a switching circuit that supplies the selected other frequency-divided output to a second frequency converter; A second oscillating output that generates two oscillation outputs.
an oscillator, supply means for supplying one oscillation output of the second oscillator to the first frequency converter and supplying the other oscillation output to the second frequency converter; 1. A carrier signal generation circuit comprising: an addition circuit for adding the output of a frequency converter.