JPS5947838A - Ladder type digital-analog converter - Google Patents

Abstract

PURPOSE:To enable a digital signal to hold the states of 2N, by uniforming approximately an input range of an input analog voltage to a value of each digital signal and forming the titiled converter so as to hold a digital signal of all ''0''. CONSTITUTION:The titled converter consists of signal input terminals 11a, 11b, 11c inputting digital signals b2, b1, b0 to be converted respectively, a signal output terminal 12 outputting a converted analog voltage V0 and an R-2R resistor circuit network 13. The resistor circuit network 13 constitutes a 5-digit R-2R resistor circuit network, and input terminal of each digit is connected successively from the most significant digit to the signal input terminals 11a, 11b, 11c and the digital signals b2, b1 and b0 to be converted are inputted sequentially. A voltage of VDD corresponding to level ''1'' of the digital signal is applied to the input terminal of the resistor circuit of the low-order two-digit.

Description

Detailed Description of the Invention (a) Technical Field The present invention relates to a ladder-type 1)A converter composed of an R-2R low resistance path network, and is particularly suitable for a -AD converter.
Regarding converters.

(B) Background Art In general, as shown in FIG. 1, an AD converter mainly includes a comparator (1), a 7-lip flop (2), a clock oscillator (3>, a counter (4), and an IIj to D converter: (Mystery 5) Analog to be converted [II, Moon-V
The output voltage cat of the I and DA converter (5) is commonly connected to the inverting input terminal of the J tube regulator (1) and the non-inverting input S window (/
(: Input.

Then, first, when the conversion start signals 3T and 1I are generated, the counter (4) and the free clock (2) are set, and the clock oscillator (3) starts oscillating.
The counter (4) counts clock pulses CL to L, and the contents of the counter increase. The output digital signal of this counter (4). bll) 2 is the DA converter (5).
This output voltage V is converted into a 1G voltage. is the input anor
[When the cog voltage Vt is slightly exceeded, the comparator
The output C of 1) becomes rHj, and the furinone norotube (2)
Seven throats.

Therefore, the Q output becomes r i [l and rc, and the oscillation of the clock oscillator (3) stops, and the content of the force 1 nonta (4) is
Output voltage V of the DA converter (5). and input analog 'Il
l: Stop when the pressures Vi become approximately equal. That is, digital light No. 1 corresponding to the input analog voltage (2) is obtained as the output Do of the counter (4). 12 in the AD converter, the contents of the counter (4) are all r-I J
If an analog voltage V higher than the output voltage of the DA converter (5) is input when In order to prevent this, the clock oscillator (3) is normally stopped from oscillating when the counter (4) reaches all 1s. I have to. That is,
In FIG. 1, the output signal b2b of the counter (4),
l). An AND gate (6) is provided that inputs all of
Detects that the output G has become OTI, gate (
The oscillation of the clock oscillator (3) is stopped by inputting the signal to the set terminal S of the Flinob flop (2) via the clock oscillator (3).

As described above, a DA converter is generally used in a human converter, and a ladder type DA converter is often used as the DA converter.

As shown in Fig. 2, the conventional ladder-type DA converter has R-2, which has the same number of pits as the manually input digital signal.
It is composed of R low resistance road network (8), (9a) (9
b) (9c) is digital signal b21), l) n'u
Signal output terminal for human input, 0 (My heart is changed 44"!: J-received jll gummy ■. Outputs 1" output ψiM child A")
4). The conventional ladder type D A converter shown in No. 21Y1 has input digital signals b2b, bo etc. output 1L.
Pressure to r. I + y old with 1 (4, Figure 3) indicated by a black circle 1
- characteristic, and when the digital signal is 0, the output voltage is V. is O, and as the digital signal increases, V
nn/2"-Vat, /8 output '11' pressure V.

increases.

This figure 2 shows a conventional ladder-type 1H converter.
Applied to the AD converter in Figure 1-'Xi roto, human power j-, I
The relationship between the blowfish voltage Vi and the converted digital No. 411, that is, the outputs b2b and bo of the counter (4) (,
11.The characteristics are shown in Figure 1. That is, the input ′′l−
i: Pressure v, ;7)'; o < Vt <”, Vn
In the range n/8, first, the output of the counter (4) is 10
00'' and the output voltage V. is 01. Therefore, the counter (4) increases and becomes [00jl and i (at this time, the output voltage V becomes higher than the input voltage Vi (・Vnn/8), so the count stops and the digital signal l-Of)
Converted to IJ. Also, VDn/8 < Vi
In the range < 2Van /8, the counter (4) is ro
01J, the output 'tlf and the pressure V. is Vno/
8, the counter (4) increases and becomes [oiol, and at this time, the output voltage is 2VoD higher than the input voltage.
/8, so the count stops and the digital signal "
o Converted to 10J.

In this way, the input analog voltage ■ is converted into a corresponding digital signal. and 7VI). /8<Vi<Vn
In the range of n, the output voltage V. is higher than the input analog voltage ■ (although it never becomes), the oscillation of the clock oscillator (3) stops when the counter (4) becomes all 1, so the input analog voltage ■ in this range is higher than the digital signal rl
11J.

As mentioned above, as shown in FIG. 4, when a conventional ladder-type DA converter is used as an AD converter, the digital signals [1,
The input range of the input analog voltage Vi that is converted to 11J is approximately twice the input range that is converted to other digital signals, and there is also a drawback that ro 00J cannot be obtained as the conversion output. . Furthermore, the number of stages of the counter is N stages (N: an integer) and the state can be 2N, so the conversion output is 2N-1 (1 or 1).
Is it a disadvantage that it is difficult to move? A; 1, 1
,.

(C) Object of the Invention The present invention solves the above-mentioned drawbacks by using an AD converter to convert analog voltage v into a digital signal.
The number of bits of the digital signal as the conversion output can be reduced by making the input range of 1 almost uniform for each digital signal value and making it possible to take an all-0 digital signal as the conversion output. N (N: integer)
The purpose of this invention is to bring the digital signal into the 2N state as shown in (4) and (b) above, and to provide a new A converter to achieve this objective. It is something.

2) Embodiment FIG. 5 is a circuit diagram showing an embodiment of the &'L L type [)A converter according to the present invention. +″, input terminals (Ila) (llb) (Ilc), and a signal output terminal @ which outputs the converted analog fci, pressure V.
1. -2 It is composed of a resistance network 01.

This R-21it resistor network (Exhibit A1, the conventional R-21it resistor network in Figure 2)
, -2R low resistance path network and 1 line, and 2 more digits of R-2R low resistance paths are added after the lowest digit. The R-2n resistor network has more digits than the number of bits "3", that is, 5 digits.The input terminal of each digit of the It-21 resistor circuit network is connected to the signal input terminal (1 ], a)
(111)) (IIC) are connected in order from the most significant digit, and the digital signals to be converted, S, B, B, are sequentially input. Signal input terminal (1, 1a) (llb) (
The input terminals of the lower two digit resistance circuits that are not connected to Ilc) and to which the digital signals to be converted are not input, that is, the input terminals of the additional resistance circuits, have the voltage of Vnn corresponding to the "1" level of the digital signal. is supplied.

Therefore, the input digital signal bIbo is 1000.
When , the output voltage V. is (2+2)VI, , /2 =
3'v,,l,/32, and hereafter the digital signal S,blb.

+7) For increasing Te, output voltage v. HavI, D/23=
The input digital signal increases by VDD/8, b,
The relationship between bo and the output voltage VO is as shown by the white circle in FIG.

Therefore, as shown in FIG.
When applied to the AD converter shown in the figure, the output b of the counter (4)
2b, bo is 1-ooo, the output is 1-ooo, J is 3 V, D/32, so if the input range of input analog voltage ■1 is O〈■i〈3VDo/32, then 1b, voltage ■ 1 is converted to "000-l. Also, when the output of the counter (4) is 1-00, the output voltage ■1 is (2"V, , -
1-3vnn)/32-VDn/8 +3 ■,,n/
32, so the input analog voltage ~l is 3Vl, n/3
1'13' higher than 2 by Yon/8, 0 within the pressure range
12. Voltage ■ is converted to "001". Similarly, when the input analog voltage (2) increases by Vnn/8, the digital signal increases step by step. Then, when the output of the counter (4) is ``110j'', it is the output type, Sho V.
o is (2'+, 2'+ 3) V,,l,/32
= 27V,,, /32 and Lenote, 27 VDT, /
32 The input analog voltage ■ in the range (vt < V, ,, /32, which is a value close to Vnn/8. That is, the ladder type T)A converter shown in FIG.
When applied to a D converter, the relationship between the human input analog voltage V and the converted digital signal is as shown in FIG. A digital signal converted to can have 23 states. Furthermore, l-00
The input range of the input analog voltage (2) converted into 0J and "111" is approximately equal to the input range of the input analog voltage (2) converted into other digital signals.

In the embodiment shown in FIG. 5, the case where the input digital signal is 3 bits and two digit R-2R low resistance paths are added is explained, but the effect of the present invention becomes even more remarkable when there are many input digital signals. Become. For example, if the input digital signal is 6
In the case of bits, the input digital signal bs b+ bs
When bt l) + t) o are all 0, the output voltage is (2° + 2') VDI, / 2' = 3 V
DIll/256, so in the AD converter,
Input analog voltage converted to all 0s and all 1s■
The difference between the input range and the input range that is converted to other digital signals is only Von/256.

That is, each input range of the input analog voltage Vt converted into each digital signal becomes more uniform, and the error thereof becomes practically negligible. In addition, the It, -2 and resistance circuits added after the lowest digit are of course limited to 2 digits (12), and if the number of digits is increased, the error will be further reduced () (E) Effect Ladder shape according to the present invention 1) A-change 4-V spiral ↓, ``Double series'' (with a very simple circuit configuration, if applied to an AD converter, the digital signal of C as the conversion output All 0
Therefore, if the number of bits of the digital signal as a conversion output is N, it is possible to make the digital signal take on 2'' states. Furthermore, it is possible to make the input ranges of the analog input voltage and the input voltage for each digital signal substantially uniform.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a general AD converter.
Figure 2 is a circuit diagram showing a conventional ladder type 1) A converter;
FIG. 3 is a characteristic diagram showing the relationship between the input digital signal and the output voltage of the ladder-type DA converter of FIG. 2 and No. 5.
Figure 134 Beams 1 and 2 (:l' l, go-sha J)
Characteristic diagram showing the relationship between the human power analog electric ratio and the output digital signal, Figure 5A (Invention 4tr-, , l, ro(1(
, a circuit diagram showing an example of a ladder-type DA converter, Figures 1 and 6,
, 1) ψ, is a characteristic diagram showing the relationship between input analog voltage and output digital signal when applied to a converter.
, Explanation of main figure numbers (1)...Comparator, (2)...Flymblong, (3)...Clock oscillator, (4)...Counter, (F))...T ) A converter, (6)...A
ND gate, (7)...OR gate, (clear...R-
211 resistor network, (9a) (9b) (9c) (]1.
a) (11, b) (], ic)...Signal input terminal, 0 (force θ?...Signal output terminal. Applicant Sanyo Electric Co., Ltd. and one other representative Patent attorney Shizuo Sano No. 1 Figure T Figure 2 00110011 (---b. 01010101 m1%---b0

Claims (1)

[Claims] 1) In a ladder-type DA converter composed of an R-2R low resistance path network, the R-2R resistance network is connected to an R, -211, number of digits greater than the number of focuses of the input digital signal.
The digital signal is input into R-21' from the input terminal of the most significant digit of the resistance circuit network, and the input terminal of the digital signal is inputted to the input terminal of the lower digit to which the digital signal is not input. A DA converter that supplies a voltage corresponding to the "1" level.