CN111628772A - High-speed high-precision time domain analog-to-digital converter - Google Patents
High-speed high-precision time domain analog-to-digital converter Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
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Abstract
The invention discloses a high-speed high-precision time domain analog-to-digital converter, which comprises: a Flash module (1) for generating a reference voltage; the VTC module (2) is connected with the Flash module (1) and is used for sampling an input voltage signal VIN and processing the input voltage signal VIN according to the reference voltage to obtain a first time signal; the interpolation module (3) is connected with the VTC module (2) and is used for subdividing the first time signal to obtain a second time signal; the time domain comparator module (4) is connected with the interpolation module (3) and is used for comparing the second time signal and outputting a thermometer code; and the digital decoding module (5) is connected with the time domain comparator module (4) and is used for converting the thermometer code into a binary code and outputting the binary code. The time domain analog-to-digital converter provided by the invention has the advantages that the speed of the ADC is improved, the power consumption is reduced, and the speed and the power consumption are controllable.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a high-speed high-precision time domain analog-to-digital converter.
Background
An Analog-to-digital converter (ADC) is a converter that converts an Analog quantity, which is compared with a standard quantity (or a reference quantity), into a discrete signal represented by a binary number. With the development of integrated circuit technology, higher requirements are put on the sampling rate and conversion precision of the ADC. In practice, the time domain ADC is a new ADC architecture that can realize a super-high speed ADC.
Conventional time domain ADCs mainly use a ring oscillator to directly quantize the input voltage into a time signal.
However, as the sampling rate increases, the oscillation frequency of the ring oscillator directly affects the accuracy and speed of the ADC; and due to the limitation of the sampling period, the quantization time of the maximum input voltage signal must be less than the quantization period of the ADC, which imposes a limitation on the amplitude of the input signal and the speed of the ADC.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a high-speed and high-precision time domain analog-to-digital converter. The technical problem to be solved by the invention is realized by the following technical scheme:
a high speed high accuracy time domain analog to digital converter comprising:
the Flash module is used for generating reference voltage;
the VTC module is connected with the Flash module and is used for sampling an input voltage signal VIN and processing the input voltage signal VIN according to the reference voltage to obtain a first time signal;
the interpolation module is connected with the VTC module and used for subdividing the first time signal to obtain a second time signal;
the time domain comparator module is connected with the interpolation module and used for comparing the second time signal and outputting a thermometer code;
and the digital decoding module is connected with the time domain comparator module and is used for converting the thermometer code into a binary code and outputting the binary code.
In an embodiment of the invention, the Flash module comprises two Flash sub-modules, each of the Flash sub-modules comprises resistors R0-Rn connected in series in sequence, one end of the resistor R0 is connected with a reference voltage HVREF, one end of the resistor Rn is connected with a reference voltage LVREF, a common end of the resistors Ri and Ri +1 is used as an output end to be connected with the VTC module, wherein resistance values of the resistors R0-Rn satisfy that R0-Rn-Rj/2, i is greater than or equal to0 and less than n, j is greater than or equal to0 and less than n, and i, j and n are integers.
In an embodiment of the invention, the VTC module includes two VTC sub-modules correspondingly connected to the Flash sub-module, each VTC sub-module includes n VTC units, wherein an input terminal of each VTC unit is correspondingly connected to a common terminal of the resistors Ri and Ri +1, and an output terminal of each VTC unit is connected to the interpolation module.
In one embodiment of the present invention, the VTC unit includes a capacitor C, a first switch Φ 1, a second switch Φ 2, a third switch Φ 3, a fourth switch Φ 4, a current source IX, and a first inverter INV1, wherein,
one end of the capacitor C is connected with a voltage input end VIN through the first switch phi 1, and the other end of the capacitor C is connected with a reference voltage input end VREF through the second switch phi 2;
the third switch Φ 3 is connected to a voltage terminal VCOM and a common terminal of the capacitor C and the first switch Φ 1;
the current source IX is connected with the common terminal of the capacitor C and the second switch phi 2 through the fourth switch phi 4;
the input end of the first inverter INV1 is connected to the common end of the capacitor C, the second switch Φ 2 and the fourth switch Φ 4, and the output end of the inverter INV is used as the output end of the VTC unit and is connected to the interpolation module.
In one embodiment of the present invention, the interpolation module includes two interpolation sub-modules connected to the VTC sub-module, each of the interpolation sub-modules includes n-1 interpolation units, wherein an input terminal of each interpolation unit is connected to an output terminal of two adjacent VTC units, and an output terminal of the interpolation unit is connected to the time domain comparator module.
In an embodiment of the present invention, the interpolation unit includes m cascaded interpolation subunits, an input end of the first-stage interpolation subunit is connected to output ends of two adjacent VTC units, and an output end of the m-th-stage interpolation subunit is connected to the time domain comparator module; wherein the m-th order interpolation subunit comprises 2m+1 interpolation circuits, m ≧ 1.
In one embodiment of the present invention, the interpolation circuit includes a second inverter INV2 and a third inverter INV3, wherein an output terminal of the second inverter INV2 is connected to an output terminal of the third inverter INV 3.
In an embodiment of the present invention, the time domain comparator module includes a plurality of time domain comparators, and an input terminal of each of the time domain comparators is correspondingly connected to an output terminal of the interpolation circuit.
In an embodiment of the present invention, the time domain comparator includes a D flip-flop DFF, wherein an input terminal and a clock signal output terminal of the D flip-flop are respectively connected to an output terminal of the interpolation circuit.
The invention has the beneficial effects that:
1. the high-speed high-precision time domain analog-to-digital converter provided by the invention replaces the traditional comparator in the flash structure by a novel VTC structure, improves the speed, reduces the power consumption and ensures that the speed and the power consumption are controllable;
2. the high-speed high-precision time domain analog-to-digital converter provided by the invention further improves the precision of the ADC by adopting the interpolation module.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a high-speed high-precision time-domain ADC according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a time domain ADC according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a single VTC unit provided by an embodiment of the present invention;
fig. 4 is a circuit structure diagram of a practical application of a VTC unit according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of an interpolation unit having two stages of interpolation sub-units according to an embodiment of the present invention;
FIG. 6 is a circuit diagram of a time domain comparator according to an embodiment of the present invention;
fig. 7 is a waveform diagram of a VX node simulation provided by an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a high-speed and high-precision time domain ADC according to an embodiment of the present invention, including:
a Flash module 1 for generating a reference voltage;
the VTC module 2 is connected with the Flash module 1 and used for sampling an input voltage signal and processing the input voltage according to the reference voltage to obtain a first time signal;
the interpolation module 3 is connected with the VTC module 2 and used for subdividing the first time signal to obtain a second time signal;
the time domain comparator module 4 is connected with the interpolation module 3 and used for comparing the second time signal and outputting a thermometer code;
and the digital decoding module 5 is connected with the time domain comparator module 4 and used for converting the thermometer code into a binary code and outputting the binary code.
Further, the Flash module 1 includes two Flash sub-modules, each of the Flash sub-modules includes resistors R0-Rn connected in series in sequence, one end of the resistor R0 is connected to a reference voltage HVREF, one end of the resistor Rn is connected to a reference voltage LVREF, a common end of the resistors Ri and Ri +1 is used as an output end to be connected to the VTC module 2, wherein resistance values of the resistors R0-Rn satisfy that R0-Rn-Rj/2, i is greater than or equal to0 and less than n, j is greater than or equal to0 and less than n, and i, j and n are integers.
In the present embodiment, when n is 16, 16 pairs of differential reference voltages VREFN0 to VREFN15 and VREFP0 to VREFP15 are generated by the two Flash sub-modules. Specifically, referring to fig. 2, fig. 2 is a circuit structure diagram of the time domain ADC according to the embodiment of the present invention.
In this embodiment, the VTC (Voltage to Time Converter) module 2 includes two VTC sub-modules correspondingly connected to the Flash sub-module, each VTC sub-module includes n VTC units, an input end of each VTC unit is correspondingly connected to a common end of the resistors Ri and Ri +1, and an output end of each VTC unit is connected to the interpolation module 3.
In the embodiment, the two Flash sub-modules generate 16 pairs of reference voltages, and correspondingly, the two VTC sub-modules are respectively provided with 16 VTC units which are respectively connected with the reference voltages VREFN 0-VREFN 15 and VREFP 0-VREFP 15 correspondingly.
Further, referring to fig. 3, fig. 3 is a schematic structural diagram of a single VTC unit according to an embodiment of the present invention, including: the VTC unit includes a capacitor C, a first switch Φ 1, a second switch Φ 2, a third switch Φ 3, a fourth switch Φ 4, a current source IX, and a first inverter INV1, wherein,
one end of the capacitor C is connected with a voltage input end VIN through the first switch phi 1, and the other end of the capacitor C is connected with a reference voltage input end VREF through the second switch phi 2;
the third switch Φ 3 is connected to a voltage terminal VCOM and a common terminal of the capacitor C and the first switch Φ 1;
the current source IX is connected with the common terminal of the capacitor C and the second switch phi 2 through the fourth switch phi 4;
the input end of the first inverter INV1 is connected to the common end of the capacitor C, the second switch Φ 2 and the fourth switch Φ 4, and the output end of the inverter INV is connected to the interpolation module 3 as the output end of the VTC unit.
Specifically, the two VTC sub-modules include 16 VTC cells, each VTC cell includes 1 open voltage input terminal VREF, 16 pairs of reference voltage input terminals VREF are correspondingly connected to 16 pairs of reference voltages VREFN0 to VREFN15 and VREFP0 to VREFP15, and the input voltage signals VIN and VIP respectively pass through the two VTC sub-modules and then output 16 pairs of time signals, that is, first time signals, one pair of which may be represented as to0 to 15.
In the present embodiment, the circuit operation principle of the VTC unit is as follows:
firstly, phi 1 and phi 2 are conducted, an input signal VIN (sampled signal) and VREF reference voltage generated by a flash resistor array are communicated with two sides of a capacitor, and the voltages of the left end and the right end of the capacitor are VIN and VREF respectively; then Φ 1 and Φ 2 are turned off, Φ 3 and Φ 4 are turned on, the voltage on the left side of the capacitor rapidly changes to VCOM, and since the charge on the capacitor cannot change abruptly, the voltage of the VX node also rapidly changes to VIN-VCOM to VREF- (VIN-VCOM), and at this time, the voltage of the VX node changes to VCOM + (VREF-VIN). Under the action of current source IX, the VX node voltage is uniformly dropped from VCOM + (VREF-VIN) to generate a ramp voltage, and when the voltage drops across the inverted threshold voltage of inverter INV, VTC outputs an upward voltage signal. It is worth mentioning that the current source IX may control the slope of the ramp signal, VCOM may control the start of the ramp signal, and VCOM and IX may control whether the ramp signal crosses the threshold voltage of the inverter in coordination. Compared with the traditional VTC structure, the structure is simple, controllability is improved, the structure can be combined with a flash structure, the functions of a sampling circuit, a comparator and the VTC can be achieved simultaneously, and the structure plays a positive role in improving the ADC speed and reducing the ADC power consumption.
Further, referring to fig. 4, fig. 4 is a circuit structure diagram of a practical application of a VTC unit according to an embodiment of the present invention, where turning on and off of the first switch Φ 1, the second switch Φ 2, the third switch Φ 3, and the fourth switch Φ 4 are implemented by transistors, and the current source IX is implemented by a Cascode (Cascode) current source. The VTC unit provided by the embodiment is easy to realize by a circuit and convenient for a user to select.
The high-speed high accuracy time domain ADC that this embodiment provided utilizes the fast advantage of flash ADC technical speed, utilizes neotype VTC structure to replace the traditional comparator in the flash structure, has improved speed and has reduced the consumption to make speed and consumption controllable. According to the invention, the level of an input signal is differenced with the output reference voltage of the flash resistor array, the error is raised to an input common mode voltage value, and a current source is turned on to discharge to generate slope signals with different starting points. The slope of the ramp signal is controlled by a current source, and the number of effective ramp voltages can be changed by changing the current. The inverter is changed into an ultra-high speed comparator, and the ramp signal does not cause the change of a subsequent circuit through a signal of which the level is not inverted by the inverter, so that the speed of the circuit is greatly improved, and the power consumption of the circuit is greatly reduced.
In addition, the VTC module utilizes a charge pump technology, controls the on and off of the switch, operates the voltage on the capacitor, realizes mathematical operation of input voltage, reference voltage and common mode voltage, and completes comparison of the input voltage and the output reference voltage of the resistor array. Different input voltages can generate a cluster of time signals with different charging starting points, and then output signals with different pulse widths are generated through the inverter, so that the conversion of the voltage signals to the time signals is completed. In addition, the slope of a ramp signal generated by the output end can be controlled by controlling the discharge current of the current source, so that the power consumption and the sampling rate of the ADC are controlled.
Further, the interpolation module 3 includes two interpolation sub-modules correspondingly connected to the VTC sub-module, each of the interpolation sub-modules includes n-1 interpolation units, wherein an input end of each of the interpolation units is correspondingly connected to output ends of two adjacent VTC units, and an output end of the interpolation unit is connected to the time domain comparator module 4.
Specifically, each interpolation submodule in the present embodiment includes 15 interpolation units.
Furthermore, the interpolation unit includes m cascaded interpolation subunits, an input end of the first-stage interpolation subunit is connected to output ends of two adjacent VTC units, and an output end of the m-th-stage interpolation subunit is connected to the time domain comparator module 4; wherein the m-th order interpolation subunit comprises 2m+1 interpolation circuits, m ≧ 1.
Specifically, the circuit principle of the interpolation subunit is as follows:
firstly, two input signals are interpolated for one time to obtain an interpolated signal between the two input signals, then the signal obtained by inverting the input signals and the intermediate signal obtained by the first interpolation are interpolated for the second time, so as to obtain 5 output signals with equal intervals, and then the third time and the fourth time … … are carried out to obtain 9 and 17 … … output signals with equal intervals.
In this embodiment, a cascade mode of 2-level interpolation subunits is adopted, and two input signals are interpolated twice to obtain 5 equally spaced output signals. Referring to fig. 5, fig. 5 is a circuit diagram of an interpolation unit having two stages of interpolation sub-units according to an embodiment of the present invention, wherein V1 to V5 represent 5 equally spaced signals output after interpolation, and then after 16 pairs of first time signals of the VTC module are subjected to fine quantization by the interpolation module, a total of 15 sets of 61 pairs of differential signals, that is, second time signals, are output.
Further, the interpolation circuit includes a second inverter INV2 and a third inverter INV3, wherein an output end of the second inverter INV2 is connected to an output end of the third inverter INV 3.
In the embodiment, the wider time signal quantized by VTC is subdivided by the interpolation circuit, so as to improve the accuracy of the overall ADC.
Further, the time domain comparator module 4 includes a plurality of time domain comparators, and an input end of each of the time domain comparators is correspondingly connected to an output end of the interpolation circuit.
Specifically, in the present embodiment, 61 pairs of differential signals are output by two interpolation submodules, and 61 time domain comparators are required.
In this embodiment, the time domain comparator may be implemented by using a D flip-flop. Specifically, referring to fig. 6, fig. 6 is a circuit diagram of a time domain comparator according to an embodiment of the present invention, where the time domain comparator includes a D flip-flop DFF, and an input terminal and a clock signal output terminal of the D flip-flop DFF are respectively connected to an output terminal of the interpolation circuit.
Specifically, the time domain differential signals DN and DP are respectively connected to the input terminal of the D flip-flop and the clock signal terminal, and when the rising edge of DN leads the rising edge of DP, because the D flip-flop is a clock rising edge trigger device, the rising edge of DN still has a low level when arriving, so the output DOUT of the D flip-flop is a low level, otherwise, the rising edge of DP leads DN, DOUT is a high level, thus realizing the function of the time domain comparator. The overall output of the comparator module is a thermometer code.
And finally, the thermometer code is translated into a binary code through a digital decoding module to be used as the integral output of the ADC.
In the present embodiment, the time domain difference signals DN and DP are the interpolation signals V1 and V2 … … outputted by the upper interpolation block.
In this embodiment, the phase relationship of the corresponding differential time signal is determined by the time domain comparator, the voltage relationship is obtained by comparing the phase relationship of the time signal, the voltage interval to which the voltage value of the input signal belongs is determined, and the corresponding digital code is output by the digital decoding module, so that the conversion from the analog signal to the digital signal is completed, and the function of the ADC is realized.
Example two
To further illustrate the effect of the present invention, simulation experiments are performed on the time-domain ADC provided in fig. 2 in the first embodiment. Referring to fig. 7, fig. 7 is a waveform diagram of a VX node simulation provided by an embodiment of the present invention.
In this embodiment, for a clearer observation, only 6 outputs of VTC16 outputs, in which the ramp signal is around the threshold voltage of the inverter, are taken. As can be seen from the simulation waveforms in fig. 7, during the Φ 3 (or Φ 4) phase, except vo4 and vo5, none of the ramp signals crosses the threshold voltage of the inverter at the Φ 3 phase, and only the to4 and the to5 of the corresponding inverter output flip in level at the Φ 3 phase. During the Φ 3 phase, the signals to4 are all low, and the signals to5 are all high. Therefore, the VTC circuit generates a 01 jumping point and a time signal which are closely related to an input signal, and the 01 jumping point can be generated by adding a thermometer code decoding circuit behind the 01 jumping point for decoding to form a complete ADC circuit and generate a quantized digital code; the generated time signal can be added into a time domain interpolation circuit later to perform further fine quantization, thereby realizing a higher-precision ADC. It is worth mentioning that the novel VTC structure provided by the invention has a very positive effect on realizing ADC with higher precision, firstly, the novel VTC structure is combined with a flash structure to carry out preliminary quantization to obtain 4-bit quantized digital codes, secondly, the structure can screen useful signals, and input signals can be quantized into a very wide time signal, so that the precision upper limit of the whole ADC is greatly improved, and the circuit power consumption is reduced.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (9)
1. A high-speed, high-accuracy time-domain analog-to-digital converter, comprising:
a Flash module (1) for generating a reference voltage;
the VTC module (2) is connected with the Flash module (1) and is used for sampling an input voltage signal VIN and processing the input voltage signal VIN according to the reference voltage to obtain a first time signal;
the interpolation module (3) is connected with the VTC module (2) and is used for subdividing the first time signal to obtain a second time signal;
the time domain comparator module (4) is connected with the interpolation module (3) and is used for comparing the second time signal and outputting a thermometer code;
and the digital decoding module (5) is connected with the time domain comparator module (4) and is used for converting the thermometer code into a binary code and outputting the binary code.
2. The high-speed high-precision time-domain analog-to-digital converter according to claim 1, wherein the Flash module (1) comprises two Flash sub-modules, each Flash sub-module comprises resistors R0-Rn connected in series in sequence, one end of the resistor R0 is connected with a reference voltage HVREF, one end of the resistor Rn is connected with a reference voltage LVREF, a common end of the resistors R0-Rn +1 is used as an output end to be connected with the VTC module (2), wherein the resistances of the resistors R0-Rn satisfy the relationship that R0 ═ Rn ═ Rj/2, i is greater than or equal to0 and less than n, j is greater than or equal to0 and less than n, and i, j and n are integers.
3. A high-speed high-precision time domain analog-to-digital converter according to claim 2, wherein the VTC module (2) comprises two VTC sub-modules connected with the Flash sub-module, each VTC sub-module comprises n VTC units, wherein an input terminal of each VTC unit is connected with a common terminal of the resistors Ri and Ri +1, and an output terminal of each VTC unit is connected with the interpolation module (3).
4. A high-speed high-precision time-domain analog-to-digital converter according to claim 3, characterized in that the VTC unit comprises a capacitor C, a first switch Φ 1, a second switch Φ 2, a third switch Φ 3, a fourth switch Φ 4, a current source IX, and a first inverter INV1, wherein,
one end of the capacitor C is connected with a voltage input end VIN through the first switch phi 1, and the other end of the capacitor C is connected with a reference voltage input end VREF through the second switch phi 2;
the third switch Φ 3 is connected to a voltage terminal VCOM and a common terminal of the capacitor C and the first switch Φ 1;
the current source IX is connected with the common terminal of the capacitor C and the second switch phi 2 through the fourth switch phi 4;
the input end of the first inverter INV1 is connected with the common end of the capacitor C, the second switch Φ 2 and the fourth switch Φ 4, and the output end of the inverter INV is used as the output end of the VTC unit and is connected with the interpolation module (3).
5. A high-speed high-precision time-domain analog-to-digital converter according to claim 4, characterized in that the interpolation module (3) comprises two interpolation sub-modules connected with the VTC sub-module, each of the interpolation sub-modules comprises n-1 interpolation units, wherein the input end of each interpolation unit is connected with the output end of two adjacent VTC units, and the output end of the interpolation unit is connected with the time-domain comparator module (4).
6. A high-speed high-precision time-domain analog-to-digital converter according to claim 5, wherein the interpolation unit comprises m cascaded interpolation sub-units, wherein the input end of the first-stage interpolation sub-unit is connected with the output end of the corresponding adjacent two VTC units, and the output end of the m-th-stage interpolation sub-unit is connected with the time-domain comparator module (4); wherein the m-th order interpolation subunit comprises 2m+1 interpolation circuits, m ≧ 1.
7. The high speed, high precision time domain analog to digital converter of claim 6, wherein the interpolation circuit comprises a second inverter INV2 and a third inverter INV3, wherein an output of the second inverter INV2 is connected to an output of the third inverter INV 3.
8. A high-speed high-precision time-domain analog-to-digital converter according to claim 6, wherein said time-domain comparator module (4) comprises a plurality of time-domain comparators, and the input end of each of said time-domain comparators is correspondingly connected with the output end of said interpolation circuit.
9. The high-speed high-precision time-domain analog-to-digital converter according to claim 8, wherein the time-domain comparator comprises a D flip-flop DFF, wherein an input end and a clock signal output end of the D flip-flop are respectively connected to an output end of the interpolation circuit.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112702062A (en) * | 2020-12-28 | 2021-04-23 | 华南理工大学 | Multi-bit analog-to-digital converter capable of effectively reducing power consumption |
| CN113556122A (en) * | 2021-06-08 | 2021-10-26 | 西安电子科技大学 | High-speed high-linearity voltage-time converter applied to time domain analog-to-digital converter |
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| CN113556122B (en) * | 2021-06-08 | 2023-03-10 | 西安电子科技大学 | High-speed high-linearity voltage-time converter applied to time domain analog-to-digital converter |
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