CN111628772A - High-speed and high-precision time-domain analog-to-digital converter - Google Patents

Abstract

The invention discloses a high-speed and high-precision time-domain analog-to-digital converter, comprising: a Flash module (1) for generating a reference voltage; a VTC module (2) for connecting to the Flash module (1) for adjusting an input voltage The signal VIN is sampled and the input voltage signal VIN is processed according to the reference voltage to obtain a first time signal; an interpolation module (3), connected to the VTC module (2), is used to subdivide the first time signal a time signal to obtain a second time signal; a time domain comparator module (4), connected to the interpolation module (3), for comparing the second time signal and outputting a thermometer code; a digital decoding module (5) ), connected to the time domain comparator module (4), for converting the thermometer code into binary code and outputting it. The time domain analog-to-digital converter provided by the invention improves the speed of the ADC, reduces the power consumption, and makes the speed and power consumption controllable.

Description

High-speed and high-precision time-domain analog-to-digital converter

technical field

The invention belongs to the technical field of integrated circuits, and in particular relates to a high-speed and high-precision time-domain analog-to-digital converter.

Background technique

An analog-to-digital converter (Analog to Digital Converter, ADC) is a converter that converts an analog quantity processed by comparison with a standard quantity (or reference quantity) into a discrete signal represented by a binary value. With the development of integrated circuit technology, higher requirements are put forward for the sampling rate and conversion accuracy of ADC. In practice, the time-domain ADC is a new ADC architecture that enables ultra-high-speed ADCs.

Traditional time-domain ADCs mainly use ring oscillators to directly quantize the input voltage into a time signal.

However, with the increase of the sampling rate, the oscillation frequency of the ring oscillator directly affects the accuracy and speed of the ADC; and due to the limitation of the sampling period, the quantization time of the maximum input voltage signal must be less than the quantization period of the ADC. The signal amplitude and the speed of the ADC create limitations.

SUMMARY OF THE INVENTION

In order to solve the above problems existing in the prior art, the present invention provides a high-speed and high-precision time-domain analog-to-digital converter. The technical problem to be solved by the present invention is realized by the following technical solutions:

A high-speed, high-precision time-domain analog-to-digital converter, comprising:

Flash module, used to generate reference voltage;

The VTC module is connected to the Flash module for sampling the input voltage signal VIN and processing the input voltage signal VIN according to the reference voltage to obtain a first time signal;

an interpolation module, connected to the VTC module, for subdividing the first time signal to obtain a second time signal;

a time domain comparator module, connected to the interpolation module, for comparing the second time signal and outputting a thermometer code;

The digital decoding module is connected to the time domain comparator module, and is used for converting the thermometer code into binary code and outputting it.

In an embodiment of the present invention, the Flash module includes two Flash sub-modules, each of the Flash sub-modules includes resistors R0 to Rn connected in series in sequence, one end of the resistor R0 is connected to the reference voltage HVREF, and the resistor R0 is connected to the reference voltage HVREF. One end of Rn is connected to the reference voltage LVREF, and the common end of the resistors Ri and Ri+1 is used as an output end to connect to the VTC module, wherein the resistances of the resistors R0 to Rn satisfy R0=Rn=Rj/2, 0≤ i<n, 0<j<n, i, j, and n are all integers.

In an embodiment of the present invention, the VTC module includes two VTC sub-modules correspondingly connected to the Flash sub-module, each of the VTC sub-modules includes n VTC units, wherein each of the VTC units The input end of the VTC unit is correspondingly connected to the common end of the resistors Ri and Ri+1, and the output end of each VTC unit is connected to the interpolation module.

In an embodiment of the present invention, the VTC unit includes a capacitor C, a first switch Φ1, a second switch Φ2, a third switch Φ3, a fourth switch Φ4, a current source IX and a first inverter INV1, wherein,

One end of the capacitor C is connected to the voltage input terminal VIN through the first switch Φ1, and the other end of the capacitor C is connected to the reference voltage input terminal VREF through the second switch Φ2;

The third switch Φ3 is connected to the voltage terminal VCOM and the common terminal of the capacitor C and the first switch Φ1;

The current source IX is connected to the common terminal of the capacitor C and the second switch Φ2 through the fourth switch Φ4;

The input terminal of the first inverter INV1 is connected to the common terminal of the capacitor C, the second switch Φ2 and the fourth switch Φ4, and the output terminal of the inverter INV is used as the output of the VTC unit The terminal is connected to the plug-in module.

In an embodiment of the present invention, the interpolation module includes two interpolation sub-modules correspondingly connected to the VTC sub-module, and each of the interpolation sub-modules includes n-1 interpolation units, wherein, The input end of each of the interpolation units is correspondingly connected to the output ends of two adjacent VTC units, and the output end of the interpolation unit is connected to the time domain comparator module.

In an embodiment of the present invention, the interpolation unit includes m cascaded interpolation subunits, and the input end of the first level interpolation subunit is connected to the output ends of the two adjacent VTC units correspondingly, The output end of the mth level interpolation subunit is connected to the time domain comparator module; wherein, the mth level interpolation subunit includes 2 ^m +1 interpolation circuits, and m≧1.

In an embodiment of the present invention, the interpolation circuit includes a second inverter INV2 and a third inverter INV3, wherein the output end of the second inverter INV2 and the third inverter The output of INV3 is connected.

In an embodiment of the present invention, the time-domain comparator module includes several time-domain comparators, and an input terminal of each time-domain comparator is correspondingly connected to an output terminal of the interpolation circuit.

In an embodiment of the present invention, the time domain comparator includes a D flip-flop DFF, wherein the input terminal of the D flip-flop and the clock signal output terminal are respectively connected to the output terminal of the interpolation circuit.

Beneficial effects of the present invention:

1. The high-speed and high-precision time-domain analog-to-digital converter provided by the present invention replaces the traditional comparator in the flash structure with a new type of VTC structure, improves the speed and reduces the power consumption, and makes the speed and power consumption controllable;

2. The high-speed and high-precision time-domain analog-to-digital converter provided by the present invention further improves the accuracy of the ADC by using an interpolation module.

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

Description of drawings

1 is a schematic structural diagram of a high-speed and high-precision time-domain ADC provided by an embodiment of the present invention;

2 is a circuit structure diagram of a time domain ADC provided by an embodiment of the present invention;

3 is a schematic structural diagram of a single VTC unit provided by an embodiment of the present invention;

4 is a schematic diagram of a practical application circuit of a VTC unit provided by an embodiment of the present invention;

5 is a circuit diagram of an interpolation unit with two-level interpolation subunits provided by an embodiment of the present invention;

6 is a circuit diagram of a time domain comparator provided by an embodiment of the present invention;

FIG. 7 is a VX node simulation waveform diagram provided by an embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

Example 1

Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a high-speed and high-precision time-domain ADC provided by an embodiment of the present invention, including:

Flash module 1, used to generate reference voltage;

The VTC module 2 is connected to the Flash module 1 for sampling the input voltage signal and processing the input voltage according to the reference voltage to obtain a first time signal;

an interpolation module 3, connected to the VTC module 2, for subdividing the first time signal to obtain a second time signal;

a time domain comparator module 4, connected to the interpolation module 3, for comparing the second time signal and outputting a thermometer code;

The digital decoding module 5 is connected to the time domain comparator module 4, and is used for converting the thermometer code into binary code and outputting it.

Further, the Flash module 1 includes two Flash sub-modules, each of the Flash sub-modules includes resistors R0 to Rn connected in series in sequence, one end of the resistor R0 is connected to the reference voltage HVREF, and one end of the resistor Rn is connected to the reference voltage voltage LVREF, the common terminal of the resistors Ri and Ri+1 is used as an output terminal to connect the VTC module 2, wherein the resistances of the resistors R0 to Rn satisfy R0=Rn=Rj/2, 0≤i<n, 0<j<n, i, j, and n are all integers.

In this embodiment, if n=16, 16 pairs of differential reference voltages VREFN0-VREFN15 and VREFP0-VREFP15 are generated by two Flash sub-modules. Specifically, please refer to FIG. 2 , which is a circuit structure diagram of a time domain ADC provided by an embodiment of the present invention.

In this embodiment, the VTC (Voltage to Time Converter, voltage-to-time conversion) module 2 includes two VTC sub-modules correspondingly connected to the Flash sub-module, and each of the VTC sub-modules includes n VTC units, Wherein, the input end of each of the VTC units is correspondingly connected to the common end of the resistors Ri and Ri+1, and the output end of each of the VTC units is connected to the interpolation module 3 .

In this embodiment, the two Flash sub-modules generate 16 pairs of reference voltages. Correspondingly, the two VTC sub-modules are provided with 16 VTC units, which are respectively connected to the reference voltages VREFN0-VREFN15 and VREFP0-VREFP15.

Further, please refer to FIG. 3, which is a schematic structural diagram of a single VTC unit provided by an embodiment of the present invention, including: the VTC unit includes a capacitor C, a first switch Φ1, a second switch Φ2, a third switch Φ3, a Four switches Φ4, current source IX and first inverter INV1, wherein,

One end of the capacitor C is connected to the voltage input terminal VIN through the first switch Φ1, and the other end of the capacitor C is connected to the reference voltage input terminal VREF through the second switch Φ2;

The third switch Φ3 is connected to the voltage terminal VCOM and the common terminal of the capacitor C and the first switch Φ1;

The current source IX is connected to the common terminal of the capacitor C and the second switch Φ2 through the fourth switch Φ4;

The input terminal of the first inverter INV1 is connected to the common terminal of the capacitor C, the second switch Φ2 and the fourth switch Φ4, and the output terminal of the inverter INV is used as the output of the VTC unit The terminal is connected to the plug-in module 3 .

Specifically, the two VTC sub-modules include 16 VTC units, each VTC unit includes one open voltage input terminal VREF, and 16 pairs of reference voltage input terminals VREF are correspondingly connected to 16 pairs of reference voltages VREFN0 to VREFN15 and VREFP0 to VREFP15. The voltage signals VIN and VIP respectively pass through the two VTC sub-modules and output 16 pairs of time signals, that is, the first time signals, one of which can be represented as to0 to to15.

In this embodiment, the circuit working principle of the VTC unit is as follows:

First, Φ1 and Φ2 are turned on, the input signal VIN (sampled signal) and the VREF reference voltage generated by the flash resistor array are connected to both sides of the capacitor. At this time, the voltages at the left and right ends of the capacitor are VIN and VREF respectively; then Φ1 and Φ2 are disconnected, and Φ3 And Φ4 is turned on, and the voltage on the left side of the capacitor quickly becomes VCOM. Since the charge on the capacitor cannot be abruptly changed, the voltage of the VX node will also quickly change from VIN-VCOM to VREF-(VIN-VCOM). At this time, the voltage of the VX node The voltage change is VCOM+(VREF-VIN). Under the action of the current source IX, the VX node voltage drops uniformly from VCOM+ (VREF-VIN) to generate a ramp voltage. When the voltage drops across the inversion threshold voltage of the inverter INV, VTC will output an upward voltage signal. It is worth mentioning that the current source IX can control the slope of the ramp voltage signal, VCOM can control the falling starting point of the ramp signal, and the coordination between VCOM and IX can control whether the ramp signal crosses the inverter threshold voltage. Compared with the traditional VTC structure, this structure is simple and increases the controllability. It can be combined with the flash structure to function as a sampling circuit, a comparator, and a VTC at the same time, which can improve the speed of the ADC and reduce the power consumption of the ADC. to a very positive effect.

Further, please refer to FIG. 4, FIG. 4 is a circuit structure diagram of a practical application of a VTC unit provided by an embodiment of the present invention, wherein the first switch Φ1, the second switch Φ2, the third switch Φ3 and the fourth switch Φ4 Both turn-on and turn-off are realized by transistors, and the current source IX is realized by a Cascode (cascode structure) current source. The VTC unit provided in this embodiment is easy to implement in a circuit and is convenient for users to choose.

The high-speed and high-precision time-domain ADC provided by this embodiment takes advantage of the fast speed of the flash ADC technology, and replaces the traditional comparator in the flash structure with a new VTC structure, which improves the speed and reduces the power consumption, and makes the speed and power consumption. Controllable. The invention makes the difference between the input signal level and the output reference voltage of the flash resistor array, raises the error to the input common mode voltage value, and opens the current source for discharging to generate ramp signals with different starting points. The slope of the ramp signal is controlled by the current source, and changing the current size can change the number of valid ramp voltages. Here, the inverter is turned into an ultra-high-speed comparator. The signal whose ramp signal does not go through the inverter to flip the level will not cause changes in the subsequent circuit. This method not only greatly improves the speed of the circuit, but also greatly reduces the power consumption of the circuit.

In addition, the VTC module utilizes the charge pump technology to operate the voltage on the capacitor by controlling the on and off of the switch to realize the mathematical operation of the input voltage, reference voltage and common-mode voltage, and complete the comparison between the input voltage and the output reference voltage of the resistor array. . Different input voltages will generate a cluster of time signals with different charging starting points, and then output signals with different pulse widths will be generated through the inverter to complete the conversion from voltage signals to time signals. In addition, by controlling the discharge current of the current source, the slope of the ramp signal generated at the output can be controlled, thereby controlling the power consumption and sampling rate of the ADC.

Further, the interpolation module 3 includes two interpolation sub-modules correspondingly connected with the VTC sub-modules, each of the interpolation sub-modules includes n-1 interpolation units, wherein each of the interpolation sub-modules The input end of the interpolation unit is correspondingly connected to the output ends of two adjacent VTC units, and the output end of the interpolation unit is connected to the time domain comparator module 4 .

Specifically, in this embodiment, each interpolation sub-module includes 15 interpolation units.

Further, the interpolation unit includes m cascaded interpolation subunits, the input end of the first-level interpolation subunit is connected to the output ends of the adjacent two VTC units correspondingly, and the mth-level interpolation subunit is connected. The output end of the unit is connected to the time domain comparator module 4; wherein, the m-th level interpolation subunit includes 2 ^m +1 interpolation circuits, where m≧1.

Specifically, the circuit principle of the interpolation subunit is as follows:

First, the two input signals are interpolated once to obtain the interpolated signal in the middle of the two input signals, and then the second interpolation is performed between the signal passing through the input signal through the inverter and the intermediate signal obtained by the first interpolation, and thus 5 9, 17... output signals at equal intervals can be obtained after the third and fourth times....

In this embodiment, a cascaded manner of 2-level interpolation subunits is adopted, so that two input signals are interpolated twice to obtain 5 equally spaced output signals. Please refer to FIG. 5. FIG. 5 is a circuit diagram of an interpolation unit with two-stage interpolation subunits provided by an embodiment of the present invention, wherein V1 to V5 represent five equally spaced signals output after interpolation, then 16 of the VTC module After the first time signal is refined by the interpolation module, a total of 61 pairs of differential signals in 15 groups are output, that is, the second time signal.

Further, the interpolation circuit includes a second inverter INV2 and a third inverter INV3, wherein the output end of the second inverter INV2 is connected to the output end of the third inverter INV3.

In this embodiment, the wider time signal quantized by the VTC is subdivided by an interpolation circuit, so as to improve the accuracy of the overall ADC.

Further, the time domain comparator module 4 includes several time domain comparators, and the input end of each of the time domain comparators is correspondingly connected to the output end of the interpolation circuit.

Specifically, in this embodiment, 61 pairs of differential signals are output by two interpolation sub-modules, and 61 time-domain comparators are required.

In this embodiment, the time domain comparator can be implemented by using a D flip-flop. Specifically, please refer to FIG. 6. FIG. 6 is a circuit diagram of a time domain comparator provided by an embodiment of the present invention. The time domain comparator includes a D flip-flop DFF, wherein the input terminal of the D flip-flop and the clock signal output terminal are They are respectively connected to the output ends of the interpolation circuit.

Specifically, the time domain differential signals DN and DP are respectively connected to the input terminal of the D flip-flop and the clock signal terminal. When the rising edge of DN is ahead of the rising edge of DP, because the D flip-flop is a device that is triggered by the rising edge of the clock, DN rises When the edge comes, DP is still low level, so the output DOUT of the D flip-flop is low level, otherwise the rising edge of DP leads DN, and DOUT is a high level, thus realizing the function of the time domain comparator. The overall output of the comparator module is a thermometer code.

Finally, the thermometer code is decoded into binary code through the digital decoding module as the overall output of the ADC.

In this embodiment, the time domain differential signals DN, DP are multiple interpolation signals V1, V2, . . . output by the upper-level interpolation module.

In this embodiment, the time domain comparator is used to determine the phase relationship of the corresponding differential time signal, and the voltage relationship is obtained by comparing the phase relationship of the time signal, and then the voltage interval to which the voltage value of the input signal belongs is determined, and then the output signal is output through the digital decoding module. The corresponding digital code completes the conversion of analog signals to digital signals and realizes the function of ADC.

Embodiment 2

In order to further illustrate the effect of the present invention, a simulation experiment is performed on the time domain ADC provided in FIG. 2 in the first embodiment above. Referring to FIG. 7, FIG. 7 is a VX node simulation waveform diagram provided by an embodiment of the present invention.

In this embodiment, for clearer observation, only 6 outputs of the 16 outputs of the VTC whose ramp signals are near the threshold voltage of the inverter are taken. It can be seen from the simulation waveform in Figure 7 that, except for vo4 and vo5 during the Φ3 (or Φ4) phase, the other ramp signals will not cross the inverter threshold voltage in the Φ3 phase, and the corresponding inverter outputs are only to4 and to5. Level inversion occurs at the Φ3 phase. During the phase of Φ3, the signals above to4 are all low levels, and the signals below to5 are all high levels. So far, the VTC circuit has generated the 01 jump point and a time signal that are closely related to the input signal. The generation of the 01 jump point can be decoded by adding a thermometer code decoding circuit behind it to form a complete ADC circuit to generate quantization. The generated time signal can be added to the interpolation circuit in the time domain later for further refinement to achieve a higher-precision ADC. It is worth mentioning that the new VTC structure proposed by the present invention has a very positive effect on the realization of higher-precision ADCs. First, it combines the flash structure to perform preliminary quantization to obtain a 4-bit quantized digital code. Signal”, which quantizes the input signal into a wide time signal, which greatly increases the upper limit of the overall ADC accuracy and reduces circuit power consumption.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (9)

1. A high-speed, high-accuracy time-domain analog-to-digital converter, comprising:

a Flash module (1) for generating a reference voltage;

the VTC module (2) is connected with the Flash module (1) and is used for sampling an input voltage signal VIN and processing the input voltage signal VIN according to the reference voltage to obtain a first time signal;

the interpolation module (3) is connected with the VTC module (2) and is used for subdividing the first time signal to obtain a second time signal;

the time domain comparator module (4) is connected with the interpolation module (3) and is used for comparing the second time signal and outputting a thermometer code;

and the digital decoding module (5) is connected with the time domain comparator module (4) and is used for converting the thermometer code into a binary code and outputting the binary code.

2. The high-speed high-precision time-domain analog-to-digital converter according to claim 1, wherein the Flash module (1) comprises two Flash sub-modules, each Flash sub-module comprises resistors R0-Rn connected in series in sequence, one end of the resistor R0 is connected with a reference voltage HVREF, one end of the resistor Rn is connected with a reference voltage LVREF, a common end of the resistors R0-Rn +1 is used as an output end to be connected with the VTC module (2), wherein the resistances of the resistors R0-Rn satisfy the relationship that R0 ═ Rn ═ Rj/2, i is greater than or equal to0 and less than n, j is greater than or equal to0 and less than n, and i, j and n are integers.

3. A high-speed high-precision time domain analog-to-digital converter according to claim 2, wherein the VTC module (2) comprises two VTC sub-modules connected with the Flash sub-module, each VTC sub-module comprises n VTC units, wherein an input terminal of each VTC unit is connected with a common terminal of the resistors Ri and Ri +1, and an output terminal of each VTC unit is connected with the interpolation module (3).

4. A high-speed high-precision time-domain analog-to-digital converter according to claim 3, characterized in that the VTC unit comprises a capacitor C, a first switch Φ 1, a second switch Φ 2, a third switch Φ 3, a fourth switch Φ 4, a current source IX, and a first inverter INV1, wherein,

one end of the capacitor C is connected with a voltage input end VIN through the first switch phi 1, and the other end of the capacitor C is connected with a reference voltage input end VREF through the second switch phi 2;

the third switch Φ 3 is connected to a voltage terminal VCOM and a common terminal of the capacitor C and the first switch Φ 1;

the current source IX is connected with the common terminal of the capacitor C and the second switch phi 2 through the fourth switch phi 4;

the input end of the first inverter INV1 is connected with the common end of the capacitor C, the second switch Φ 2 and the fourth switch Φ 4, and the output end of the inverter INV is used as the output end of the VTC unit and is connected with the interpolation module (3).

5. A high-speed high-precision time-domain analog-to-digital converter according to claim 4, characterized in that the interpolation module (3) comprises two interpolation sub-modules connected with the VTC sub-module, each of the interpolation sub-modules comprises n-1 interpolation units, wherein the input end of each interpolation unit is connected with the output end of two adjacent VTC units, and the output end of the interpolation unit is connected with the time-domain comparator module (4).

6. A high-speed high-precision time-domain analog-to-digital converter according to claim 5, wherein the interpolation unit comprises m cascaded interpolation sub-units, wherein the input end of the first-stage interpolation sub-unit is connected with the output end of the corresponding adjacent two VTC units, and the output end of the m-th-stage interpolation sub-unit is connected with the time-domain comparator module (4); wherein the m-th order interpolation subunit comprises 2^m+1 interpolation circuits, m ≧ 1.

7. The high speed, high precision time domain analog to digital converter of claim 6, wherein the interpolation circuit comprises a second inverter INV2 and a third inverter INV3, wherein an output of the second inverter INV2 is connected to an output of the third inverter INV 3.

8. A high-speed high-precision time-domain analog-to-digital converter according to claim 6, wherein said time-domain comparator module (4) comprises a plurality of time-domain comparators, and the input end of each of said time-domain comparators is correspondingly connected with the output end of said interpolation circuit.

9. The high-speed high-precision time-domain analog-to-digital converter according to claim 8, wherein the time-domain comparator comprises a D flip-flop DFF, wherein an input end and a clock signal output end of the D flip-flop are respectively connected to an output end of the interpolation circuit.

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